1 1.3 garbled /* $NetBSD: README,v 1.3 2007/10/17 19:56:54 garbled Exp $ */ 2 1.2 briggs 3 1.1 briggs Overview 4 1.1 briggs 5 1.1 briggs This is a port to the Motorola "SandPoint" evaluation system. The 6 1.1 briggs SandPoint is the successor to the "Yellowknife" system. The system 7 1.1 briggs can be fitted with different PMCs (Processor Mezzanine Cards). This 8 1.1 briggs port is specifically for the rev X2 motherboard system with the PPC 9 1.2 briggs 8240 PMC rev X4 installed. It also works with the Altimus X2 PMC 10 1.2 briggs (MPC7400 with MPC107). 11 1.1 briggs 12 1.1 briggs All references (cf) listed here are for the MPC8240 Integrated Processor 13 1.1 briggs User's Manual. 14 1.1 briggs 15 1.2 briggs Information on the Sandpoint can be found on Motorola's web site: 16 1.2 briggs http://www.mot.com/SPS/PowerPC/teksupport/refdesigns/sandpoint.html 17 1.1 briggs 18 1.1 briggs 19 1.1 briggs SandPoint Hardware Configuration 20 1.1 briggs 21 1.1 briggs This port was developed on a Sandpoint X2 motherboard with a Unity X4 PMC. 22 1.1 briggs 23 1.1 briggs This port assumes that the jumpers are set as follows: 24 1.1 briggs S3/S4 - Mode 1: PMC w/o IDE (switches opposite, one nearest PCI 25 1.1 briggs slot toward near edge) 26 1.1 briggs S5 - Interrupt to PMC normal (switch toward near edge) 27 1.1 briggs S6 - Local I/O shared with slot 2 (switch toward near edge) 28 1.1 briggs 29 1.1 briggs Mode 0 (PMC w/ IDE) does not appear to work right with ISA interrupts. The 30 1.1 briggs interrupts from the Winbond chip do not appear at the PMC. 31 1.1 briggs 32 1.1 briggs On the PPMC, we assume a 100MHz clock. 33 1.1 briggs on PPMC: (C == closed, or "on") 34 1.1 briggs SW2: 35 1.1 briggs C ROM on PCI bus (DINK32 on mainboard) 36 1.1 briggs - Map "B": CHRP 37 1.1 briggs C Motorola PPMC 38 1.1 briggs C Wait for initialization (peripheral mode) 39 1.1 briggs - Program mode: Normal mode 40 1.1 briggs - Select normal ROM 41 1.1 briggs - 33 MHz only 42 1.1 briggs - COP only resets local CPU/MPC107 43 1.1 briggs SW3: 44 1.1 briggs -C--C PCI 33, Mem 66, PPC 266 45 1.1 briggs -- 0.5 - 0.9 ns PCI hold time 46 1.1 briggs C 25 ohm PCI drive strength 47 1.1 briggs 48 1.1 briggs 49 1.1 briggs Address Map 50 1.1 briggs 51 1.1 briggs For this port, we choose the "Address Map B" (CHRP-compatible) for the 52 1.1 briggs system (see SW2, #2, above): 53 1.1 briggs 54 1.1 briggs (Processor View) 55 1.1 briggs 0000 0000 0009 FFFF System Memory 56 1.1 briggs 000A 0000 000F FFFF Compatibility Hole (programmable to go to PCI space 57 1.1 briggs or system memory--programmed for system memory--cf 5.8) 58 1.1 briggs 0010 0000 3FFF FFFF System memory 59 1.1 briggs 4000 0000 7FFF FFFF Reserved (programmed to give a memory select 60 1.1 briggs error if accessed--cf 5.7.2) 61 1.1 briggs 8000 0000 FCFF FFFF PCI memory space 62 1.1 briggs FD00 0000 FDFF FFFF PCI/ISA memory space (see 5.8, CPU_FD_ALIAS_EN) 63 1.1 briggs FE00 0000 FE7F FFFF PCI/ISA I/O space (Forwarded to PCI address space 64 1.1 briggs with high byte zeroed, but FE01 0000 and up are 65 1.1 briggs reserved) 66 1.1 briggs FE80 0000 FEBF FFFF PCI I/O space (Forwarded to PCI I/O space with high 67 1.1 briggs byte zeroed) 68 1.1 briggs FEC0 0000 FEDF FFFF PCI configuration address register (Each word in this 69 1.1 briggs range is aliased to the PCI CONFIG_ADDR register) 70 1.1 briggs FEE0 0000 FEEF FFFF PCI configuration data register (Each word in this 71 1.1 briggs range is aliased to the PCI CONFIG_DATA register) 72 1.1 briggs FEF0 0000 FEFF FFFF PCI interrupt acknowledge 73 1.1 briggs FF00 0000 FF7F FFFF 32- or 64-bit Flash/ROM space (Can hit either local 74 1.1 briggs memory or PCI bus -- cf. 5.6) 75 1.1 briggs FF80 0000 FFFF FFFF 8-, 32- or 64-bit Flash/ROM space (Can hit either 76 1.1 briggs local memory or PCI bus -- cf. 5.6) 77 1.1 briggs 78 1.1 briggs This is a host-mode port, so the inbound and output translation windows 79 1.1 briggs are unused. 80 1.1 briggs 81 1.1 briggs The Embedded Utilities Memory Block (EUMB) is set to be 1M below the end 82 1.2 briggs of the PCI memory space: FC00 0000, so EUMBBAR is FC00 0000, giving us 83 1.1 briggs 84 1.2 briggs Message unit (I2O) base : FC00 0000 (cf. 10.2, 10.2.3, 10.3) 85 1.2 briggs DMA base : FC00 1000 (cf. 9.2) 86 1.2 briggs ATU base : FC00 2000 (cf. 4.3.3) 87 1.2 briggs I2C base : FC00 3000 (cf. 11.3) 88 1.2 briggs EPIC base : FC04 0000 (cf. 12.2) 89 1.1 briggs 90 1.1 briggs 91 1.1 briggs 92 1.1 briggs Boot Information 93 1.1 briggs 94 1.1 briggs The SandPoint ships with the Motorola DINK32 ROM. This is a rather 95 1.1 briggs basic ROM with only serial-download (S-Record) capability for 96 1.1 briggs loading the kernel. Basically, the kernel is loaded to a specified 97 1.1 briggs address and you jump to it. The ROM takes care of initializing 98 1.1 briggs the MICRs and MCCRs. There is really no boot information to pass. 99 1.1 briggs 100 1.1 briggs It would be nice to have a much more complete ROM interface, allowing 101 1.1 briggs settings for, say, bootp/tftp boot, automatic boot, and persistent 102 1.1 briggs settings (for console rate, auto boot, bootp, etc), and that might 103 1.1 briggs be provided at some point, but that's not available as of this 104 1.1 briggs writing. 105 1.1 briggs 106 1.2 briggs So, the kernel is hard-coded to boot w/ 32MB for now. 107 1.1 briggs 108 1.1 briggs 109 1.1 briggs 110 1.1 briggs Interrupt Configuration 111 1.1 briggs 112 1.1 briggs The 8240 has the internal EPIC. For the SandPoint, the EPIC is programmed 113 1.1 briggs in mixed-mode (GCR) with direct interrupts (EICR). With this configuration, 114 1.1 briggs there are 13 available interrupts: 115 1.1 briggs 4 global timers 116 1.1 briggs 5 direct IRQs 117 1.1 briggs IRQ0 - PCI Slot #0 INTA# 118 1.1 briggs IRQ1 - PCI Slot #1 INTA# / shared with WinBond I/O 119 1.1 briggs IRQ2 - PCI Slot #2 INTA# 120 1.1 briggs IRQ3 - PCI Slot #3 INTA# 121 1.1 briggs IRQ4 - On-PPMC 16552 interrupt (Unity X2) 122 1.1 briggs IRQ4 - pulled down w/ resistor (Unity X4) 123 1.1 briggs 4 internal interrupts 124 1.1 briggs I2C 125 1.1 briggs DMA Ch0 126 1.1 briggs DMA Ch1 127 1.1 briggs I2O message unit 128 1.1 briggs 129 1.1 briggs The SandPoint can run in one of 4 interrupt modes: 130 1.1 briggs 0 - PMC host with IDE (3.3v PCI slots are unavailable) 131 1.1 briggs 1 - PMC host w/o IDE (all PCI slots are available) 132 1.1 briggs 2 - PMC agent, Winbond providing arbitration & interrupt to INTA# on PMC 133 1.1 briggs 3 - Yellowknife mode--just like #2, except drives INTA# on 4th PCI slot 134 1.1 briggs 135 1.1 briggs We choose to run in mode 1 as Motorola recommends modes 0 or 1 for 136 1.1 briggs all new development. Unfortunately, mode 0 does not appear to 137 1.1 briggs work--"ISA" interrupts are lost. In this mode, with interrupts 138 1.1 briggs routed to PCI slot 3, we have to check for both a Winbond (ISA) 139 1.1 briggs interrupt, and a PCI slot interrupt. So basically, we have a 140 1.1 briggs two-level interrupt configuration for Winbond interrupts. The ISA 141 1.1 briggs bus attachment registers an interrupt for PCI slot 3 with its own 142 1.1 briggs interrupt handler. Drivers for ISA devices on the Winbond will 143 1.1 briggs register interrupts with the ISA interrupt handler. The sticky 144 1.1 briggs part of this is how to deal with one global interrupt priority. 145 1.1 briggs 146 1.1 briggs 147 1.3 garbled 148 1.3 garbled SandPoint III "SP3" Interrupt Configuration 149 1.3 garbled 150 1.3 garbled With a help of additional logic circuit SP3 organizes external 151 1.3 garbled interrupt sources as EPIC serial mode interrupts. 152 1.3 garbled 16 serial IRQs 153 1.3 garbled IRQ0 - WinBond South bridge i8259 PIC, polarity inverted 154 1.3 garbled IRQ1 - reserved 155 1.3 garbled IRQ2 - PCI Slot #1, INTA# 156 1.3 garbled IRQ3 - PCI Slot #2, INTA# 157 1.3 garbled IRQ4 - PCI Slot #3, INTA# 158 1.3 garbled IRQ5 - PCI Slot #4, INTA# 159 1.3 garbled IRQ6 - WinBond INTA# 160 1.3 garbled IRQ7 - WinBond INTB# 161 1.3 garbled IRQ8 - WinBond INTC# 162 1.3 garbled IRQ9 - WinBond INTD# 163 1.3 garbled IRQ10 thru 15 - reserved 164 1.3 garbled SP3 provides switch selections to emulate SP1/2 compatible EPIC 165 1.3 garbled direct mode interrupt assignments. 166
Indexes created Mon Sep 29 21:09:56 GMT 2025