README revision 1.1
1 Overview 2 3 This is a port to the Motorola "SandPoint" evaluation system. The 4 SandPoint is the successor to the "Yellowknife" system. The system 5 can be fitted with different PMCs (Processor Mezzanine Cards). This 6 port is specifically for the rev X2 motherboard system with the PPC 7 8240 PMC rev X4 installed. 8 9 All references (cf) listed here are for the MPC8240 Integrated Processor 10 User's Manual. 11 12 13 14 SandPoint Hardware Configuration 15 16 This port was developed on a Sandpoint X2 motherboard with a Unity X4 PMC. 17 18 This port assumes that the jumpers are set as follows: 19 S3/S4 - Mode 1: PMC w/o IDE (switches opposite, one nearest PCI 20 slot toward near edge) 21 S5 - Interrupt to PMC normal (switch toward near edge) 22 S6 - Local I/O shared with slot 2 (switch toward near edge) 23 24 Mode 0 (PMC w/ IDE) does not appear to work right with ISA interrupts. The 25 interrupts from the Winbond chip do not appear at the PMC. 26 27 On the PPMC, we assume a 100MHz clock. 28 on PPMC: (C == closed, or "on") 29 SW2: 30 C ROM on PCI bus (DINK32 on mainboard) 31 - Map "B": CHRP 32 C Motorola PPMC 33 C Wait for initialization (peripheral mode) 34 - Program mode: Normal mode 35 - Select normal ROM 36 - 33 MHz only 37 - COP only resets local CPU/MPC107 38 SW3: 39 -C--C PCI 33, Mem 66, PPC 266 40 -- 0.5 - 0.9 ns PCI hold time 41 C 25 ohm PCI drive strength 42 43 44 Address Map 45 46 For this port, we choose the "Address Map B" (CHRP-compatible) for the 47 system (see SW2, #2, above): 48 49 (Processor View) 50 0000 0000 0009 FFFF System Memory 51 000A 0000 000F FFFF Compatibility Hole (programmable to go to PCI space 52 or system memory--programmed for system memory--cf 5.8) 53 0010 0000 3FFF FFFF System memory 54 4000 0000 7FFF FFFF Reserved (programmed to give a memory select 55 error if accessed--cf 5.7.2) 56 8000 0000 FCFF FFFF PCI memory space 57 FD00 0000 FDFF FFFF PCI/ISA memory space (see 5.8, CPU_FD_ALIAS_EN) 58 FE00 0000 FE7F FFFF PCI/ISA I/O space (Forwarded to PCI address space 59 with high byte zeroed, but FE01 0000 and up are 60 reserved) 61 FE80 0000 FEBF FFFF PCI I/O space (Forwarded to PCI I/O space with high 62 byte zeroed) 63 FEC0 0000 FEDF FFFF PCI configuration address register (Each word in this 64 range is aliased to the PCI CONFIG_ADDR register) 65 FEE0 0000 FEEF FFFF PCI configuration data register (Each word in this 66 range is aliased to the PCI CONFIG_DATA register) 67 FEF0 0000 FEFF FFFF PCI interrupt acknowledge 68 FF00 0000 FF7F FFFF 32- or 64-bit Flash/ROM space (Can hit either local 69 memory or PCI bus -- cf. 5.6) 70 FF80 0000 FFFF FFFF 8-, 32- or 64-bit Flash/ROM space (Can hit either 71 local memory or PCI bus -- cf. 5.6) 72 73 This is a host-mode port, so the inbound and output translation windows 74 are unused. 75 76 The Embedded Utilities Memory Block (EUMB) is set to be 1M below the end 77 of the PCI memory space: FCF0 0000, so EUMBBAR is FCF0 0000, giving us 78 79 Message unit (I2O) base : FCF0 0000 (cf. 10.2, 10.2.3, 10.3) 80 DMA base : FCF0 1000 (cf. 9.2) 81 ATU base : FCF0 2000 (cf. 4.3.3) 82 I2C base : FCF0 3000 (cf. 11.3) 83 EPIC base : FCF4 0000 (cf. 12.2) 84 85 86 87 Boot Information 88 89 The SandPoint ships with the Motorola DINK32 ROM. This is a rather 90 basic ROM with only serial-download (S-Record) capability for 91 loading the kernel. Basically, the kernel is loaded to a specified 92 address and you jump to it. The ROM takes care of initializing 93 the MICRs and MCCRs. There is really no boot information to pass. 94 95 It would be nice to have a much more complete ROM interface, allowing 96 settings for, say, bootp/tftp boot, automatic boot, and persistent 97 settings (for console rate, auto boot, bootp, etc), and that might 98 be provided at some point, but that's not available as of this 99 writing. 100 101 So, the kernel is hard-coded to boot w/ 64MB for now. 102 103 104 105 Interrupt Configuration 106 107 The 8240 has the internal EPIC. For the SandPoint, the EPIC is programmed 108 in mixed-mode (GCR) with direct interrupts (EICR). With this configuration, 109 there are 13 available interrupts: 110 4 global timers 111 5 direct IRQs 112 IRQ0 - PCI Slot #0 INTA# 113 IRQ1 - PCI Slot #1 INTA# / shared with WinBond I/O 114 IRQ2 - PCI Slot #2 INTA# 115 IRQ3 - PCI Slot #3 INTA# 116 IRQ4 - On-PPMC 16552 interrupt (Unity X2) 117 IRQ4 - pulled down w/ resistor (Unity X4) 118 4 internal interrupts 119 I2C 120 DMA Ch0 121 DMA Ch1 122 I2O message unit 123 124 The SandPoint can run in one of 4 interrupt modes: 125 0 - PMC host with IDE (3.3v PCI slots are unavailable) 126 1 - PMC host w/o IDE (all PCI slots are available) 127 2 - PMC agent, Winbond providing arbitration & interrupt to INTA# on PMC 128 3 - Yellowknife mode--just like #2, except drives INTA# on 4th PCI slot 129 130 We choose to run in mode 1 as Motorola recommends modes 0 or 1 for 131 all new development. Unfortunately, mode 0 does not appear to 132 work--"ISA" interrupts are lost. In this mode, with interrupts 133 routed to PCI slot 3, we have to check for both a Winbond (ISA) 134 interrupt, and a PCI slot interrupt. So basically, we have a 135 two-level interrupt configuration for Winbond interrupts. The ISA 136 bus attachment registers an interrupt for PCI slot 3 with its own 137 interrupt handler. Drivers for ISA devices on the Winbond will 138 register interrupts with the ISA interrupt handler. The sticky 139 part of this is how to deal with one global interrupt priority. 140 141 142
Indexes created Thu Oct 02 10:09:58 GMT 2025