README revision 1.2
1 /* $NetBSD: README,v 1.2 2001/03/06 20:16:09 briggs Exp $ */ 2 3 Overview 4 5 This is a port to the Motorola "SandPoint" evaluation system. The 6 SandPoint is the successor to the "Yellowknife" system. The system 7 can be fitted with different PMCs (Processor Mezzanine Cards). This 8 port is specifically for the rev X2 motherboard system with the PPC 9 8240 PMC rev X4 installed. It also works with the Altimus X2 PMC 10 (MPC7400 with MPC107). 11 12 All references (cf) listed here are for the MPC8240 Integrated Processor 13 User's Manual. 14 15 Information on the Sandpoint can be found on Motorola's web site: 16 http://www.mot.com/SPS/PowerPC/teksupport/refdesigns/sandpoint.html 17 18 19 SandPoint Hardware Configuration 20 21 This port was developed on a Sandpoint X2 motherboard with a Unity X4 PMC. 22 23 This port assumes that the jumpers are set as follows: 24 S3/S4 - Mode 1: PMC w/o IDE (switches opposite, one nearest PCI 25 slot toward near edge) 26 S5 - Interrupt to PMC normal (switch toward near edge) 27 S6 - Local I/O shared with slot 2 (switch toward near edge) 28 29 Mode 0 (PMC w/ IDE) does not appear to work right with ISA interrupts. The 30 interrupts from the Winbond chip do not appear at the PMC. 31 32 On the PPMC, we assume a 100MHz clock. 33 on PPMC: (C == closed, or "on") 34 SW2: 35 C ROM on PCI bus (DINK32 on mainboard) 36 - Map "B": CHRP 37 C Motorola PPMC 38 C Wait for initialization (peripheral mode) 39 - Program mode: Normal mode 40 - Select normal ROM 41 - 33 MHz only 42 - COP only resets local CPU/MPC107 43 SW3: 44 -C--C PCI 33, Mem 66, PPC 266 45 -- 0.5 - 0.9 ns PCI hold time 46 C 25 ohm PCI drive strength 47 48 49 Address Map 50 51 For this port, we choose the "Address Map B" (CHRP-compatible) for the 52 system (see SW2, #2, above): 53 54 (Processor View) 55 0000 0000 0009 FFFF System Memory 56 000A 0000 000F FFFF Compatibility Hole (programmable to go to PCI space 57 or system memory--programmed for system memory--cf 5.8) 58 0010 0000 3FFF FFFF System memory 59 4000 0000 7FFF FFFF Reserved (programmed to give a memory select 60 error if accessed--cf 5.7.2) 61 8000 0000 FCFF FFFF PCI memory space 62 FD00 0000 FDFF FFFF PCI/ISA memory space (see 5.8, CPU_FD_ALIAS_EN) 63 FE00 0000 FE7F FFFF PCI/ISA I/O space (Forwarded to PCI address space 64 with high byte zeroed, but FE01 0000 and up are 65 reserved) 66 FE80 0000 FEBF FFFF PCI I/O space (Forwarded to PCI I/O space with high 67 byte zeroed) 68 FEC0 0000 FEDF FFFF PCI configuration address register (Each word in this 69 range is aliased to the PCI CONFIG_ADDR register) 70 FEE0 0000 FEEF FFFF PCI configuration data register (Each word in this 71 range is aliased to the PCI CONFIG_DATA register) 72 FEF0 0000 FEFF FFFF PCI interrupt acknowledge 73 FF00 0000 FF7F FFFF 32- or 64-bit Flash/ROM space (Can hit either local 74 memory or PCI bus -- cf. 5.6) 75 FF80 0000 FFFF FFFF 8-, 32- or 64-bit Flash/ROM space (Can hit either 76 local memory or PCI bus -- cf. 5.6) 77 78 This is a host-mode port, so the inbound and output translation windows 79 are unused. 80 81 The Embedded Utilities Memory Block (EUMB) is set to be 1M below the end 82 of the PCI memory space: FC00 0000, so EUMBBAR is FC00 0000, giving us 83 84 Message unit (I2O) base : FC00 0000 (cf. 10.2, 10.2.3, 10.3) 85 DMA base : FC00 1000 (cf. 9.2) 86 ATU base : FC00 2000 (cf. 4.3.3) 87 I2C base : FC00 3000 (cf. 11.3) 88 EPIC base : FC04 0000 (cf. 12.2) 89 90 91 92 Boot Information 93 94 The SandPoint ships with the Motorola DINK32 ROM. This is a rather 95 basic ROM with only serial-download (S-Record) capability for 96 loading the kernel. Basically, the kernel is loaded to a specified 97 address and you jump to it. The ROM takes care of initializing 98 the MICRs and MCCRs. There is really no boot information to pass. 99 100 It would be nice to have a much more complete ROM interface, allowing 101 settings for, say, bootp/tftp boot, automatic boot, and persistent 102 settings (for console rate, auto boot, bootp, etc), and that might 103 be provided at some point, but that's not available as of this 104 writing. 105 106 So, the kernel is hard-coded to boot w/ 32MB for now. 107 108 109 110 Interrupt Configuration 111 112 The 8240 has the internal EPIC. For the SandPoint, the EPIC is programmed 113 in mixed-mode (GCR) with direct interrupts (EICR). With this configuration, 114 there are 13 available interrupts: 115 4 global timers 116 5 direct IRQs 117 IRQ0 - PCI Slot #0 INTA# 118 IRQ1 - PCI Slot #1 INTA# / shared with WinBond I/O 119 IRQ2 - PCI Slot #2 INTA# 120 IRQ3 - PCI Slot #3 INTA# 121 IRQ4 - On-PPMC 16552 interrupt (Unity X2) 122 IRQ4 - pulled down w/ resistor (Unity X4) 123 4 internal interrupts 124 I2C 125 DMA Ch0 126 DMA Ch1 127 I2O message unit 128 129 The SandPoint can run in one of 4 interrupt modes: 130 0 - PMC host with IDE (3.3v PCI slots are unavailable) 131 1 - PMC host w/o IDE (all PCI slots are available) 132 2 - PMC agent, Winbond providing arbitration & interrupt to INTA# on PMC 133 3 - Yellowknife mode--just like #2, except drives INTA# on 4th PCI slot 134 135 We choose to run in mode 1 as Motorola recommends modes 0 or 1 for 136 all new development. Unfortunately, mode 0 does not appear to 137 work--"ISA" interrupts are lost. In this mode, with interrupts 138 routed to PCI slot 3, we have to check for both a Winbond (ISA) 139 interrupt, and a PCI slot interrupt. So basically, we have a 140 two-level interrupt configuration for Winbond interrupts. The ISA 141 bus attachment registers an interrupt for PCI slot 3 with its own 142 interrupt handler. Drivers for ISA devices on the Winbond will 143 register interrupts with the ISA interrupt handler. The sticky 144 part of this is how to deal with one global interrupt priority. 145 146 147
Indexes created Thu Oct 02 07:10:07 GMT 2025