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intr.h revision 1.1
      1  1.1  briggs /*	$NetBSD: intr.h,v 1.1 2001/02/04 18:32:13 briggs Exp $	*/
      2  1.1  briggs 
      3  1.1  briggs /*-
      4  1.1  briggs  * Copyright (c) 1998 The NetBSD Foundation, Inc.
      5  1.1  briggs  * All rights reserved.
      6  1.1  briggs  *
      7  1.1  briggs  * This code is derived from software contributed to The NetBSD Foundation
      8  1.1  briggs  * by Charles M. Hannum.
      9  1.1  briggs  *
     10  1.1  briggs  * Redistribution and use in source and binary forms, with or without
     11  1.1  briggs  * modification, are permitted provided that the following conditions
     12  1.1  briggs  * are met:
     13  1.1  briggs  * 1. Redistributions of source code must retain the above copyright
     14  1.1  briggs  *    notice, this list of conditions and the following disclaimer.
     15  1.1  briggs  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.1  briggs  *    notice, this list of conditions and the following disclaimer in the
     17  1.1  briggs  *    documentation and/or other materials provided with the distribution.
     18  1.1  briggs  * 3. All advertising materials mentioning features or use of this software
     19  1.1  briggs  *    must display the following acknowledgement:
     20  1.1  briggs  *        This product includes software developed by the NetBSD
     21  1.1  briggs  *        Foundation, Inc. and its contributors.
     22  1.1  briggs  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  1.1  briggs  *    contributors may be used to endorse or promote products derived
     24  1.1  briggs  *    from this software without specific prior written permission.
     25  1.1  briggs  *
     26  1.1  briggs  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  1.1  briggs  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  1.1  briggs  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  1.1  briggs  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  1.1  briggs  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  1.1  briggs  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  1.1  briggs  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  1.1  briggs  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  1.1  briggs  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  1.1  briggs  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  1.1  briggs  * POSSIBILITY OF SUCH DAMAGE.
     37  1.1  briggs  */
     38  1.1  briggs /*
     39  1.1  briggs  * Sandpoint-specific code developed
     40  1.1  briggs  * by Allen Briggs for Wasabi Systems, Inc.
     41  1.1  briggs  *
     42  1.1  briggs  * OpenPIC code derived from code with the following notice.
     43  1.1  briggs  */
     44  1.1  briggs /*-
     45  1.1  briggs  * Copyright (c) 2000 Tsubai Masanari.  All rights reserved.
     46  1.1  briggs  *
     47  1.1  briggs  * Redistribution and use in source and binary forms, with or without
     48  1.1  briggs  * modification, are permitted provided that the following conditions
     49  1.1  briggs  * are met:
     50  1.1  briggs  * 1. Redistributions of source code must retain the above copyright
     51  1.1  briggs  *    notice, this list of conditions and the following disclaimer.
     52  1.1  briggs  * 2. Redistributions in binary form must reproduce the above copyright
     53  1.1  briggs  *    notice, this list of conditions and the following disclaimer in the
     54  1.1  briggs  *    documentation and/or other materials provided with the distribution.
     55  1.1  briggs  * 3. The name of the author may not be used to endorse or promote products
     56  1.1  briggs  *    derived from this software without specific prior written permission.
     57  1.1  briggs  *
     58  1.1  briggs  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     59  1.1  briggs  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     60  1.1  briggs  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     61  1.1  briggs  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     62  1.1  briggs  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     63  1.1  briggs  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     64  1.1  briggs  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     65  1.1  briggs  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     66  1.1  briggs  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     67  1.1  briggs  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     68  1.1  briggs  */
     69  1.1  briggs 
     70  1.1  briggs #ifndef _SANDPOINT_INTR_H_
     71  1.1  briggs #define _SANDPOINT_INTR_H_
     72  1.1  briggs 
     73  1.1  briggs /* Interrupt priority `levels'. */
     74  1.1  briggs #define	IPL_NONE	9	/* nothing */
     75  1.1  briggs #define	IPL_SOFTCLOCK	8	/* software clock interrupt */
     76  1.1  briggs #define	IPL_SOFTNET	7	/* software network interrupt */
     77  1.1  briggs #define	IPL_BIO		6	/* block I/O */
     78  1.1  briggs #define	IPL_NET		5	/* network */
     79  1.1  briggs #define	IPL_SOFTSERIAL	4	/* software serial interrupt */
     80  1.1  briggs #define	IPL_TTY		3	/* terminal */
     81  1.1  briggs #define	IPL_IMP		3	/* memory allocation */
     82  1.1  briggs #define	IPL_AUDIO	2	/* audio */
     83  1.1  briggs #define	IPL_CLOCK	1	/* clock */
     84  1.1  briggs #define	IPL_HIGH	1	/* everything */
     85  1.1  briggs #define	IPL_SERIAL	0	/* serial */
     86  1.1  briggs #define	NIPL		10
     87  1.1  briggs 
     88  1.1  briggs /* Interrupt sharing types. */
     89  1.1  briggs #define	IST_NONE	0	/* none */
     90  1.1  briggs #define	IST_PULSE	1	/* pulsed */
     91  1.1  briggs #define	IST_EDGE	2	/* edge-triggered */
     92  1.1  briggs #define	IST_LEVEL	3	/* level-triggered */
     93  1.1  briggs 
     94  1.1  briggs #ifndef _LOCORE
     95  1.1  briggs 
     96  1.1  briggs /*
     97  1.1  briggs  * Interrupt handler chains.  intr_establish() inserts a handler into
     98  1.1  briggs  * the list.  The handler is called with its (single) argument.
     99  1.1  briggs  */
    100  1.1  briggs struct intrhand {
    101  1.1  briggs 	int	(*ih_fun)(void *);
    102  1.1  briggs 	void	*ih_arg;
    103  1.1  briggs 	u_long	ih_count;
    104  1.1  briggs 	struct	intrhand *ih_next;
    105  1.1  briggs 	int	ih_level;
    106  1.1  briggs 	int	ih_irq;
    107  1.1  briggs };
    108  1.1  briggs 
    109  1.1  briggs void	setsoftclock(void);
    110  1.1  briggs void	clearsoftclock(void);
    111  1.1  briggs int	splsoftclock(void);
    112  1.1  briggs void	setsoftnet(void);
    113  1.1  briggs void	clearsoftnet(void);
    114  1.1  briggs int	splsoftnet(void);
    115  1.1  briggs 
    116  1.1  briggs void	do_pending_int(void);
    117  1.1  briggs void	*intr_establish(int, int, int, int (*)(void *), void *);
    118  1.1  briggs void	intr_disestablish(void *);
    119  1.1  briggs 
    120  1.1  briggs static __inline int splraise(int);
    121  1.1  briggs static __inline int spllower(int);
    122  1.1  briggs static __inline void splx(int);
    123  1.1  briggs static __inline void set_sint(int);
    124  1.1  briggs 
    125  1.1  briggs void softnet __P((int));	/* Defined in machdep.c, used in extintr.c */
    126  1.1  briggs 
    127  1.1  briggs extern volatile int cpl, ipending, astpending, tickspending;
    128  1.1  briggs extern int imask[];
    129  1.1  briggs extern long intrcnt[];
    130  1.1  briggs 
    131  1.1  briggs /*
    132  1.1  briggs  * Reorder protection in the following inline functions is
    133  1.1  briggs  * protected with the "eieio" instruction.
    134  1.1  briggs  */
    135  1.1  briggs static __inline int
    136  1.1  briggs splraise(newcpl)
    137  1.1  briggs 	int newcpl;
    138  1.1  briggs {
    139  1.1  briggs 	int oldcpl;
    140  1.1  briggs 
    141  1.1  briggs 	__asm__ volatile("sync; eieio\n");	/* don't reorder.... */
    142  1.1  briggs 	oldcpl = cpl;
    143  1.1  briggs 	cpl = oldcpl | newcpl;
    144  1.1  briggs 	__asm__ volatile("sync; eieio\n");	/* reorder protect */
    145  1.1  briggs 	return(oldcpl);
    146  1.1  briggs }
    147  1.1  briggs 
    148  1.1  briggs static __inline void
    149  1.1  briggs splx(newcpl)
    150  1.1  briggs 	int newcpl;
    151  1.1  briggs {
    152  1.1  briggs 	__asm__ volatile("sync; eieio\n");	/* reorder protect */
    153  1.1  briggs 	cpl = newcpl;
    154  1.1  briggs 	if(ipending & ~newcpl)
    155  1.1  briggs 		do_pending_int();
    156  1.1  briggs 	__asm__ volatile("sync; eieio\n");	/* reorder protect */
    157  1.1  briggs }
    158  1.1  briggs 
    159  1.1  briggs static __inline int
    160  1.1  briggs spllower(newcpl)
    161  1.1  briggs 	int newcpl;
    162  1.1  briggs {
    163  1.1  briggs 	int oldcpl;
    164  1.1  briggs 
    165  1.1  briggs 	__asm__ volatile("sync; eieio\n");	/* reorder protect */
    166  1.1  briggs 	oldcpl = cpl;
    167  1.1  briggs 	cpl = newcpl;
    168  1.1  briggs 	if(ipending & ~newcpl)
    169  1.1  briggs 		do_pending_int();
    170  1.1  briggs 	__asm__ volatile("sync; eieio\n");	/* reorder protect */
    171  1.1  briggs 	return(oldcpl);
    172  1.1  briggs }
    173  1.1  briggs 
    174  1.1  briggs /* Following code should be implemented with lwarx/stwcx to avoid
    175  1.1  briggs  * the disable/enable. i need to read the manual once more.... */
    176  1.1  briggs static __inline void
    177  1.1  briggs set_sint(pending)
    178  1.1  briggs 	int	pending;
    179  1.1  briggs {
    180  1.1  briggs 	int	msrsave;
    181  1.1  briggs 
    182  1.1  briggs 	__asm__ ("mfmsr %0" : "=r"(msrsave));
    183  1.1  briggs 	__asm__ volatile ("mtmsr %0" :: "r"(msrsave & ~PSL_EE));
    184  1.1  briggs 	ipending |= pending;
    185  1.1  briggs 	__asm__ volatile ("mtmsr %0" :: "r"(msrsave));
    186  1.1  briggs }
    187  1.1  briggs 
    188  1.1  briggs /*
    189  1.1  briggs  * Motorola SandPoint PPC eval board interrupt list
    190  1.1  briggs  */
    191  1.1  briggs #define	SANDPOINT_INTR_PCI0		0
    192  1.1  briggs #define	SANDPOINT_INTR_IDE0		SANDPOINT_INTR_PCI0
    193  1.1  briggs #define	SANDPOINT_INTR_PCI1		1
    194  1.1  briggs #define	SANDPOINT_INTR_IDE1		SANDPOINT_INTR_PCI1
    195  1.1  briggs #define	SANDPOINT_INTR_ISA		SANDPOINT_INTR_PCI1
    196  1.1  briggs #define	SANDPOINT_INTR_PCI2		2
    197  1.1  briggs #define	SANDPOINT_INTR_PCI3		3
    198  1.1  briggs #define	SANDPOINT_INTR_SERCON		4	/* Not used on Unity X4 */
    199  1.1  briggs #define	SANDPOINT_INTR_I2C		5
    200  1.1  briggs #define	SANDPOINT_INTR_DMA0		6
    201  1.1  briggs #define	SANDPOINT_INTR_DMA1		7
    202  1.1  briggs #define	SANDPOINT_INTR_I2O		8
    203  1.1  briggs #define	SANDPOINT_INTR_TIMER0		9
    204  1.1  briggs #define	SANDPOINT_INTR_TIMER1		10
    205  1.1  briggs #define	SANDPOINT_INTR_TIMER2		11
    206  1.1  briggs #define	SANDPOINT_INTR_TIMER3		12
    207  1.1  briggs 
    208  1.1  briggs #define	OPENPIC_MAX_EXTERNAL_INT	4
    209  1.1  briggs 
    210  1.1  briggs #define	ICU_LEN		13
    211  1.1  briggs #define	ICU_MASK	0x00001fff
    212  1.1  briggs #define	LEGAL_IRQ(x)	((x) >= 0 && (x) < ICU_LEN)
    213  1.1  briggs 
    214  1.1  briggs #define	SINT_ISA	0x10000000
    215  1.1  briggs #define	SINT_NET	0x20000000
    216  1.1  briggs #define	SINT_CLOCK	0x40000000
    217  1.1  briggs #define	SINT_SERIAL	0x80000000
    218  1.1  briggs #define	SPL_CLOCK	0x00000001
    219  1.1  briggs #define	SINT_MASK	(SINT_ISA|SINT_CLOCK|SINT_NET|SINT_SERIAL)
    220  1.1  briggs 
    221  1.1  briggs #define	CNT_SINT_ISA	28
    222  1.1  briggs #define	CNT_SINT_NET	29
    223  1.1  briggs #define	CNT_SINT_CLOCK	30
    224  1.1  briggs #define	CNT_SINT_SERIAL	31
    225  1.1  briggs #define	CNT_CLOCK	0
    226  1.1  briggs 
    227  1.1  briggs #define splbio()	splraise(imask[IPL_BIO])
    228  1.1  briggs #define splnet()	splraise(imask[IPL_NET])
    229  1.1  briggs #define spltty()	splraise(imask[IPL_TTY])
    230  1.1  briggs #define splclock()	splraise(imask[IPL_CLOCK])
    231  1.1  briggs #define splimp()	splraise(imask[IPL_IMP])
    232  1.1  briggs #define splvm()		splraise(imask[IPL_IMP])
    233  1.1  briggs #define	splserial()	splraise(imask[IPL_SERIAL])
    234  1.1  briggs #define splstatclock()	splclock()
    235  1.1  briggs #define	spllowersoftclock() spllower(imask[IPL_SOFTCLOCK])
    236  1.1  briggs #define	splsoftclock()	splraise(imask[IPL_SOFTCLOCK])
    237  1.1  briggs #define	splsoftnet()	splraise(imask[IPL_SOFTNET])
    238  1.1  briggs #define	splsoftserial()	splraise(imask[IPL_SOFTSERIAL])
    239  1.1  briggs 
    240  1.1  briggs #define spllpt()	spltty()
    241  1.1  briggs 
    242  1.1  briggs #define	setsoftisa()	set_sint(SINT_ISA);
    243  1.1  briggs #define	setsoftclock()	set_sint(SINT_CLOCK);
    244  1.1  briggs #define	setsoftnet()	set_sint(SINT_NET);
    245  1.1  briggs #define	setsoftserial()	set_sint(SINT_SERIAL);
    246  1.1  briggs 
    247  1.1  briggs #define	splhigh()	splraise(imask[IPL_HIGH])
    248  1.1  briggs #define	spl0()		spllower(0)
    249  1.1  briggs 
    250  1.1  briggs #define splsched()	splhigh()
    251  1.1  briggs #define spllock()	splhigh()
    252  1.1  briggs 
    253  1.1  briggs #endif /* !_LOCORE */
    254  1.1  briggs 
    255  1.1  briggs #endif /* !_SANDPOINT_INTR_H_ */
    256