pci_machdep.c revision 1.12.38.1
1 /* $NetBSD: pci_machdep.c,v 1.12.38.1 2007/05/04 11:03:24 nisimura Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Machine-specific functions for PCI autoconfiguration. 35 * 36 * On PCs, there are two methods of generating PCI configuration cycles. 37 * We try to detect the appropriate mechanism for this machine and set 38 * up a few function pointers to access the correct method directly. 39 * 40 * The configuration method can be hard-coded in the config file by 41 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 42 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.12.38.1 2007/05/04 11:03:24 nisimura Exp $"); 47 48 #include "opt_openpic.h" 49 50 #include <sys/types.h> 51 #include <sys/param.h> 52 #include <sys/device.h> 53 #include <sys/errno.h> 54 #include <sys/extent.h> 55 #include <sys/malloc.h> 56 #include <sys/queue.h> 57 #include <sys/systm.h> 58 #include <sys/time.h> 59 60 #include <uvm/uvm.h> 61 62 #define _POWERPC_BUS_DMA_PRIVATE 63 #include <machine/bus.h> 64 #include <machine/pio.h> 65 #include <machine/intr.h> 66 #include <machine/openpicreg.h> 67 68 #include <dev/isa/isavar.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pciconf.h> 72 73 struct powerpc_bus_dma_tag pci_bus_dma_tag = { 74 0, /* _bounce_thresh */ 75 _bus_dmamap_create, 76 _bus_dmamap_destroy, 77 _bus_dmamap_load, 78 _bus_dmamap_load_mbuf, 79 _bus_dmamap_load_uio, 80 _bus_dmamap_load_raw, 81 _bus_dmamap_unload, 82 NULL, /* _dmamap_sync */ 83 _bus_dmamem_alloc, 84 _bus_dmamem_free, 85 _bus_dmamem_map, 86 _bus_dmamem_unmap, 87 _bus_dmamem_mmap, 88 }; 89 90 #define PCI_CONFIG_ENABLE 0x80000000UL 91 92 void 93 pci_attach_hook(parent, self, pba) 94 struct device *parent, *self; 95 struct pcibus_attach_args *pba; 96 { 97 } 98 99 int 100 pci_bus_maxdevs(pc, busno) 101 pci_chipset_tag_t pc; 102 int busno; 103 { 104 105 /* 106 * Bus number is irrelevant. Configuration Mechanism 1 is in 107 * use, can have devices 0-32 (i.e. the `normal' range). 108 */ 109 return (32); 110 } 111 112 pcitag_t 113 pci_make_tag(pc, bus, device, function) 114 pci_chipset_tag_t pc; 115 int bus, device, function; 116 { 117 pcitag_t tag; 118 119 if (bus >= 256 || device >= 32 || function >= 8) 120 panic("pci_make_tag: bad request"); 121 122 tag = PCI_CONFIG_ENABLE | 123 (bus << 16) | (device << 11) | (function << 8); 124 return tag; 125 } 126 127 void 128 pci_decompose_tag(pc, tag, bp, dp, fp) 129 pci_chipset_tag_t pc; 130 pcitag_t tag; 131 int *bp, *dp, *fp; 132 { 133 134 if (bp != NULL) 135 *bp = (tag >> 16) & 0xff; 136 if (dp != NULL) 137 *dp = (tag >> 11) & 0x1f; 138 if (fp != NULL) 139 *fp = (tag >> 8) & 0x7; 140 return; 141 } 142 143 /* 144 * The Kahlua documentation says that "reg" should be left-shifted by two 145 * and be in bits 2-7. Apparently not. It doesn't work that way, and the 146 * DINK32 ROM doesn't do it that way (I peeked at 0xfec00000 after running 147 * the DINK32 "pcf" command). 148 */ 149 #define SP_PCI(tag, reg) ((tag) | (reg)) 150 151 pcireg_t 152 pci_conf_read(pc, tag, reg) 153 pci_chipset_tag_t pc; 154 pcitag_t tag; 155 int reg; 156 { 157 pcireg_t data; 158 159 out32rb(SANDPOINT_PCI_CONFIG_ADDR, SP_PCI(tag,reg)); 160 data = in32rb(SANDPOINT_PCI_CONFIG_DATA); 161 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 162 return data; 163 } 164 165 void 166 pci_conf_write(pc, tag, reg, data) 167 pci_chipset_tag_t pc; 168 pcitag_t tag; 169 int reg; 170 pcireg_t data; 171 { 172 out32rb(SANDPOINT_PCI_CONFIG_ADDR, SP_PCI(tag, reg)); 173 out32rb(SANDPOINT_PCI_CONFIG_DATA, data); 174 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 175 } 176 177 int 178 pci_intr_map(pa, ihp) 179 struct pci_attach_args *pa; 180 pci_intr_handle_t *ihp; 181 { 182 int pin = pa->pa_intrpin; 183 int line = pa->pa_intrline; 184 185 if (pin == 0) { 186 /* No IRQ used. */ 187 goto bad; 188 } 189 190 if (pin > 4) { 191 printf("pci_intr_map: bad interrupt pin %d\n", pin); 192 goto bad; 193 } 194 195 /* 196 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 197 * `unknown' or `no connection' on a PC. We assume that a device with 198 * `no connection' either doesn't have an interrupt (in which case the 199 * pin number should be 0, and would have been noticed above), or 200 * wasn't configured by the BIOS (in which case we punt, since there's 201 * no real way we can know how the interrupt lines are mapped in the 202 * hardware). 203 * 204 * XXX 205 * Since IRQ 0 is only used by the clock, and we can't actually be sure 206 * that the BIOS did its job, we also recognize that as meaning that 207 * the BIOS has not configured the device. 208 */ 209 if (line == 255) { 210 printf("pci_intr_map: no mapping for pin %c\n", '@' + pin); 211 goto bad; 212 } 213 #if defined(OPENPIC_SERIAL_MODE) 214 if (line == 11) { 215 switch (pin) { 216 case PCI_INTERRUPT_PIN_A: 217 *ihp = SANDPOINT_INTR_WINBOND_A; 218 break; 219 case PCI_INTERRUPT_PIN_B: 220 *ihp = SANDPOINT_INTR_WINBOND_B; 221 break; 222 case PCI_INTERRUPT_PIN_C: 223 *ihp = SANDPOINT_INTR_WINBOND_C; 224 break; 225 case PCI_INTERRUPT_PIN_D: 226 *ihp = SANDPOINT_INTR_WINBOND_D; 227 break; 228 default: 229 printf("pci_intr_map: bad interrupt line %d,%c\n", 230 line, pin + '@'); 231 goto bad; 232 break; 233 } 234 *ihp = SANDPOINT_INTR_WINBOND_C; 235 } else { 236 #else 237 if (1) { 238 #endif 239 /* 240 * Sandpoint has 4 PCI slots. 241 * Sandpoint rev. X2 has them in a weird order. Counting 242 * from center out toward the edge, we have: 243 * Slot 1 (dev 14?) (labelled 1) 244 * Slot 0 (dev 13?) (labelled 2) 245 * Slot 3 (dev 16) (labelled 3) 246 * Slot 2 (dev 15) (labelled 4) 247 * To keep things confusing, we will consistently use a zero- 248 * based numbering scheme where Motorola's is usually 1-based. 249 */ 250 if (line < 13 || line > 16) { 251 printf("pci_intr_map: bad interrupt line %d,%c\n", 252 line, pin + '@'); 253 goto bad; 254 } 255 256 /* 257 * In the PCI configuration code, we simply assign the dev 258 * number to the interrupt line. We extract it here for the 259 * interrupt, but subtract off the lowest dev (13) to get 260 * the IRQ. 261 */ 262 #if defined(OPENPIC_SERIAL_MODE) 263 *ihp = line - 11; 264 #else 265 *ihp = line - 13; 266 #endif 267 } 268 return 0; 269 270 bad: 271 *ihp = -1; 272 return 1; 273 } 274 275 const char * 276 pci_intr_string(pc, ih) 277 pci_chipset_tag_t pc; 278 pci_intr_handle_t ih; 279 { 280 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 281 282 if (ih < 0 || ih >= ICU_LEN) 283 panic("pci_intr_string: bogus handle 0x%x", ih); 284 285 sprintf(irqstr, "irq %d", ih); 286 return (irqstr); 287 288 } 289 290 const struct evcnt * 291 pci_intr_evcnt(pc, ih) 292 pci_chipset_tag_t pc; 293 pci_intr_handle_t ih; 294 { 295 296 /* XXX for now, no evcnt parent reported */ 297 return NULL; 298 } 299 300 void * 301 pci_intr_establish(pc, ih, level, func, arg) 302 pci_chipset_tag_t pc; 303 pci_intr_handle_t ih; 304 int level, (*func) __P((void *)); 305 void *arg; 306 { 307 #if 0 308 if (ih < SANDPOINT_INTR_PCI0 || ih > SANDPOINT_INTR_PCI3) 309 panic("pci_intr_establish: bogus handle 0x%x", ih); 310 #endif 311 312 /* 313 * ih is the value assigned in pci_intr_map(), above. 314 * For the Sandpoint, this is the zero-based slot #, 315 * configured when the bus is set up. 316 */ 317 return intr_establish(ih, IST_LEVEL, level, func, arg); 318 } 319 320 void 321 pci_intr_disestablish(pc, cookie) 322 pci_chipset_tag_t pc; 323 void *cookie; 324 { 325 intr_disestablish(cookie); 326 } 327 328 void 329 pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin, int swiz, 330 int *iline) 331 { 332 if (bus == 0) { 333 *iline = dev; 334 } else { 335 /* 336 * If we are not on bus zero, we're behind a bridge, so we 337 * swizzle. 338 * 339 * The documentation lies about this. In slot 3 (numbering 340 * from 0) aka device 16, INTD# becomes an interrupt for 341 * slot 2. INTC# becomes an interrupt for slot 1, etc. 342 * In slot 2 aka device 16, INTD# becomes an interrupt for 343 * slot 1, etc. 344 * 345 * Verified for INTD# on device 16, INTC# on device 16, 346 * INTD# on device 15, INTD# on device 13, and INTC# on 347 * device 14. I presume that the rest follow the same 348 * pattern. 349 * 350 * Slot 0 is device 13, and is the base for the rest. 351 */ 352 *iline = 13 + ((swiz + dev + 3) & 3); 353 } 354 } 355
Indexes created Fri Oct 31 04:09:52 GMT 2025