pci_machdep.c revision 1.12.38.3
1 /* $NetBSD: pci_machdep.c,v 1.12.38.3 2007/05/23 01:45:10 nisimura Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Machine-specific functions for PCI autoconfiguration. 35 * 36 * On PCs, there are two methods of generating PCI configuration cycles. 37 * We try to detect the appropriate mechanism for this machine and set 38 * up a few function pointers to access the correct method directly. 39 * 40 * The configuration method can be hard-coded in the config file by 41 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 42 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.12.38.3 2007/05/23 01:45:10 nisimura Exp $"); 47 48 #include <sys/types.h> 49 #include <sys/param.h> 50 #include <sys/device.h> 51 #include <sys/errno.h> 52 #include <sys/extent.h> 53 #include <sys/malloc.h> 54 #include <sys/queue.h> 55 #include <sys/systm.h> 56 #include <sys/time.h> 57 58 #include <uvm/uvm.h> 59 60 #define _POWERPC_BUS_DMA_PRIVATE 61 #include <machine/bus.h> 62 #include <machine/pio.h> 63 #include <machine/intr.h> 64 65 #include <dev/isa/isavar.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pciconf.h> 69 #include <dev/pci/pcidevs.h> 70 71 struct powerpc_bus_dma_tag pci_bus_dma_tag = { 72 0, /* _bounce_thresh */ 73 _bus_dmamap_create, 74 _bus_dmamap_destroy, 75 _bus_dmamap_load, 76 _bus_dmamap_load_mbuf, 77 _bus_dmamap_load_uio, 78 _bus_dmamap_load_raw, 79 _bus_dmamap_unload, 80 NULL, /* _dmamap_sync */ 81 _bus_dmamem_alloc, 82 _bus_dmamem_free, 83 _bus_dmamem_map, 84 _bus_dmamem_unmap, 85 _bus_dmamem_mmap, 86 }; 87 88 static int brdtype; 89 #define BRD_SANDPOINTX2 2 90 #define BRD_SANDPOINTX3 3 91 #define BRD_ENCOREPP1 10 92 #define BRD_KUROBOX 100 93 #define BRD_QNAPTS101 101 94 #define BRD_SYNOLOGY 102 95 #define BRD_UNKNOWN -1 96 97 #define PCI_CONFIG_ENABLE 0x80000000UL 98 99 void 100 pci_attach_hook(parent, self, pba) 101 struct device *parent, *self; 102 struct pcibus_attach_args *pba; 103 { 104 pcitag_t tag; 105 pcireg_t dev11, dev22, dev15; 106 107 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 108 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 109 if (PCI_CLASS(dev11) == PCI_CLASS_BRIDGE) { 110 /* WinBond/Symphony Lab 83C553 at dev 11 */ 111 /* 112 * XXX distinguish SP3 from SP2 by fiddling ISA GPIO #7/6. 113 * XXX SP3 #7 output values loopback to #6 input. 114 */ 115 brdtype = BRD_SANDPOINTX3; 116 return; 117 } 118 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 22, 0); 119 dev22 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 120 if (PCI_CLASS(dev22) == PCI_CLASS_BRIDGE) { 121 /* VIA 82C686B at dev 22 */ 122 brdtype = BRD_ENCOREPP1; 123 return; 124 } 125 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 126 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 127 if (PCI_CLASS(dev11) == PCI_CLASS_NETWORK) { 128 /* tlp (ADMtek AN985) or re (RealTek 8169S) at dev 11 */ 129 brdtype = BRD_KUROBOX; 130 return; 131 } 132 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 15, 0); 133 dev15 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 134 if (PCI_VENDOR(dev15) == PCI_VENDOR_MARVELL) { 135 /* Marvell GbE at dev 15 */ 136 brdtype = BRD_SYNOLOGY; 137 return; 138 } 139 if (PCI_VENDOR(dev15) == PCI_VENDOR_INTEL) { 140 /* Intel GbE at dev 15 */ 141 brdtype = BRD_QNAPTS101; 142 return; 143 } 144 brdtype = BRD_UNKNOWN; 145 } 146 147 int 148 pci_bus_maxdevs(pc, busno) 149 pci_chipset_tag_t pc; 150 int busno; 151 { 152 153 /* 154 * Bus number is irrelevant. Configuration Mechanism 1 is in 155 * use, can have devices 0-32 (i.e. the `normal' range). 156 */ 157 return (32); 158 } 159 160 pcitag_t 161 pci_make_tag(pc, bus, device, function) 162 pci_chipset_tag_t pc; 163 int bus, device, function; 164 { 165 pcitag_t tag; 166 167 if (bus >= 256 || device >= 32 || function >= 8) 168 panic("pci_make_tag: bad request"); 169 170 tag = PCI_CONFIG_ENABLE | 171 (bus << 16) | (device << 11) | (function << 8); 172 return tag; 173 } 174 175 void 176 pci_decompose_tag(pc, tag, bp, dp, fp) 177 pci_chipset_tag_t pc; 178 pcitag_t tag; 179 int *bp, *dp, *fp; 180 { 181 182 if (bp != NULL) 183 *bp = (tag >> 16) & 0xff; 184 if (dp != NULL) 185 *dp = (tag >> 11) & 0x1f; 186 if (fp != NULL) 187 *fp = (tag >> 8) & 0x7; 188 return; 189 } 190 191 /* 192 * The Kahlua documentation says that "reg" should be left-shifted by two 193 * and be in bits 2-7. Apparently not. It doesn't work that way, and the 194 * DINK32 ROM doesn't do it that way (I peeked at 0xfec00000 after running 195 * the DINK32 "pcf" command). 196 */ 197 #define SP_PCI(tag, reg) ((tag) | (reg)) 198 199 pcireg_t 200 pci_conf_read(pc, tag, reg) 201 pci_chipset_tag_t pc; 202 pcitag_t tag; 203 int reg; 204 { 205 pcireg_t data; 206 207 out32rb(SANDPOINT_PCI_CONFIG_ADDR, SP_PCI(tag,reg)); 208 data = in32rb(SANDPOINT_PCI_CONFIG_DATA); 209 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 210 return data; 211 } 212 213 void 214 pci_conf_write(pc, tag, reg, data) 215 pci_chipset_tag_t pc; 216 pcitag_t tag; 217 int reg; 218 pcireg_t data; 219 { 220 out32rb(SANDPOINT_PCI_CONFIG_ADDR, SP_PCI(tag, reg)); 221 out32rb(SANDPOINT_PCI_CONFIG_DATA, data); 222 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 223 } 224 225 int 226 pci_intr_map(pa, ihp) 227 struct pci_attach_args *pa; 228 pci_intr_handle_t *ihp; 229 { 230 int pin = pa->pa_intrpin; 231 int line = pa->pa_intrline; 232 233 if (pin == 0) { 234 /* No IRQ used. */ 235 goto bad; 236 } 237 238 if (pin > 4) { 239 printf("pci_intr_map: bad interrupt pin %d\n", pin); 240 goto bad; 241 } 242 243 /* 244 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 245 * `unknown' or `no connection' on a PC. We assume that a device with 246 * `no connection' either doesn't have an interrupt (in which case the 247 * pin number should be 0, and would have been noticed above), or 248 * wasn't configured by the BIOS (in which case we punt, since there's 249 * no real way we can know how the interrupt lines are mapped in the 250 * hardware). 251 * 252 * XXX 253 * Since IRQ 0 is only used by the clock, and we can't actually be sure 254 * that the BIOS did its job, we also recognize that as meaning that 255 * the BIOS has not configured the device. 256 */ 257 if (line == 255) { 258 printf("pci_intr_map: no mapping for pin %c\n", '@' + pin); 259 goto bad; 260 } 261 262 printf("line %d, pin %c", line, pin + '@'); 263 switch (brdtype) { 264 /* Sandpoint has 4 PCI slots in a weird order. 265 * From next to MPMC mezzanine card toward the board edge, 266 * 64bit slot PCI AD14 267 * 64bit slot PCI AD13 268 * 32bit slot PCI AD16 269 * 32bit slot PCI AD15 270 * Don't believe identifying labels printed on PCB and 271 * documents confusing as well since Moto names the slots 272 * as number 1 origin. 273 * 274 * Sandpoint X3 "SP3" brd uses EPIC serial mode IRQ. WinBond 275 * SB i8259 PIC interrupt is wired to EPIC IRQ0 while AD13-16 276 * come through IRQ2-5. 277 * 278 * Sandpoint X2 brd uses EPIC direct mode IRQ. Interrupts 279 * from AD13-AD16 are wired with EPIC IRQ0-3. WinBond SB 280 * i8259 shares EPIC IRQ1 line with the PCI slot next to 281 * MPMC mezzanine card. WinBond IDE shares EPIC IRQ2 line. 282 */ 283 case BRD_SANDPOINTX3: 284 if (line == 11 285 && pa->pa_function == 1 && pa->pa_bus == 0) { 286 /* map pin A-D to EPIC IRQ6-9 */ 287 *ihp = 6 + (pin - 1); 288 break; 289 } 290 if (line < 13 || line > 16) { 291 printf("pci_intr_map: bad interrupt line %d,%c\n", 292 line, pin + '@'); 293 goto bad; 294 } 295 /* map line 13-16 to EPIC IRQ2-5 */ 296 *ihp = line - 11; 297 break; 298 case BRD_SANDPOINTX2: 299 if (line == 11 300 && pa->pa_function == 1 && pa->pa_bus == 0) { 301 /* 83C553 PCI IDE comes thru EPIC IRQ2 */ 302 *ihp = 2; 303 break; 304 } 305 if (line < 13 || line > 16) { 306 printf("pci_intr_map: bad interrupt line %d,%c\n", 307 line, pin + '@'); 308 goto bad; 309 } 310 /* map line 13-16 to EPIC IRQ0-3 */ 311 line -= 13; pin -= 1; 312 *ihp = (line + (4 - pin)) & 3; 313 break; 314 case BRD_ENCOREPP1: 315 /* 316 * Ampro EnCorePP1 brd uses EPIC direct mode IRQ. Via 686B SB 317 * i8259 interrupt goes through EPC IRQ0. PCI pin A-D are 318 * tied with EPIC IRQ1-4. 319 * AD22 pin A,B,C,D -> EPIC IRQ 1,2,3,4. 320 * AD23 pin A,B,C,D -> EPIC IRQ 2,3,4,1. 321 * AD24 pin A,B,C,D -> EPIC IRQ 3,4,1,2. 322 * AD25 pin A,B,C,D -> EPIC IRQ 4,1,2,3. 323 */ 324 line -= 22; pin -= 1; 325 *ihp = 1 + ((pin + line) & 3); 326 break; 327 case BRD_KUROBOX: 328 /* map line 11,12,13,14 to EPIC IRQ0,1,4,3 */ 329 *ihp = (line == 13) ? 4 : line - 11; 330 break; 331 case BRD_QNAPTS101: 332 /* map line 12-15 to EPIC IRQ0-3 */ 333 *ihp = line - 12; 334 break; 335 case BRD_SYNOLOGY: 336 /* map line 13-16 to EPIC IRQ0-3 */ 337 *ihp = line - 13; 338 break; 339 default: 340 /* map line 12-15 to EPIC IRQ0-3 */ 341 *ihp = line - 12; 342 break; 343 } 344 printf(" = EPIC %d\n", *ihp); 345 return 0; 346 bad: 347 *ihp = -1; 348 return 1; 349 } 350 351 const char * 352 pci_intr_string(pc, ih) 353 pci_chipset_tag_t pc; 354 pci_intr_handle_t ih; 355 { 356 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 357 358 if (ih < 0 || ih >= ICU_LEN) 359 panic("pci_intr_string: bogus handle 0x%x", ih); 360 361 sprintf(irqstr, "irq %d", ih + 16); 362 return (irqstr); 363 364 } 365 366 const struct evcnt * 367 pci_intr_evcnt(pc, ih) 368 pci_chipset_tag_t pc; 369 pci_intr_handle_t ih; 370 { 371 372 /* XXX for now, no evcnt parent reported */ 373 return NULL; 374 } 375 376 void * 377 pci_intr_establish(pc, ih, level, func, arg) 378 pci_chipset_tag_t pc; 379 pci_intr_handle_t ih; 380 int level, (*func) __P((void *)); 381 void *arg; 382 { 383 /* 384 * ih is the value assigned in pci_intr_map(), above. 385 * It's the EPIC IRQ #. 386 */ 387 return intr_establish(ih + 16, IST_LEVEL, level, func, arg); 388 } 389 390 void 391 pci_intr_disestablish(pc, cookie) 392 pci_chipset_tag_t pc; 393 void *cookie; 394 { 395 intr_disestablish(cookie); 396 } 397 398 void 399 pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin, int swiz, 400 int *iline) 401 { 402 if (bus == 0) { 403 *iline = dev; 404 } else { 405 /* 406 * If we are not on bus zero, we're behind a bridge, so we 407 * swizzle. 408 * 409 * The documentation lies about this. In slot 3 (numbering 410 * from 0) aka device 16, INTD# becomes an interrupt for 411 * slot 2. INTC# becomes an interrupt for slot 1, etc. 412 * In slot 2 aka device 16, INTD# becomes an interrupt for 413 * slot 1, etc. 414 * 415 * Verified for INTD# on device 16, INTC# on device 16, 416 * INTD# on device 15, INTD# on device 13, and INTC# on 417 * device 14. I presume that the rest follow the same 418 * pattern. 419 * 420 * Slot 0 is device 13, and is the base for the rest. 421 */ 422 *iline = 13 + ((swiz + dev + 3) & 3); 423 } 424 } 425
Indexes created Thu Oct 23 22:10:10 GMT 2025