pci_machdep.c revision 1.12.38.4
1 /* $NetBSD: pci_machdep.c,v 1.12.38.4 2007/06/08 09:55:51 nisimura Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Machine-specific functions for PCI autoconfiguration. 35 * 36 * On PCs, there are two methods of generating PCI configuration cycles. 37 * We try to detect the appropriate mechanism for this machine and set 38 * up a few function pointers to access the correct method directly. 39 * 40 * The configuration method can be hard-coded in the config file by 41 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 42 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.12.38.4 2007/06/08 09:55:51 nisimura Exp $"); 47 48 #include <sys/types.h> 49 #include <sys/param.h> 50 #include <sys/device.h> 51 #include <sys/errno.h> 52 #include <sys/extent.h> 53 #include <sys/malloc.h> 54 #include <sys/queue.h> 55 #include <sys/systm.h> 56 #include <sys/time.h> 57 58 #include <uvm/uvm.h> 59 60 #define _POWERPC_BUS_DMA_PRIVATE 61 #include <machine/bus.h> 62 #include <machine/intr.h> 63 #include <machine/pio.h> 64 65 #include <dev/isa/isavar.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pciconf.h> 69 #include <dev/pci/pcidevs.h> 70 71 struct powerpc_bus_dma_tag pci_bus_dma_tag = { 72 0, /* _bounce_thresh */ 73 _bus_dmamap_create, 74 _bus_dmamap_destroy, 75 _bus_dmamap_load, 76 _bus_dmamap_load_mbuf, 77 _bus_dmamap_load_uio, 78 _bus_dmamap_load_raw, 79 _bus_dmamap_unload, 80 NULL, /* _dmamap_sync */ 81 _bus_dmamem_alloc, 82 _bus_dmamem_free, 83 _bus_dmamem_map, 84 _bus_dmamem_unmap, 85 _bus_dmamem_mmap, 86 }; 87 88 #define EPIC_DEBUGIRQ 89 90 static int brdtype; 91 #define BRD_SANDPOINTX2 2 92 #define BRD_SANDPOINTX3 3 93 #define BRD_ENCOREPP1 10 94 #define BRD_KUROBOX 100 95 #define BRD_QNAPTS101 101 96 #define BRD_SYNOLOGY 102 97 #define BRD_UNKNOWN -1 98 99 #define PCI_CONFIG_ENABLE 0x80000000UL 100 101 void 102 pci_attach_hook(parent, self, pba) 103 struct device *parent, *self; 104 struct pcibus_attach_args *pba; 105 { 106 pcitag_t tag; 107 pcireg_t dev11, dev22, dev15; 108 109 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 110 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 111 if (PCI_CLASS(dev11) == PCI_CLASS_BRIDGE) { 112 /* WinBond/Symphony Lab 83C553 at dev 11 */ 113 /* 114 * XXX distinguish SP3 from SP2 by fiddling ISA GPIO #7/6. 115 * XXX SP3 #7 output values loopback to #6 input. 116 */ 117 brdtype = BRD_SANDPOINTX3; 118 return; 119 } 120 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 22, 0); 121 dev22 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 122 if (PCI_CLASS(dev22) == PCI_CLASS_BRIDGE) { 123 /* VIA 82C686B at dev 22 */ 124 brdtype = BRD_ENCOREPP1; 125 return; 126 } 127 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 128 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 129 if (PCI_CLASS(dev11) == PCI_CLASS_NETWORK) { 130 /* tlp (ADMtek AN985) or re (RealTek 8169S) at dev 11 */ 131 brdtype = BRD_KUROBOX; 132 return; 133 } 134 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 15, 0); 135 dev15 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 136 if (PCI_VENDOR(dev15) == PCI_VENDOR_INTEL) { 137 /* Intel GbE at dev 15 */ 138 brdtype = BRD_QNAPTS101; 139 return; 140 } 141 if (PCI_VENDOR(dev15) == PCI_VENDOR_MARVELL) { 142 /* Marvell GbE at dev 15 */ 143 brdtype = BRD_SYNOLOGY; 144 return; 145 } 146 brdtype = BRD_UNKNOWN; 147 } 148 149 int 150 pci_bus_maxdevs(pc, busno) 151 pci_chipset_tag_t pc; 152 int busno; 153 { 154 155 /* 156 * Bus number is irrelevant. Configuration Mechanism 1 is in 157 * use, can have devices 0-32 (i.e. the `normal' range). 158 */ 159 return (32); 160 } 161 162 pcitag_t 163 pci_make_tag(pc, bus, device, function) 164 pci_chipset_tag_t pc; 165 int bus, device, function; 166 { 167 pcitag_t tag; 168 169 if (bus >= 256 || device >= 32 || function >= 8) 170 panic("pci_make_tag: bad request"); 171 172 tag = PCI_CONFIG_ENABLE | 173 (bus << 16) | (device << 11) | (function << 8); 174 return tag; 175 } 176 177 void 178 pci_decompose_tag(pc, tag, bp, dp, fp) 179 pci_chipset_tag_t pc; 180 pcitag_t tag; 181 int *bp, *dp, *fp; 182 { 183 184 if (bp != NULL) 185 *bp = (tag >> 16) & 0xff; 186 if (dp != NULL) 187 *dp = (tag >> 11) & 0x1f; 188 if (fp != NULL) 189 *fp = (tag >> 8) & 0x7; 190 return; 191 } 192 193 /* 194 * The Kahlua documentation says that "reg" should be left-shifted by two 195 * and be in bits 2-7. Apparently not. It doesn't work that way, and the 196 * DINK32 ROM doesn't do it that way (I peeked at 0xfec00000 after running 197 * the DINK32 "pcf" command). 198 */ 199 #define SP_PCI(tag, reg) ((tag) | (reg)) 200 201 pcireg_t 202 pci_conf_read(pc, tag, reg) 203 pci_chipset_tag_t pc; 204 pcitag_t tag; 205 int reg; 206 { 207 pcireg_t data; 208 209 out32rb(SANDPOINT_PCI_CONFIG_ADDR, SP_PCI(tag,reg)); 210 data = in32rb(SANDPOINT_PCI_CONFIG_DATA); 211 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 212 return data; 213 } 214 215 void 216 pci_conf_write(pc, tag, reg, data) 217 pci_chipset_tag_t pc; 218 pcitag_t tag; 219 int reg; 220 pcireg_t data; 221 { 222 out32rb(SANDPOINT_PCI_CONFIG_ADDR, SP_PCI(tag, reg)); 223 out32rb(SANDPOINT_PCI_CONFIG_DATA, data); 224 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 225 } 226 227 int 228 pci_intr_map(pa, ihp) 229 struct pci_attach_args *pa; 230 pci_intr_handle_t *ihp; 231 { 232 int pin = pa->pa_intrpin; 233 int line = pa->pa_intrline; 234 235 /* No IRQ used. */ 236 if (pin == 0) 237 goto bad; 238 if (pin > 4) { 239 aprint_error("pci_intr_map: bad interrupt pin %d\n", pin); 240 goto bad; 241 } 242 243 /* 244 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 245 * `unknown' or `no connection' on a PC. We assume that a device with 246 * `no connection' either doesn't have an interrupt (in which case the 247 * pin number should be 0, and would have been noticed above), or 248 * wasn't configured by the BIOS (in which case we punt, since there's 249 * no real way we can know how the interrupt lines are mapped in the 250 * hardware). 251 * 252 * XXX 253 * Since IRQ 0 is only used by the clock, and we can't actually be sure 254 * that the BIOS did its job, we also recognize that as meaning that 255 * the BIOS has not configured the device. 256 */ 257 if (line == 255) { 258 aprint_error("pci_intr_map: no mapping for pin %c\n", 259 '@' + pin); 260 goto bad; 261 } 262 #ifdef EPIC_DEBUGIRQ 263 printf("line %d, pin %c", line, pin + '@'); 264 #endif 265 switch (brdtype) { 266 /* Sandpoint has 4 PCI slots in a weird order. 267 * From next to MPMC mezzanine card toward the board edge, 268 * 64bit slot PCI AD14 269 * 64bit slot PCI AD13 270 * 32bit slot PCI AD16 271 * 32bit slot PCI AD15 272 * Don't believe identifying labels printed on PCB and 273 * documents confusing as well since Moto names the slots 274 * as number 1 origin. 275 * 276 * Sandpoint X3 "SP3" brd uses EPIC serial mode IRQ. WinBond 277 * SB i8259 PIC interrupt is wired to EPIC IRQ0 while AD13-16 278 * come through IRQ2-5. 279 * 280 * Sandpoint X2 brd uses EPIC direct mode IRQ. Interrupts 281 * from AD13-AD16 are wired with EPIC IRQ0-3. WinBond SB 282 * i8259 shares EPIC IRQ1 line with the PCI slot next to 283 * MPMC mezzanine card. WinBond IDE shares EPIC IRQ2 line. 284 */ 285 case BRD_SANDPOINTX3: 286 if (line == 11 287 && pa->pa_function == 1 && pa->pa_bus == 0) { 288 /* map pin A-D to EPIC IRQ6-9 */ 289 *ihp = 6 + (pin - 1); 290 break; 291 } 292 if (line < 13 || line > 16) { 293 aprint_error("pci_intr_map: bad interrupt line %d,%c\n", 294 line, pin + '@'); 295 goto bad; 296 } 297 /* map line 13-16 to EPIC IRQ2-5 */ 298 *ihp = line - 11; 299 break; 300 case BRD_SANDPOINTX2: 301 if (line == 11 302 && pa->pa_function == 1 && pa->pa_bus == 0) { 303 /* 83C553 PCI IDE comes thru EPIC IRQ2 */ 304 *ihp = 2; 305 break; 306 } 307 if (line < 13 || line > 16) { 308 aprint_error("pci_intr_map: bad interrupt line %d,%c\n", 309 line, pin + '@'); 310 goto bad; 311 } 312 /* map line 13-16 to EPIC IRQ0-3 */ 313 line -= 13; pin -= 1; 314 *ihp = (line + (4 - pin)) & 3; 315 break; 316 case BRD_ENCOREPP1: 317 /* 318 * Ampro EnCorePP1 brd uses EPIC direct mode IRQ. Via 686B SB 319 * i8259 interrupt goes through EPC IRQ0. PCI pin A-D are 320 * tied with EPIC IRQ1-4. 321 * AD22 pin A,B,C,D -> EPIC IRQ 1,2,3,4. 322 * AD23 pin A,B,C,D -> EPIC IRQ 2,3,4,1. 323 * AD24 pin A,B,C,D -> EPIC IRQ 3,4,1,2. 324 * AD25 pin A,B,C,D -> EPIC IRQ 4,1,2,3. 325 */ 326 *ihp = pin; 327 break; 328 line -= 22; pin -= 1; 329 *ihp = 1 + ((pin + line) & 3); 330 break; 331 case BRD_KUROBOX: 332 /* map line 11,12,13,14 to EPIC IRQ0,1,4,3 */ 333 *ihp = (line == 13) ? 4 : line - 11; 334 break; 335 case BRD_QNAPTS101: 336 /* map line 12-15 to EPIC IRQ0-3 */ 337 *ihp = line - 12; 338 break; 339 case BRD_SYNOLOGY: 340 /* map line 12,13-15 to EPIC IRQ4,0-2 */ 341 *ihp = (line == 12) ? 4 : line - 13; 342 break; 343 default: 344 /* map line 12-15 to EPIC IRQ0-3 */ 345 *ihp = line - 12; 346 break; 347 } 348 #ifdef EPIC_DEBUGIRQ 349 printf(" = EPIC %d\n", *ihp); 350 #endif 351 return 0; 352 bad: 353 *ihp = -1; 354 return 1; 355 } 356 357 const char * 358 pci_intr_string(pc, ih) 359 pci_chipset_tag_t pc; 360 pci_intr_handle_t ih; 361 { 362 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 363 364 if (ih < 0 || ih >= ICU_LEN) 365 panic("pci_intr_string: bogus handle 0x%x", ih); 366 367 sprintf(irqstr, "irq %d", ih + 16); 368 return (irqstr); 369 370 } 371 372 const struct evcnt * 373 pci_intr_evcnt(pc, ih) 374 pci_chipset_tag_t pc; 375 pci_intr_handle_t ih; 376 { 377 378 /* XXX for now, no evcnt parent reported */ 379 return NULL; 380 } 381 382 void * 383 pci_intr_establish(pc, ih, level, func, arg) 384 pci_chipset_tag_t pc; 385 pci_intr_handle_t ih; 386 int level, (*func) __P((void *)); 387 void *arg; 388 { 389 /* 390 * ih is the value assigned in pci_intr_map(), above. 391 * It's the EPIC IRQ #. 392 */ 393 return intr_establish(ih + 16, IST_LEVEL, level, func, arg); 394 } 395 396 void 397 pci_intr_disestablish(pc, cookie) 398 pci_chipset_tag_t pc; 399 void *cookie; 400 { 401 intr_disestablish(cookie); 402 } 403 404 void 405 pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin, int swiz, 406 int *iline) 407 { 408 if (bus == 0) { 409 *iline = dev; 410 } else { 411 /* 412 * If we are not on bus zero, we're behind a bridge, so we 413 * swizzle. 414 * 415 * The documentation lies about this. In slot 3 (numbering 416 * from 0) aka device 16, INTD# becomes an interrupt for 417 * slot 2. INTC# becomes an interrupt for slot 1, etc. 418 * In slot 2 aka device 16, INTD# becomes an interrupt for 419 * slot 1, etc. 420 * 421 * Verified for INTD# on device 16, INTC# on device 16, 422 * INTD# on device 15, INTD# on device 13, and INTC# on 423 * device 14. I presume that the rest follow the same 424 * pattern. 425 * 426 * Slot 0 is device 13, and is the base for the rest. 427 */ 428 *iline = 13 + ((swiz + dev + 3) & 3); 429 } 430 } 431
Indexes created Mon Oct 27 17:09:47 GMT 2025