pci_machdep.c revision 1.22
1 /* $NetBSD: pci_machdep.c,v 1.22 2011/02/10 13:54:45 nisimura Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Machine-specific functions for PCI autoconfiguration. 35 * 36 * On PCs, there are two methods of generating PCI configuration cycles. 37 * We try to detect the appropriate mechanism for this machine and set 38 * up a few function pointers to access the correct method directly. 39 * 40 * The configuration method can be hard-coded in the config file by 41 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 42 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.22 2011/02/10 13:54:45 nisimura Exp $"); 47 48 #include "opt_pci.h" 49 50 #include <sys/types.h> 51 #include <sys/param.h> 52 #include <sys/device.h> 53 #include <sys/errno.h> 54 #include <sys/extent.h> 55 #include <sys/malloc.h> 56 #include <sys/queue.h> 57 #include <sys/systm.h> 58 #include <sys/time.h> 59 60 #define _POWERPC_BUS_DMA_PRIVATE 61 #include <machine/bus.h> 62 #include <machine/intr.h> 63 #include <machine/pio.h> 64 65 #include <dev/isa/isavar.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pciconf.h> 69 #include <dev/pci/pcidevs.h> 70 71 struct powerpc_bus_dma_tag pci_bus_dma_tag = { 72 0, /* _bounce_thresh */ 73 _bus_dmamap_create, 74 _bus_dmamap_destroy, 75 _bus_dmamap_load, 76 _bus_dmamap_load_mbuf, 77 _bus_dmamap_load_uio, 78 _bus_dmamap_load_raw, 79 _bus_dmamap_unload, 80 NULL, /* _dmamap_sync */ 81 _bus_dmamem_alloc, 82 _bus_dmamem_free, 83 _bus_dmamem_map, 84 _bus_dmamem_unmap, 85 _bus_dmamem_mmap, 86 }; 87 88 /*#define EPIC_DEBUGIRQ*/ 89 90 static int brdtype; 91 #define BRD_SANDPOINTX2 2 92 #define BRD_SANDPOINTX3 3 93 #define BRD_ENCOREPP1 10 94 #define BRD_KUROBOX 100 95 #define BRD_QNAPTS101 101 96 #define BRD_SYNOLOGY 102 97 #define BRD_STORCENTER 103 98 #define BRD_DLINKDSM 104 99 #define BRD_UNKNOWN -1 100 101 #define PCI_CONFIG_ENABLE 0x80000000UL 102 103 void 104 pci_attach_hook(struct device *parent, struct device *self, 105 struct pcibus_attach_args *pba) 106 { 107 pcitag_t tag; 108 pcireg_t dev11, dev22, dev15, dev13, dev16; 109 110 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 111 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 112 if (PCI_CLASS(dev11) == PCI_CLASS_BRIDGE) { 113 /* WinBond/Symphony Lab 83C553 at dev 11 */ 114 /* 115 * XXX distinguish SP3 from SP2 by fiddling ISA GPIO #7/6. 116 * XXX SP3 #7 output values loopback to #6 input. 117 */ 118 brdtype = BRD_SANDPOINTX3; 119 return; 120 } 121 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 22, 0); 122 dev22 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 123 if (PCI_CLASS(dev22) == PCI_CLASS_BRIDGE) { 124 /* VIA 82C686B at dev 22 */ 125 brdtype = BRD_ENCOREPP1; 126 return; 127 } 128 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 129 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 130 if (PCI_CLASS(dev11) == PCI_CLASS_NETWORK) { 131 /* tlp (ADMtek AN985) or re (RealTek 8169S) at dev 11 */ 132 brdtype = BRD_KUROBOX; 133 return; 134 } 135 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 15, 0); 136 dev15 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 137 if (PCI_VENDOR(dev15) == PCI_VENDOR_INTEL) { 138 /* Intel GbE at dev 15 */ 139 brdtype = BRD_QNAPTS101; 140 return; 141 } 142 if (PCI_VENDOR(dev15) == PCI_VENDOR_MARVELL) { 143 /* Marvell GbE at dev 15 */ 144 brdtype = BRD_SYNOLOGY; 145 return; 146 } 147 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 13, 0); 148 dev13 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 149 if (PCI_VENDOR(dev13) == PCI_VENDOR_VIATECH) { 150 /* VIA 6410 PCIIDE at dev 13 */ 151 brdtype = BRD_STORCENTER; 152 return; 153 } 154 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 16, 0); 155 dev16 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 156 if (PCI_VENDOR(dev16) == PCI_VENDOR_ACARD) { 157 /* ACARD ATP865 at dev 16 */ 158 brdtype = BRD_DLINKDSM; 159 return; 160 } 161 162 brdtype = BRD_UNKNOWN; 163 } 164 165 int 166 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 167 { 168 169 return 32; 170 } 171 172 pcitag_t 173 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 174 { 175 pcitag_t tag; 176 177 if (bus >= 256 || device >= 32 || function >= 8) 178 panic("pci_make_tag: bad request"); 179 180 tag = PCI_CONFIG_ENABLE | 181 (bus << 16) | (device << 11) | (function << 8); 182 return tag; 183 } 184 185 void 186 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 187 int *bp, int *dp, int *fp) 188 { 189 190 if (bp != NULL) 191 *bp = (tag >> 16) & 0xff; 192 if (dp != NULL) 193 *dp = (tag >> 11) & 0x1f; 194 if (fp != NULL) 195 *fp = (tag >> 8) & 0x7; 196 return; 197 } 198 199 /* 200 * The Kahlua documentation says that "reg" should be left-shifted by two 201 * and be in bits 2-7. Apparently not. It doesn't work that way, and the 202 * DINK32 ROM doesn't do it that way (I peeked at 0xfec00000 after running 203 * the DINK32 "pcf" command). 204 */ 205 pcireg_t 206 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 207 { 208 pcireg_t data; 209 210 out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg); 211 data = in32rb(SANDPOINT_PCI_CONFIG_DATA); 212 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 213 return data; 214 } 215 216 void 217 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 218 { 219 220 out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg); 221 out32rb(SANDPOINT_PCI_CONFIG_DATA, data); 222 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 223 } 224 225 int 226 pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 227 { 228 int pin = pa->pa_intrpin; 229 int line = pa->pa_intrline; 230 231 /* No IRQ used. */ 232 if (pin == 0) 233 goto bad; 234 if (pin > 4) { 235 aprint_error("pci_intr_map: bad interrupt pin %d\n", pin); 236 goto bad; 237 } 238 239 /* 240 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 241 * `unknown' or `no connection' on a PC. We assume that a device with 242 * `no connection' either doesn't have an interrupt (in which case the 243 * pin number should be 0, and would have been noticed above), or 244 * wasn't configured by the BIOS (in which case we punt, since there's 245 * no real way we can know how the interrupt lines are mapped in the 246 * hardware). 247 * 248 * XXX 249 * Since IRQ 0 is only used by the clock, and we can't actually be sure 250 * that the BIOS did its job, we also recognize that as meaning that 251 * the BIOS has not configured the device. 252 */ 253 if (line == 255) { 254 aprint_error("pci_intr_map: no mapping for pin %c\n", 255 '@' + pin); 256 goto bad; 257 } 258 #ifdef EPIC_DEBUGIRQ 259 printf("line %d, pin %c", line, pin + '@'); 260 #endif 261 switch (brdtype) { 262 /* Sandpoint has 4 PCI slots in a weird order. 263 * From next to MPMC mezzanine card toward the board edge, 264 * 64bit slot PCI AD14 265 * 64bit slot PCI AD13 266 * 32bit slot PCI AD16 267 * 32bit slot PCI AD15 268 * Don't believe identifying labels printed on PCB and 269 * documents confusing as well since Moto names the slots 270 * as number 1 origin. 271 */ 272 case BRD_SANDPOINTX3: 273 /* 274 * Sandpoint X3 brd uses EPIC serial mode IRQ. 275 * - i8259 PIC interrupt to EPIC IRQ0. 276 * - WinBond IDE PCI C/D to EPIC IRQ8/9. 277 * - PCI AD13 pin A to EPIC IRQ2. 278 * - PCI AD14 pin A to EPIC IRQ3. 279 * - PCI AD15 pin A to EPIC IRQ4. 280 * - PCI AD16 pin A to EPIC IRQ5. 281 */ 282 if (line == 11 283 && pa->pa_function == 1 && pa->pa_bus == 0) { 284 /* X3 wires 83c553 pin C,D to EPIC IRQ8,9 */ 285 *ihp = 8; /* pin C only, indeed */ 286 break; 287 } 288 if (line < 13 || line > 16) { 289 aprint_error("pci_intr_map: bad interrupt line %d,%c\n", 290 line, pin + '@'); 291 goto bad; 292 } 293 line -= 13; /* B/C/D is not available */ 294 *ihp = 2 + line; 295 break; 296 case BRD_SANDPOINTX2: 297 /* 298 * Sandpoint X2 brd uses EPIC direct mode IRQ. 299 * - i8259 PIC interrupt EPIC IRQ2. 300 * - PCI AD13 pin A,B,C,D to EPIC IRQ0,1,2,3. 301 * - PCI AD14 pin A,B,C,D to EPIC IRQ1,2,3,0. 302 * - PCI AD15 pin A,B,C,D to EPIC IRQ2,3,0,1. 303 * - PCI AD16 pin A,B,C,D to EPIC IRQ3,0,1,2. 304 * - PCI AD12 is wired to PMPC device itself. 305 */ 306 if (line == 11 307 && pa->pa_function == 1 && pa->pa_bus == 0) { 308 /* 83C553 PCI IDE comes thru EPIC IRQ2 */ 309 *ihp = 2; 310 break; 311 } 312 if (line < 13 || line > 16) { 313 aprint_error("pci_intr_map: bad interrupt line %d,%c\n", 314 line, pin + '@'); 315 goto bad; 316 } 317 line -= 13; pin -= 1; 318 *ihp = (line + pin) & 03; 319 break; 320 case BRD_ENCOREPP1: 321 /* 322 * Ampro EnCorePP1 brd uses EPIC direct mode IRQ. 323 * PDF says VIA 686B SB i8259 interrupt goes through EPC IRQ0, 324 * while PCI pin A-D are tied with EPIC IRQ1-4. 325 * 326 * It mentions i82559 is at AD24, however, found at AD25 instead. 327 * Heuristics show that i82559 responds to EPIC 2 (!). Then we 328 * decided to return EPIC 2 here since i82559 is the only one PCI 329 * device ENCPP1 can have; 330 */ 331 if (pa->pa_device != 25) 332 goto bad; /* eeh !? */ 333 *ihp = 2; 334 break; 335 case BRD_KUROBOX: 336 /* map line 11,12,13,14 to EPIC IRQ0,1,4,3 */ 337 *ihp = (line == 13) ? 4 : line - 11; 338 break; 339 case BRD_QNAPTS101: 340 /* map line 13-16 to EPIC IRQ0-3 */ 341 *ihp = line - 13; 342 break; 343 case BRD_SYNOLOGY: 344 /* map line 12,13-15 to EPIC IRQ4,0-2 */ 345 *ihp = (line == 12) ? 4 : line - 13; 346 break; 347 case BRD_DLINKDSM: 348 /* map line 13,14,15,16 to EPIC IRQ0,1,3,4 */ 349 *ihp = (line < 15) ? line - 13 : line - 12; 350 break; 351 case BRD_STORCENTER: 352 default: 353 /* map line 12-15 to EPIC IRQ0-3 */ 354 *ihp = line - 12; 355 break; 356 } 357 #ifdef EPIC_DEBUGIRQ 358 printf(" = EPIC %d\n", *ihp); 359 #endif 360 return 0; 361 bad: 362 *ihp = -1; 363 return 1; 364 } 365 366 const char * 367 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 368 { 369 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 370 371 if (ih < 0 || ih >= OPENPIC_ICU) 372 panic("pci_intr_string: bogus handle 0x%x", ih); 373 374 sprintf(irqstr, "irq %d", ih + I8259_ICU); 375 return (irqstr); 376 377 } 378 379 const struct evcnt * 380 pci_intr_evcnt(void *v, pci_intr_handle_t ih) 381 { 382 383 /* XXX for now, no evcnt parent reported */ 384 return NULL; 385 } 386 387 int 388 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih, 389 int attr, uint64_t data) 390 { 391 392 switch (attr) { 393 case PCI_INTR_MPSAFE: 394 return 0; 395 default: 396 return ENODEV; 397 } 398 } 399 400 void * 401 pci_intr_establish(void *v, pci_intr_handle_t ih, int level, 402 int (*func)(void *), void *arg) 403 { 404 /* 405 * ih is the value assigned in pci_intr_map(), above. 406 * It's the EPIC IRQ #. 407 */ 408 return intr_establish(ih + I8259_ICU, IST_LEVEL, level, func, arg); 409 } 410 411 void 412 pci_intr_disestablish(void *v, void *cookie) 413 { 414 415 intr_disestablish(cookie); 416 } 417 418 #if defined(PCI_NETBSD_CONFIGURE) 419 void 420 pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, 421 int pin, int swiz, int *iline) 422 { 423 if (bus == 0) { 424 *iline = dev; 425 } else { 426 /* 427 * If we are not on bus zero, we're behind a bridge, so we 428 * swizzle. 429 * 430 * The documentation lies about this. In slot 3 (numbering 431 * from 0) aka device 16, INTD# becomes an interrupt for 432 * slot 2. INTC# becomes an interrupt for slot 1, etc. 433 * In slot 2 aka device 16, INTD# becomes an interrupt for 434 * slot 1, etc. 435 * 436 * Verified for INTD# on device 16, INTC# on device 16, 437 * INTD# on device 15, INTD# on device 13, and INTC# on 438 * device 14. I presume that the rest follow the same 439 * pattern. 440 * 441 * Slot 0 is device 13, and is the base for the rest. 442 */ 443 *iline = 13 + ((swiz + dev + 3) & 3); 444 } 445 } 446 #endif 447
Indexes created Fri Sep 26 20:09:58 GMT 2025