pci_machdep.c revision 1.26
1 /* $NetBSD: pci_machdep.c,v 1.26 2011/04/04 20:37:53 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Machine-specific functions for PCI autoconfiguration. 35 * 36 * On PCs, there are two methods of generating PCI configuration cycles. 37 * We try to detect the appropriate mechanism for this machine and set 38 * up a few function pointers to access the correct method directly. 39 * 40 * The configuration method can be hard-coded in the config file by 41 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 42 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.26 2011/04/04 20:37:53 dyoung Exp $"); 47 48 #include "opt_pci.h" 49 50 #include <sys/types.h> 51 #include <sys/param.h> 52 #include <sys/device.h> 53 #include <sys/errno.h> 54 #include <sys/extent.h> 55 #include <sys/malloc.h> 56 #include <sys/queue.h> 57 #include <sys/systm.h> 58 #include <sys/time.h> 59 60 #define _POWERPC_BUS_DMA_PRIVATE 61 #include <machine/bus.h> 62 #include <machine/intr.h> 63 #include <machine/pio.h> 64 65 #include <dev/isa/isavar.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pciconf.h> 69 #include <dev/pci/pcidevs.h> 70 71 struct powerpc_bus_dma_tag pci_bus_dma_tag = { 72 0, /* _bounce_thresh */ 73 _bus_dmamap_create, 74 _bus_dmamap_destroy, 75 _bus_dmamap_load, 76 _bus_dmamap_load_mbuf, 77 _bus_dmamap_load_uio, 78 _bus_dmamap_load_raw, 79 _bus_dmamap_unload, 80 NULL, /* _dmamap_sync */ 81 _bus_dmamem_alloc, 82 _bus_dmamem_free, 83 _bus_dmamem_map, 84 _bus_dmamem_unmap, 85 _bus_dmamem_mmap, 86 }; 87 88 /*#define EPIC_DEBUGIRQ*/ 89 90 static int brdtype; 91 #define BRD_SANDPOINTX2 2 92 #define BRD_SANDPOINTX3 3 93 #define BRD_ENCOREPP1 10 94 #define BRD_KUROBOX 100 95 #define BRD_QNAPTS 101 96 #define BRD_SYNOLOGY 102 97 #define BRD_STORCENTER 103 98 #define BRD_DLINKDSM 104 99 #define BRD_NH230NAS 105 100 #define BRD_UNKNOWN -1 101 102 #define PCI_CONFIG_ENABLE 0x80000000UL 103 104 void 105 pci_attach_hook(struct device *parent, struct device *self, 106 struct pcibus_attach_args *pba) 107 { 108 pcitag_t tag; 109 pcireg_t dev11, dev22, dev15, dev13, dev16; 110 111 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 112 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 113 if (PCI_CLASS(dev11) == PCI_CLASS_BRIDGE) { 114 /* WinBond/Symphony Lab 83C553 at dev 11 */ 115 /* 116 * XXX distinguish SP3 from SP2 by fiddling ISA GPIO #7/6. 117 * XXX SP3 #7 output values loopback to #6 input. 118 */ 119 brdtype = BRD_SANDPOINTX3; 120 return; 121 } 122 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 22, 0); 123 dev22 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 124 if (PCI_CLASS(dev22) == PCI_CLASS_BRIDGE) { 125 /* VIA 82C686B at dev 22 */ 126 brdtype = BRD_ENCOREPP1; 127 return; 128 } 129 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 130 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 131 if (PCI_CLASS(dev11) == PCI_CLASS_NETWORK) { 132 /* tlp (ADMtek AN985) or re (RealTek 8169S) at dev 11 */ 133 brdtype = BRD_KUROBOX; 134 return; 135 } 136 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 15, 0); 137 dev15 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 138 if (PCI_VENDOR(dev15) == PCI_VENDOR_INTEL 139 || PCI_VENDOR(dev15) == PCI_VENDOR_REALTEK) { 140 /* Intel or Realtek GbE at dev 15 */ 141 brdtype = BRD_QNAPTS; 142 return; 143 } 144 if (PCI_VENDOR(dev15) == PCI_VENDOR_MARVELL) { 145 /* Marvell GbE at dev 15 */ 146 brdtype = BRD_SYNOLOGY; 147 return; 148 } 149 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 13, 0); 150 dev13 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 151 if (PCI_VENDOR(dev13) == PCI_VENDOR_VIATECH) { 152 /* VIA 6410 PCIIDE at dev 13 */ 153 brdtype = BRD_STORCENTER; 154 return; 155 } 156 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 16, 0); 157 dev16 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 158 if (PCI_VENDOR(dev16) == PCI_VENDOR_ACARD) { 159 /* ACARD ATP865 at dev 16 */ 160 brdtype = BRD_DLINKDSM; 161 return; 162 } 163 if (PCI_VENDOR(dev16) == PCI_VENDOR_ITE 164 || PCI_VENDOR(dev16) == PCI_VENDOR_CMDTECH) { 165 brdtype = BRD_NH230NAS; 166 return; 167 } 168 169 brdtype = BRD_UNKNOWN; 170 } 171 172 int 173 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 174 { 175 176 return 32; 177 } 178 179 pcitag_t 180 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 181 { 182 pcitag_t tag; 183 184 if (bus >= 256 || device >= 32 || function >= 8) 185 panic("pci_make_tag: bad request"); 186 187 tag = PCI_CONFIG_ENABLE | 188 (bus << 16) | (device << 11) | (function << 8); 189 return tag; 190 } 191 192 void 193 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 194 int *bp, int *dp, int *fp) 195 { 196 197 if (bp != NULL) 198 *bp = (tag >> 16) & 0xff; 199 if (dp != NULL) 200 *dp = (tag >> 11) & 0x1f; 201 if (fp != NULL) 202 *fp = (tag >> 8) & 0x7; 203 return; 204 } 205 206 /* 207 * The Kahlua documentation says that "reg" should be left-shifted by two 208 * and be in bits 2-7. Apparently not. It doesn't work that way, and the 209 * DINK32 ROM doesn't do it that way (I peeked at 0xfec00000 after running 210 * the DINK32 "pcf" command). 211 */ 212 pcireg_t 213 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 214 { 215 pcireg_t data; 216 217 out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg); 218 data = in32rb(SANDPOINT_PCI_CONFIG_DATA); 219 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 220 return data; 221 } 222 223 void 224 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 225 { 226 227 out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg); 228 out32rb(SANDPOINT_PCI_CONFIG_DATA, data); 229 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 230 } 231 232 int 233 pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 234 { 235 int pin = pa->pa_intrpin; 236 int line = pa->pa_intrline; 237 238 /* No IRQ used. */ 239 if (pin == 0) 240 goto bad; 241 if (pin > 4) { 242 aprint_error("pci_intr_map: bad interrupt pin %d\n", pin); 243 goto bad; 244 } 245 246 /* 247 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 248 * `unknown' or `no connection' on a PC. We assume that a device with 249 * `no connection' either doesn't have an interrupt (in which case the 250 * pin number should be 0, and would have been noticed above), or 251 * wasn't configured by the BIOS (in which case we punt, since there's 252 * no real way we can know how the interrupt lines are mapped in the 253 * hardware). 254 * 255 * XXX 256 * Since IRQ 0 is only used by the clock, and we can't actually be sure 257 * that the BIOS did its job, we also recognize that as meaning that 258 * the BIOS has not configured the device. 259 */ 260 if (line == 255) { 261 aprint_error("pci_intr_map: no mapping for pin %c\n", 262 '@' + pin); 263 goto bad; 264 } 265 #ifdef EPIC_DEBUGIRQ 266 printf("line %d, pin %c", line, pin + '@'); 267 #endif 268 switch (brdtype) { 269 /* Sandpoint has 4 PCI slots in a weird order. 270 * From next to MPMC mezzanine card toward the board edge, 271 * 64bit slot PCI AD14 272 * 64bit slot PCI AD13 273 * 32bit slot PCI AD16 274 * 32bit slot PCI AD15 275 * Don't believe identifying labels printed on PCB and 276 * documents confusing as well since Moto names the slots 277 * as number 1 origin. 278 */ 279 case BRD_SANDPOINTX3: 280 /* 281 * Sandpoint X3 brd uses EPIC serial mode IRQ. 282 * - i8259 PIC interrupt to EPIC IRQ0. 283 * - WinBond IDE PCI C/D to EPIC IRQ8/9. 284 * - PCI AD13 pin A to EPIC IRQ2. 285 * - PCI AD14 pin A to EPIC IRQ3. 286 * - PCI AD15 pin A to EPIC IRQ4. 287 * - PCI AD16 pin A to EPIC IRQ5. 288 */ 289 if (line == 11 290 && pa->pa_function == 1 && pa->pa_bus == 0) { 291 /* X3 wires 83c553 pin C,D to EPIC IRQ8,9 */ 292 *ihp = 8; /* pin C only, indeed */ 293 break; 294 } 295 if (line < 13 || line > 16) { 296 aprint_error("pci_intr_map: bad interrupt line %d,%c\n", 297 line, pin + '@'); 298 goto bad; 299 } 300 line -= 13; /* B/C/D is not available */ 301 *ihp = 2 + line; 302 break; 303 case BRD_SANDPOINTX2: 304 /* 305 * Sandpoint X2 brd uses EPIC direct mode IRQ. 306 * - i8259 PIC interrupt EPIC IRQ2. 307 * - PCI AD13 pin A,B,C,D to EPIC IRQ0,1,2,3. 308 * - PCI AD14 pin A,B,C,D to EPIC IRQ1,2,3,0. 309 * - PCI AD15 pin A,B,C,D to EPIC IRQ2,3,0,1. 310 * - PCI AD16 pin A,B,C,D to EPIC IRQ3,0,1,2. 311 * - PCI AD12 is wired to PMPC device itself. 312 */ 313 if (line == 11 314 && pa->pa_function == 1 && pa->pa_bus == 0) { 315 /* 83C553 PCI IDE comes thru EPIC IRQ2 */ 316 *ihp = 2; 317 break; 318 } 319 if (line < 13 || line > 16) { 320 aprint_error("pci_intr_map: bad interrupt line %d,%c\n", 321 line, pin + '@'); 322 goto bad; 323 } 324 line -= 13; pin -= 1; 325 *ihp = (line + pin) & 03; 326 break; 327 case BRD_ENCOREPP1: 328 /* 329 * Ampro EnCorePP1 brd uses EPIC direct mode IRQ. 330 * PDF says VIA 686B SB i8259 interrupt goes through EPC IRQ0, 331 * while PCI pin A-D are tied with EPIC IRQ1-4. 332 * 333 * It mentions i82559 is at AD24, however, found at AD25 instead. 334 * Heuristics show that i82559 responds to EPIC 2 (!). Then we 335 * decided to return EPIC 2 here since i82559 is the only one PCI 336 * device ENCPP1 can have; 337 */ 338 if (pa->pa_device != 25) 339 goto bad; /* eeh !? */ 340 *ihp = 2; 341 break; 342 case BRD_KUROBOX: 343 /* map line 11,12,13,14 to EPIC IRQ0,1,4,3 */ 344 *ihp = (line == 13) ? 4 : line - 11; 345 break; 346 case BRD_QNAPTS: 347 /* map line 13-16 to EPIC IRQ0-3 */ 348 *ihp = line - 13; 349 break; 350 case BRD_SYNOLOGY: 351 /* map line 12,13-15 to EPIC IRQ4,0-2 */ 352 *ihp = (line == 12) ? 4 : line - 13; 353 break; 354 case BRD_DLINKDSM: 355 /* map line 13,14,15,16 to EPIC IRQ0,1,3,4 */ 356 *ihp = (line < 15) ? line - 13 : line - 12; 357 if (line == 14 && pin == 3) 358 *ihp += 1; /* USB pin C (EHCI) uses next IRQ */ 359 break; 360 case BRD_NH230NAS: 361 /* map line 13,14,15,16 to EPIC IRQ0,3,1,2 */ 362 *ihp = (line == 16) ? 2 : 363 (line == 15) ? 1 : 364 (line == 14) ? 3 : 0; 365 break; 366 case BRD_STORCENTER: 367 default: 368 /* map line 12-15 to EPIC IRQ0-3 */ 369 *ihp = line - 12; 370 break; 371 } 372 #ifdef EPIC_DEBUGIRQ 373 printf(" = EPIC %d\n", *ihp); 374 #endif 375 return 0; 376 bad: 377 *ihp = -1; 378 return 1; 379 } 380 381 const char * 382 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 383 { 384 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 385 386 if (ih < 0 || ih >= OPENPIC_ICU) 387 panic("pci_intr_string: bogus handle 0x%x", ih); 388 389 sprintf(irqstr, "irq %d", ih + I8259_ICU); 390 return (irqstr); 391 392 } 393 394 const struct evcnt * 395 pci_intr_evcnt(void *v, pci_intr_handle_t ih) 396 { 397 398 /* XXX for now, no evcnt parent reported */ 399 return NULL; 400 } 401 402 int 403 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih, 404 int attr, uint64_t data) 405 { 406 407 switch (attr) { 408 case PCI_INTR_MPSAFE: 409 return 0; 410 default: 411 return ENODEV; 412 } 413 } 414 415 void * 416 pci_intr_establish(void *v, pci_intr_handle_t ih, int level, 417 int (*func)(void *), void *arg) 418 { 419 /* 420 * ih is the value assigned in pci_intr_map(), above. 421 * It's the EPIC IRQ #. 422 */ 423 return intr_establish(ih + I8259_ICU, IST_LEVEL, level, func, arg); 424 } 425 426 void 427 pci_intr_disestablish(void *v, void *cookie) 428 { 429 430 intr_disestablish(cookie); 431 } 432 433 #if defined(PCI_NETBSD_CONFIGURE) 434 void 435 pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, 436 int pin, int swiz, int *iline) 437 { 438 if (bus == 0) { 439 *iline = dev; 440 } else { 441 /* 442 * If we are not on bus zero, we're behind a bridge, so we 443 * swizzle. 444 * 445 * The documentation lies about this. In slot 3 (numbering 446 * from 0) aka device 16, INTD# becomes an interrupt for 447 * slot 2. INTC# becomes an interrupt for slot 1, etc. 448 * In slot 2 aka device 16, INTD# becomes an interrupt for 449 * slot 1, etc. 450 * 451 * Verified for INTD# on device 16, INTC# on device 16, 452 * INTD# on device 15, INTD# on device 13, and INTC# on 453 * device 14. I presume that the rest follow the same 454 * pattern. 455 * 456 * Slot 0 is device 13, and is the base for the rest. 457 */ 458 *iline = 13 + ((swiz + dev + 3) & 3); 459 } 460 } 461 #endif 462
Indexes created Sat Sep 27 14:09:57 GMT 2025