pci_machdep.c revision 1.34.2.1
1 /* $NetBSD: pci_machdep.c,v 1.34.2.1 2016/11/04 14:49:04 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Machine-specific functions for PCI autoconfiguration. 35 * 36 * On PCs, there are two methods of generating PCI configuration cycles. 37 * We try to detect the appropriate mechanism for this machine and set 38 * up a few function pointers to access the correct method directly. 39 * 40 * The configuration method can be hard-coded in the config file by 41 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 42 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.34.2.1 2016/11/04 14:49:04 pgoyette Exp $"); 47 48 #include "opt_pci.h" 49 50 #include <sys/types.h> 51 #include <sys/param.h> 52 #include <sys/device.h> 53 #include <sys/errno.h> 54 #include <sys/extent.h> 55 #include <sys/kmem.h> 56 #include <sys/malloc.h> 57 #include <sys/queue.h> 58 #include <sys/systm.h> 59 #include <sys/time.h> 60 61 #define _POWERPC_BUS_DMA_PRIVATE 62 #include <sys/bus.h> 63 #include <machine/intr.h> 64 #include <machine/pio.h> 65 66 #include <dev/isa/isavar.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pciconf.h> 70 #include <dev/pci/pcidevs.h> 71 72 struct powerpc_bus_dma_tag pci_bus_dma_tag = { 73 0, /* _bounce_thresh */ 74 _bus_dmamap_create, 75 _bus_dmamap_destroy, 76 _bus_dmamap_load, 77 _bus_dmamap_load_mbuf, 78 _bus_dmamap_load_uio, 79 _bus_dmamap_load_raw, 80 _bus_dmamap_unload, 81 NULL, /* _dmamap_sync */ 82 _bus_dmamem_alloc, 83 _bus_dmamem_free, 84 _bus_dmamem_map, 85 _bus_dmamem_unmap, 86 _bus_dmamem_mmap, 87 }; 88 89 /*#define EPIC_DEBUGIRQ*/ 90 91 static int brdtype; 92 #define BRD_SANDPOINTX2 2 93 #define BRD_SANDPOINTX3 3 94 #define BRD_ENCOREPP1 10 95 #define BRD_KUROBOX 100 96 #define BRD_QNAPTS 101 97 #define BRD_SYNOLOGY 102 98 #define BRD_STORCENTER 103 99 #define BRD_DLINKDSM 104 100 #define BRD_NH230NAS 105 101 #define BRD_UNKNOWN -1 102 103 #define PCI_CONFIG_ENABLE 0x80000000UL 104 105 void 106 pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 107 { 108 pcitag_t tag; 109 pcireg_t dev11, dev22, dev15, dev13, dev16; 110 111 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 112 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 113 if (PCI_CLASS(dev11) == PCI_CLASS_BRIDGE) { 114 /* WinBond/Symphony Lab 83C553 at dev 11 */ 115 /* 116 * XXX distinguish SP3 from SP2 by fiddling ISA GPIO #7/6. 117 * XXX SP3 #7 output values loopback to #6 input. 118 */ 119 brdtype = BRD_SANDPOINTX3; 120 return; 121 } 122 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 22, 0); 123 dev22 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 124 if (PCI_CLASS(dev22) == PCI_CLASS_BRIDGE) { 125 /* VIA 82C686B at dev 22 */ 126 brdtype = BRD_ENCOREPP1; 127 return; 128 } 129 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 130 dev11 = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 131 if (PCI_CLASS(dev11) == PCI_CLASS_NETWORK) { 132 /* tlp (ADMtek AN985) or re (RealTek 8169S) at dev 11 */ 133 brdtype = BRD_KUROBOX; 134 return; 135 } 136 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 15, 0); 137 dev15 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 138 if (PCI_VENDOR(dev15) == PCI_VENDOR_MARVELL) { 139 /* Marvell GbE at dev 15 */ 140 brdtype = BRD_SYNOLOGY; 141 return; 142 } 143 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 13, 0); 144 dev13 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 145 if (PCI_VENDOR(dev13) == PCI_VENDOR_VIATECH) { 146 /* VIA 6410 PCIIDE at dev 13 */ 147 brdtype = BRD_STORCENTER; 148 return; 149 } 150 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 16, 0); 151 dev16 = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 152 if (PCI_VENDOR(dev16) == PCI_VENDOR_ACARD) { 153 /* ACARD ATP865 at dev 16 */ 154 brdtype = BRD_DLINKDSM; 155 return; 156 } 157 if (PCI_VENDOR(dev16) == PCI_VENDOR_ITE 158 || PCI_VENDOR(dev16) == PCI_VENDOR_CMDTECH) { 159 brdtype = BRD_NH230NAS; 160 return; 161 } 162 if (PCI_VENDOR(dev15) == PCI_VENDOR_INTEL 163 || PCI_VENDOR(dev15) == PCI_VENDOR_REALTEK) { 164 /* Intel or Realtek GbE at dev 15 */ 165 brdtype = BRD_QNAPTS; 166 return; 167 } 168 169 brdtype = BRD_UNKNOWN; 170 } 171 172 int 173 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 174 { 175 176 return 32; 177 } 178 179 pcitag_t 180 pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 181 { 182 pcitag_t tag; 183 184 if (bus >= 256 || device >= 32 || function >= 8) 185 panic("pci_make_tag: bad request"); 186 187 tag = PCI_CONFIG_ENABLE | 188 (bus << 16) | (device << 11) | (function << 8); 189 return tag; 190 } 191 192 void 193 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 194 int *bp, int *dp, int *fp) 195 { 196 197 if (bp != NULL) 198 *bp = (tag >> 16) & 0xff; 199 if (dp != NULL) 200 *dp = (tag >> 11) & 0x1f; 201 if (fp != NULL) 202 *fp = (tag >> 8) & 0x7; 203 return; 204 } 205 206 /* 207 * The Kahlua documentation says that "reg" should be left-shifted by two 208 * and be in bits 2-7. Apparently not. It doesn't work that way, and the 209 * DINK32 ROM doesn't do it that way (I peeked at 0xfec00000 after running 210 * the DINK32 "pcf" command). 211 */ 212 pcireg_t 213 pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 214 { 215 pcireg_t data; 216 217 if ((unsigned int)reg >= PCI_CONF_SIZE) 218 return (pcireg_t) -1; 219 220 out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg); 221 data = in32rb(SANDPOINT_PCI_CONFIG_DATA); 222 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 223 return data; 224 } 225 226 void 227 pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 228 { 229 230 if ((unsigned int)reg >= PCI_CONF_SIZE) 231 return; 232 233 out32rb(SANDPOINT_PCI_CONFIG_ADDR, tag | reg); 234 out32rb(SANDPOINT_PCI_CONFIG_DATA, data); 235 out32rb(SANDPOINT_PCI_CONFIG_ADDR, 0); 236 } 237 238 int 239 pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 240 { 241 int pin = pa->pa_intrpin; 242 int line = pa->pa_intrline; 243 244 /* No IRQ used. */ 245 if (pin == 0) 246 goto bad; 247 if (pin > 4) { 248 aprint_error("pci_intr_map: bad interrupt pin %d\n", pin); 249 goto bad; 250 } 251 252 /* 253 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 254 * `unknown' or `no connection' on a PC. We assume that a device with 255 * `no connection' either doesn't have an interrupt (in which case the 256 * pin number should be 0, and would have been noticed above), or 257 * wasn't configured by the BIOS (in which case we punt, since there's 258 * no real way we can know how the interrupt lines are mapped in the 259 * hardware). 260 * 261 * XXX 262 * Since IRQ 0 is only used by the clock, and we can't actually be sure 263 * that the BIOS did its job, we also recognize that as meaning that 264 * the BIOS has not configured the device. 265 */ 266 if (line == 255) { 267 aprint_error("pci_intr_map: no mapping for pin %c\n", 268 '@' + pin); 269 goto bad; 270 } 271 #ifdef EPIC_DEBUGIRQ 272 printf("line %d, pin %c", line, pin + '@'); 273 #endif 274 switch (brdtype) { 275 /* Sandpoint has 4 PCI slots in a weird order. 276 * From next to MPMC mezzanine card toward the board edge, 277 * 64bit slot PCI AD14 278 * 64bit slot PCI AD13 279 * 32bit slot PCI AD16 280 * 32bit slot PCI AD15 281 * Don't believe identifying labels printed on PCB and 282 * documents confusing as well since Moto names the slots 283 * as number 1 origin. 284 */ 285 case BRD_SANDPOINTX3: 286 /* 287 * Sandpoint X3 brd uses EPIC serial mode IRQ. 288 * - i8259 PIC interrupt to EPIC IRQ0. 289 * - WinBond IDE PCI C/D to EPIC IRQ8/9. 290 * - PCI AD13 pin A to EPIC IRQ2. 291 * - PCI AD14 pin A to EPIC IRQ3. 292 * - PCI AD15 pin A to EPIC IRQ4. 293 * - PCI AD16 pin A to EPIC IRQ5. 294 */ 295 if (line == 11 296 && pa->pa_function == 1 && pa->pa_bus == 0) { 297 /* X3 wires 83c553 pin C,D to EPIC IRQ8,9 */ 298 *ihp = 8; /* pin C only, indeed */ 299 break; 300 } 301 if (line < 13 || line > 16) { 302 aprint_error("pci_intr_map: bad interrupt line %d,%c\n", 303 line, pin + '@'); 304 goto bad; 305 } 306 line -= 13; /* B/C/D is not available */ 307 *ihp = 2 + line; 308 break; 309 case BRD_SANDPOINTX2: 310 /* 311 * Sandpoint X2 brd uses EPIC direct mode IRQ. 312 * - i8259 PIC interrupt EPIC IRQ2. 313 * - PCI AD13 pin A,B,C,D to EPIC IRQ0,1,2,3. 314 * - PCI AD14 pin A,B,C,D to EPIC IRQ1,2,3,0. 315 * - PCI AD15 pin A,B,C,D to EPIC IRQ2,3,0,1. 316 * - PCI AD16 pin A,B,C,D to EPIC IRQ3,0,1,2. 317 * - PCI AD12 is wired to PMPC device itself. 318 */ 319 if (line == 11 320 && pa->pa_function == 1 && pa->pa_bus == 0) { 321 /* 83C553 PCI IDE comes thru EPIC IRQ2 */ 322 *ihp = 2; 323 break; 324 } 325 if (line < 13 || line > 16) { 326 aprint_error("pci_intr_map: bad interrupt line %d,%c\n", 327 line, pin + '@'); 328 goto bad; 329 } 330 line -= 13; pin -= 1; 331 *ihp = (line + pin) & 03; 332 break; 333 case BRD_ENCOREPP1: 334 /* 335 * Ampro EnCorePP1 brd uses EPIC direct mode IRQ. 336 * PDF says VIA 686B SB i8259 interrupt goes through EPC IRQ0, 337 * while PCI pin A-D are tied with EPIC IRQ1-4. 338 * 339 * It mentions i82559 is at AD24, however, found at AD25 instead. 340 * Heuristics show that i82559 responds to EPIC 2 (!). Then we 341 * decided to return EPIC 2 here since i82559 is the only one PCI 342 * device ENCPP1 can have; 343 */ 344 if (pa->pa_device != 25) 345 goto bad; /* eeh !? */ 346 *ihp = 2; 347 break; 348 case BRD_KUROBOX: 349 /* map line 11,12,13,14 to EPIC IRQ 0,1,4,3 */ 350 *ihp = (line == 13) ? 4 : line - 11; 351 break; 352 case BRD_QNAPTS: 353 /* map line 13-16 to EPIC IRQ0-3 */ 354 *ihp = line - 13; 355 break; 356 case BRD_SYNOLOGY: 357 /* map line 12,13-15 to EPIC IRQ 4,0-2 */ 358 *ihp = (line == 12) ? 4 : line - 13; 359 break; 360 case BRD_DLINKDSM: 361 /* map line 13,14A,14B,14C,15,16 to EPIC IRQ 0,1,1,2,3,4 */ 362 *ihp = (line < 15) ? line - 13 : line - 12; 363 if (line == 14 && pin == 3) 364 *ihp += 1; /* USB pin C (EHCI) uses next IRQ */ 365 break; 366 case BRD_NH230NAS: 367 /* map line 13,14,15,16 to EPIC IRQ0,3,1,2 */ 368 *ihp = (line == 16) ? 2 : 369 (line == 15) ? 1 : 370 (line == 14) ? 3 : 0; 371 break; 372 case BRD_STORCENTER: 373 /* map line 13,14A,14B,14C,15 to EPIC IRQ 1,2,3,4,0 */ 374 *ihp = (line == 15) ? 0 : 375 (line == 13) ? 1 : 1 + pin; 376 break; 377 default: 378 /* simply map line 12-15 to EPIC IRQ0-3 */ 379 *ihp = line - 12; 380 #if defined(DIAGNOSTIC) || defined(DEBUG) 381 printf("pci_intr_map: line %d, pin %c for unknown board" 382 " mapped to irq %d\n", line, pin + '@', *ihp); 383 #endif 384 break; 385 } 386 #ifdef EPIC_DEBUGIRQ 387 printf(" = EPIC %d\n", *ihp); 388 #endif 389 return 0; 390 bad: 391 *ihp = -1; 392 return 1; 393 } 394 395 const char * 396 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf, 397 size_t len) 398 { 399 if (ih < 0 || ih >= OPENPIC_ICU) 400 panic("pci_intr_string: bogus handle 0x%x", ih); 401 402 snprintf(buf, len, "irq %d", ih + I8259_ICU); 403 return buf; 404 405 } 406 407 const struct evcnt * 408 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih) 409 { 410 411 /* XXX for now, no evcnt parent reported */ 412 return NULL; 413 } 414 415 int 416 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih, 417 int attr, uint64_t data) 418 { 419 420 switch (attr) { 421 case PCI_INTR_MPSAFE: 422 return 0; 423 default: 424 return ENODEV; 425 } 426 } 427 428 void * 429 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 430 int (*func)(void *), void *arg) 431 { 432 433 return pci_intr_establish_xname(pc, ih, level, func, arg, NULL); 434 } 435 436 void * 437 pci_intr_establish_xname(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 438 int (*func)(void *), void *arg, const char *xname) 439 { 440 int type; 441 442 if (brdtype == BRD_STORCENTER && ih == 1) { 443 /* 444 * XXX This is a workaround for the VT6410 IDE controller! 445 * Apparently its interrupt cannot be disabled and remains 446 * asserted during the whole device probing procedure, 447 * causing an interrupt storm. 448 * Using an edge-trigger fixes that and triggers the 449 * interrupt only once during probing. 450 */ 451 type = IST_EDGE; 452 } else 453 type = IST_LEVEL; 454 455 /* 456 * ih is the value assigned in pci_intr_map(), above. 457 * It's the EPIC IRQ #. 458 */ 459 return intr_establish_xname(ih + I8259_ICU, type, level, func, arg, 460 xname); 461 } 462 463 void 464 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 465 { 466 467 intr_disestablish(cookie); 468 } 469 470 #if defined(PCI_NETBSD_CONFIGURE) 471 void 472 pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, 473 int pin, int swiz, int *iline) 474 { 475 if (bus == 0) { 476 *iline = dev; 477 } else { 478 /* 479 * If we are not on bus zero, we're behind a bridge, so we 480 * swizzle. 481 * 482 * The documentation lies about this. In slot 3 (numbering 483 * from 0) aka device 16, INTD# becomes an interrupt for 484 * slot 2. INTC# becomes an interrupt for slot 1, etc. 485 * In slot 2 aka device 16, INTD# becomes an interrupt for 486 * slot 1, etc. 487 * 488 * Verified for INTD# on device 16, INTC# on device 16, 489 * INTD# on device 15, INTD# on device 13, and INTC# on 490 * device 14. I presume that the rest follow the same 491 * pattern. 492 * 493 * Slot 0 is device 13, and is the base for the rest. 494 */ 495 *iline = 13 + ((swiz + dev + 3) & 3); 496 } 497 } 498 #endif 499 500 int 501 pci_intx_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihpp) 502 { 503 pci_intr_handle_t *ihp; 504 505 ihp = kmem_alloc(sizeof(*ihp), KM_SLEEP); 506 if (ihp == NULL) 507 return ENOMEM; 508 509 if (pci_intr_map(pa, ihp)) { 510 kmem_free(ihp, sizeof(*ihp)); 511 return EINVAL; 512 } 513 514 *ihpp = ihp; 515 return 0; 516 } 517 518 /* experimental MSI support */ 519 int 520 pci_msi_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihps, 521 int *count) 522 { 523 524 return EOPNOTSUPP; 525 } 526 527 int 528 pci_msi_alloc_exact(const struct pci_attach_args *pa, pci_intr_handle_t **ihps, 529 int count) 530 { 531 532 return EOPNOTSUPP; 533 } 534 535 /* experimental MSI-X support */ 536 int 537 pci_msix_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihps, 538 int *count) 539 { 540 541 return EOPNOTSUPP; 542 } 543 544 int 545 pci_msix_alloc_exact(const struct pci_attach_args *pa, pci_intr_handle_t **ihps, 546 int count) 547 { 548 549 return EOPNOTSUPP; 550 } 551 552 int 553 pci_msix_alloc_map(const struct pci_attach_args *pa, pci_intr_handle_t **ihps, 554 u_int *table_indexes, int count) 555 { 556 557 return EOPNOTSUPP; 558 } 559
Indexes created Thu Oct 23 22:10:10 GMT 2025