entry.S revision 1.1
1 1.1 nisimura /* $NetBSD: entry.S,v 1.1 2011/01/23 01:05:30 nisimura Exp $ */ 2 1.1 nisimura 3 1.1 nisimura #include <powerpc/psl.h> 4 1.1 nisimura #include <powerpc/spr.h> 5 1.1 nisimura #include <powerpc/oea/spr.h> 6 1.1 nisimura #include <powerpc/oea/bat.h> 7 1.1 nisimura #include <powerpc/oea/hid.h> 8 1.1 nisimura 9 1.1 nisimura .text 10 1.1 nisimura .globl _start 11 1.1 nisimura _start: 12 1.1 nisimura mr 30,3 13 1.1 nisimura mr 31,4 14 1.1 nisimura mfspr 11,SPR_HID0 15 1.1 nisimura andi. 0,11,HID0_DCE 16 1.1 nisimura ori 11,11,HID0_ICE 17 1.1 nisimura ori 8,11,HID0_ICFI 18 1.1 nisimura bne 1f /* don't invalidate the D-cache */ 19 1.1 nisimura ori 8,8,HID0_DCFI /* unless it wasn't enabled */ 20 1.1 nisimura 1: 21 1.1 nisimura mfmsr 0 22 1.1 nisimura andi. 0,0,PSL_DR 23 1.1 nisimura beq 2f 24 1.1 nisimura lis 5, 0xfec00000@ha /* CONFIG_ADDR of PCI */ 25 1.1 nisimura lis 6, 0xfee00000@ha /* CONFIG_DATA of PCI */ 26 1.1 nisimura mfspr 3,SPR_DBAT0U 27 1.1 nisimura mfspr 4,SPR_DBAT0L 28 1.1 nisimura bl dbat_sanity_check 29 1.1 nisimura beq 3f 30 1.1 nisimura mfspr 3,SPR_DBAT1U 31 1.1 nisimura mfspr 4,SPR_DBAT1L 32 1.1 nisimura bl dbat_sanity_check 33 1.1 nisimura beq 3f 34 1.1 nisimura mfspr 3,SPR_DBAT2U 35 1.1 nisimura mfspr 4,SPR_DBAT2L 36 1.1 nisimura bl dbat_sanity_check 37 1.1 nisimura beq 3f 38 1.1 nisimura mfspr 3,SPR_DBAT3U 39 1.1 nisimura mfspr 4,SPR_DBAT3L 40 1.1 nisimura bl dbat_sanity_check 41 1.1 nisimura beq 3f 42 1.1 nisimura 43 1.1 nisimura 2: /* Disable D-cache */ 44 1.1 nisimura li 0,HID0_DCE 45 1.1 nisimura andc 11,11,0 46 1.1 nisimura b 4f 47 1.1 nisimura 48 1.1 nisimura 3: /* Enable D-cache */ 49 1.1 nisimura ori 11,11,HID0_DCE 50 1.1 nisimura 51 1.1 nisimura 4: 52 1.1 nisimura lis 1,BAT123@ha 53 1.1 nisimura addi 1,1,BAT123@l 54 1.1 nisimura lwz 3,0(1) 55 1.1 nisimura lwz 4,4(1) 56 1.1 nisimura mtdbatl 1,3 57 1.1 nisimura mtdbatu 1,4 58 1.1 nisimura lwz 3,8(1) 59 1.1 nisimura lwz 4,12(1) 60 1.1 nisimura mtdbatl 2,3 61 1.1 nisimura mtdbatu 2,4 62 1.1 nisimura lwz 3,16(1) 63 1.1 nisimura lwz 4,20(1) 64 1.1 nisimura mtdbatl 3,3 65 1.1 nisimura mtdbatu 3,4 66 1.1 nisimura 67 1.1 nisimura sync 68 1.1 nisimura mtspr SPR_HID0,8 /* enable and invalidate caches */ 69 1.1 nisimura sync 70 1.1 nisimura mtspr SPR_HID0,11 /* enable caches */ 71 1.1 nisimura sync 72 1.1 nisimura isync 73 1.1 nisimura 74 1.1 nisimura /* make sure .bss gets zeroed. */ 75 1.1 nisimura li 0,0 76 1.1 nisimura lis 8,edata@ha 77 1.1 nisimura addi 8,8,edata@l 78 1.1 nisimura lis 9,end@ha 79 1.1 nisimura addi 9,9,end@l 80 1.1 nisimura 5: cmpw 0,8,9 /* edata & end are >= word aligned */ 81 1.1 nisimura bge 6f 82 1.1 nisimura stw 0,0(8) 83 1.1 nisimura addi 8,8,4 84 1.1 nisimura b 5b 85 1.1 nisimura 86 1.1 nisimura 6: 87 1.1 nisimura /* prepare stack at +1MB from _start. */ 88 1.1 nisimura lis 1,_start@h 89 1.1 nisimura ori 1,1,_start@l 90 1.1 nisimura addis 1,1,0x10 91 1.1 nisimura addi 1,1,-4 92 1.1 nisimura 93 1.1 nisimura bl brdsetup 94 1.1 nisimura mr 3,30 95 1.1 nisimura mr 4,31 96 1.1 nisimura bl main 97 1.1 nisimura 98 1.1 nisimura hang: b hang 99 1.1 nisimura /* NOTREACHED */ 100 1.1 nisimura 101 1.1 nisimura dbat_sanity_check: 102 1.1 nisimura andi. 0,3,BAT_Vs 103 1.1 nisimura beq 2f 104 1.1 nisimura andi. 0,4,BAT_I|BAT_PP_RW 105 1.1 nisimura cmpwi 0,0,BAT_I|BAT_PP_RW 106 1.1 nisimura bnelr 107 1.1 nisimura rlwinm 0,3,15,4,14 108 1.1 nisimura andis. 3,3,0xfffe0000@ha /* BAT_EPI */ 109 1.1 nisimura andis. 4,4,BAT_RPN@ha 110 1.1 nisimura cmplw 0,3,4 111 1.1 nisimura bnelr 112 1.1 nisimura add 4,4,0 113 1.1 nisimura oris 4,4,0x0001ffff@ha 114 1.1 nisimura ori 4,4,0x0001ffff@l 115 1.1 nisimura cmplw 0,3,5 116 1.1 nisimura bgt 1f 117 1.1 nisimura cmplw 0,5,4 118 1.1 nisimura bgt 1f 119 1.1 nisimura li 5,0 120 1.1 nisimura 1: cmplw 0,3,6 121 1.1 nisimura bgt 2f 122 1.1 nisimura cmplw 0,6,4 123 1.1 nisimura bgt 2f 124 1.1 nisimura li 6,0 125 1.1 nisimura 2: cmplw 0,5,6 126 1.1 nisimura blr 127 1.1 nisimura 128 1.1 nisimura /* 129 1.1 nisimura * run(startsym, endsym, howto, bootinfo, entry) 130 1.1 nisimura */ 131 1.1 nisimura .globl run 132 1.1 nisimura run: 133 1.1 nisimura mtctr 7 /* hat trick jump to entry point */ 134 1.1 nisimura bctr 135 1.1 nisimura 136 1.1 nisimura /* 137 1.1 nisimura * reverse endian access to mimic outw/outl/inw/inl 138 1.1 nisimura */ 139 1.1 nisimura .globl out16rb 140 1.1 nisimura .globl iohtole16 141 1.1 nisimura out16rb: 142 1.1 nisimura iohtole16: 143 1.1 nisimura sthbrx 4,0,3 144 1.1 nisimura eieio 145 1.1 nisimura blr 146 1.1 nisimura 147 1.1 nisimura .globl out32rb 148 1.1 nisimura .globl iohtole32 149 1.1 nisimura out32rb: 150 1.1 nisimura iohtole32: 151 1.1 nisimura stwbrx 4,0,3 152 1.1 nisimura eieio 153 1.1 nisimura blr 154 1.1 nisimura 155 1.1 nisimura .global in16rb 156 1.1 nisimura .global iole16toh 157 1.1 nisimura in16rb: 158 1.1 nisimura iole16toh: 159 1.1 nisimura lhbrx 3,0,3 160 1.1 nisimura eieio 161 1.1 nisimura blr 162 1.1 nisimura 163 1.1 nisimura .global in32rb 164 1.1 nisimura .global iole32toh 165 1.1 nisimura in32rb: 166 1.1 nisimura iole32toh: 167 1.1 nisimura lwbrx 3,0,3 168 1.1 nisimura eieio 169 1.1 nisimura blr 170 1.1 nisimura 171 1.1 nisimura .data 172 1.1 nisimura #define xBATL(pa, wimg, pp) \ 173 1.1 nisimura ((pa) | (wimg) | (pp)) 174 1.1 nisimura #define xBATU(va, len, v) \ 175 1.1 nisimura ((va) | ((len) & BAT_BL) | ((v) & BAT_V)) 176 1.1 nisimura BAT123: 177 1.1 nisimura .long xBATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW) 178 1.1 nisimura .long xBATU(0x80000000, BAT_BL_256M, BAT_Vs) 179 1.1 nisimura .long xBATL(0xfc000000, BAT_I|BAT_G, BAT_PP_RW) 180 1.1 nisimura .long xBATU(0xfc000000, BAT_BL_64M, BAT_Vs) 181 1.1 nisimura .long 0 182 1.1 nisimura .long 0 183
Indexes created Wed Oct 01 18:09:54 GMT 2025