entry.S revision 1.3
1 1.3 phx /* $NetBSD: entry.S,v 1.3 2011/03/13 15:23:43 phx Exp $ */ 2 1.1 nisimura 3 1.1 nisimura #include <powerpc/psl.h> 4 1.1 nisimura #include <powerpc/spr.h> 5 1.1 nisimura #include <powerpc/oea/spr.h> 6 1.1 nisimura #include <powerpc/oea/bat.h> 7 1.1 nisimura #include <powerpc/oea/hid.h> 8 1.1 nisimura 9 1.1 nisimura .text 10 1.1 nisimura .globl _start 11 1.1 nisimura _start: 12 1.2 phx /* 13 1.2 phx * Save possible argc and argv values from the firmware, usually 14 1.2 phx * passed in r3 and r4. 15 1.2 phx * When started with "bootm", as a Linux kernel module, r6 and r7 16 1.2 phx * point to the start and end address of the bootargs. 17 1.2 phx */ 18 1.1 nisimura mr 30,3 19 1.1 nisimura mr 31,4 20 1.2 phx mr 28,6 21 1.2 phx mr 29,7 22 1.2 phx 23 1.2 phx /* 24 1.2 phx * U-Boot/PPCBoot forgets to flush the cache when using the "bootm" 25 1.2 phx * command, so we have to do that now. 26 1.2 phx */ 27 1.3 phx lis 11,_start@ha 28 1.3 phx addi 11,11,_start@l 29 1.3 phx andi. 11,11,~31@l 30 1.3 phx lis 12,(_edata+31)@ha 31 1.3 phx addi 12,12,(_edata+31)@l 32 1.3 phx bl syncicache 33 1.2 phx 34 1.1 nisimura mfspr 11,SPR_HID0 35 1.1 nisimura andi. 0,11,HID0_DCE 36 1.1 nisimura ori 11,11,HID0_ICE 37 1.1 nisimura ori 8,11,HID0_ICFI 38 1.1 nisimura bne 1f /* don't invalidate the D-cache */ 39 1.1 nisimura ori 8,8,HID0_DCFI /* unless it wasn't enabled */ 40 1.1 nisimura 1: 41 1.1 nisimura mfmsr 0 42 1.1 nisimura andi. 0,0,PSL_DR 43 1.1 nisimura beq 2f 44 1.1 nisimura lis 5, 0xfec00000@ha /* CONFIG_ADDR of PCI */ 45 1.1 nisimura lis 6, 0xfee00000@ha /* CONFIG_DATA of PCI */ 46 1.1 nisimura mfspr 3,SPR_DBAT0U 47 1.1 nisimura mfspr 4,SPR_DBAT0L 48 1.1 nisimura bl dbat_sanity_check 49 1.1 nisimura beq 3f 50 1.1 nisimura mfspr 3,SPR_DBAT1U 51 1.1 nisimura mfspr 4,SPR_DBAT1L 52 1.1 nisimura bl dbat_sanity_check 53 1.1 nisimura beq 3f 54 1.1 nisimura mfspr 3,SPR_DBAT2U 55 1.1 nisimura mfspr 4,SPR_DBAT2L 56 1.1 nisimura bl dbat_sanity_check 57 1.1 nisimura beq 3f 58 1.1 nisimura mfspr 3,SPR_DBAT3U 59 1.1 nisimura mfspr 4,SPR_DBAT3L 60 1.1 nisimura bl dbat_sanity_check 61 1.1 nisimura beq 3f 62 1.1 nisimura 63 1.1 nisimura 2: /* Disable D-cache */ 64 1.1 nisimura li 0,HID0_DCE 65 1.1 nisimura andc 11,11,0 66 1.1 nisimura b 4f 67 1.1 nisimura 68 1.1 nisimura 3: /* Enable D-cache */ 69 1.1 nisimura ori 11,11,HID0_DCE 70 1.1 nisimura 71 1.1 nisimura 4: 72 1.1 nisimura lis 1,BAT123@ha 73 1.1 nisimura addi 1,1,BAT123@l 74 1.1 nisimura lwz 3,0(1) 75 1.1 nisimura lwz 4,4(1) 76 1.1 nisimura mtdbatl 1,3 77 1.1 nisimura mtdbatu 1,4 78 1.1 nisimura lwz 3,8(1) 79 1.1 nisimura lwz 4,12(1) 80 1.1 nisimura mtdbatl 2,3 81 1.1 nisimura mtdbatu 2,4 82 1.1 nisimura lwz 3,16(1) 83 1.1 nisimura lwz 4,20(1) 84 1.1 nisimura mtdbatl 3,3 85 1.1 nisimura mtdbatu 3,4 86 1.1 nisimura 87 1.1 nisimura sync 88 1.1 nisimura mtspr SPR_HID0,8 /* enable and invalidate caches */ 89 1.1 nisimura sync 90 1.1 nisimura mtspr SPR_HID0,11 /* enable caches */ 91 1.1 nisimura sync 92 1.1 nisimura isync 93 1.1 nisimura 94 1.1 nisimura /* make sure .bss gets zeroed. */ 95 1.1 nisimura li 0,0 96 1.1 nisimura lis 8,edata@ha 97 1.1 nisimura addi 8,8,edata@l 98 1.1 nisimura lis 9,end@ha 99 1.1 nisimura addi 9,9,end@l 100 1.1 nisimura 5: cmpw 0,8,9 /* edata & end are >= word aligned */ 101 1.1 nisimura bge 6f 102 1.1 nisimura stw 0,0(8) 103 1.1 nisimura addi 8,8,4 104 1.1 nisimura b 5b 105 1.1 nisimura 106 1.1 nisimura 6: 107 1.1 nisimura /* prepare stack at +1MB from _start. */ 108 1.1 nisimura lis 1,_start@h 109 1.1 nisimura ori 1,1,_start@l 110 1.1 nisimura addis 1,1,0x10 111 1.1 nisimura addi 1,1,-4 112 1.1 nisimura 113 1.1 nisimura bl brdsetup 114 1.1 nisimura mr 3,30 115 1.1 nisimura mr 4,31 116 1.2 phx mr 5,28 117 1.2 phx mr 6,29 118 1.1 nisimura bl main 119 1.1 nisimura 120 1.1 nisimura hang: b hang 121 1.1 nisimura /* NOTREACHED */ 122 1.1 nisimura 123 1.1 nisimura dbat_sanity_check: 124 1.1 nisimura andi. 0,3,BAT_Vs 125 1.1 nisimura beq 2f 126 1.1 nisimura andi. 0,4,BAT_I|BAT_PP_RW 127 1.1 nisimura cmpwi 0,0,BAT_I|BAT_PP_RW 128 1.1 nisimura bnelr 129 1.1 nisimura rlwinm 0,3,15,4,14 130 1.1 nisimura andis. 3,3,0xfffe0000@ha /* BAT_EPI */ 131 1.1 nisimura andis. 4,4,BAT_RPN@ha 132 1.1 nisimura cmplw 0,3,4 133 1.1 nisimura bnelr 134 1.1 nisimura add 4,4,0 135 1.1 nisimura oris 4,4,0x0001ffff@ha 136 1.1 nisimura ori 4,4,0x0001ffff@l 137 1.1 nisimura cmplw 0,3,5 138 1.1 nisimura bgt 1f 139 1.1 nisimura cmplw 0,5,4 140 1.1 nisimura bgt 1f 141 1.1 nisimura li 5,0 142 1.1 nisimura 1: cmplw 0,3,6 143 1.1 nisimura bgt 2f 144 1.1 nisimura cmplw 0,6,4 145 1.1 nisimura bgt 2f 146 1.1 nisimura li 6,0 147 1.1 nisimura 2: cmplw 0,5,6 148 1.1 nisimura blr 149 1.1 nisimura 150 1.1 nisimura /* 151 1.1 nisimura * run(startsym, endsym, howto, bootinfo, entry) 152 1.1 nisimura */ 153 1.1 nisimura .globl run 154 1.1 nisimura run: 155 1.1 nisimura mtctr 7 /* hat trick jump to entry point */ 156 1.1 nisimura bctr 157 1.1 nisimura 158 1.1 nisimura /* 159 1.3 phx * newaltboot(argc, argv, altboot_base, altboot_len) 160 1.3 phx * To be executed in a safe memory region. Copies the new altboot from 161 1.3 phx * altboot_base to 0x1000000 and starts it there. 162 1.3 phx */ 163 1.3 phx .globl newaltboot 164 1.3 phx newaltboot: 165 1.3 phx lis 7,0x1000000@h 166 1.3 phx mr 11,7 167 1.3 phx subi 7,7,4 168 1.3 phx subi 5,5,4 169 1.3 phx add 12,11,6 170 1.3 phx addi 6,6,3 171 1.3 phx srawi 6,6,2 172 1.3 phx mtctr 6 173 1.3 phx 1: lwzu 8,4(5) 174 1.3 phx stwu 8,4(7) 175 1.3 phx bdnz+ 1b 176 1.3 phx mtctr 11 177 1.3 phx addi 12,12,31 178 1.3 phx bl syncicache 179 1.3 phx bctr 180 1.3 phx syncicache: 181 1.3 phx /* r11=start, r12=end, r10=scratch */ 182 1.3 phx mr 10,11 183 1.3 phx 2: dcbst 0,10 184 1.3 phx addi 10,10,32 185 1.3 phx cmplw 10,12 186 1.3 phx ble 2b 187 1.3 phx sync 188 1.3 phx 3: icbi 0,11 189 1.3 phx addi 11,11,32 190 1.3 phx cmplw 11,12 191 1.3 phx ble 3b 192 1.3 phx sync 193 1.3 phx isync 194 1.3 phx blr 195 1.3 phx .globl newaltboot_end 196 1.3 phx newaltboot_end: 197 1.3 phx 198 1.3 phx /* 199 1.1 nisimura * reverse endian access to mimic outw/outl/inw/inl 200 1.1 nisimura */ 201 1.1 nisimura .globl out16rb 202 1.1 nisimura .globl iohtole16 203 1.1 nisimura out16rb: 204 1.1 nisimura iohtole16: 205 1.1 nisimura sthbrx 4,0,3 206 1.1 nisimura eieio 207 1.1 nisimura blr 208 1.1 nisimura 209 1.1 nisimura .globl out32rb 210 1.1 nisimura .globl iohtole32 211 1.1 nisimura out32rb: 212 1.1 nisimura iohtole32: 213 1.1 nisimura stwbrx 4,0,3 214 1.1 nisimura eieio 215 1.1 nisimura blr 216 1.1 nisimura 217 1.1 nisimura .global in16rb 218 1.1 nisimura .global iole16toh 219 1.1 nisimura in16rb: 220 1.1 nisimura iole16toh: 221 1.1 nisimura lhbrx 3,0,3 222 1.1 nisimura eieio 223 1.1 nisimura blr 224 1.1 nisimura 225 1.1 nisimura .global in32rb 226 1.1 nisimura .global iole32toh 227 1.1 nisimura in32rb: 228 1.1 nisimura iole32toh: 229 1.1 nisimura lwbrx 3,0,3 230 1.1 nisimura eieio 231 1.1 nisimura blr 232 1.1 nisimura 233 1.1 nisimura .data 234 1.1 nisimura #define xBATL(pa, wimg, pp) \ 235 1.1 nisimura ((pa) | (wimg) | (pp)) 236 1.1 nisimura #define xBATU(va, len, v) \ 237 1.1 nisimura ((va) | ((len) & BAT_BL) | ((v) & BAT_V)) 238 1.1 nisimura BAT123: 239 1.1 nisimura .long xBATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW) 240 1.1 nisimura .long xBATU(0x80000000, BAT_BL_256M, BAT_Vs) 241 1.1 nisimura .long xBATL(0xfc000000, BAT_I|BAT_G, BAT_PP_RW) 242 1.1 nisimura .long xBATU(0xfc000000, BAT_BL_64M, BAT_Vs) 243 1.1 nisimura .long 0 244 1.1 nisimura .long 0 245
Indexes created Wed Oct 01 19:09:53 GMT 2025