pcn.c revision 1.1.4.2
1 /* $NetBSD: pcn.c,v 1.1.4.2 2011/03/06 15:07:56 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 34 #include <netinet/in.h> 35 #include <netinet/in_systm.h> 36 37 #include <lib/libsa/stand.h> 38 #include <lib/libsa/net.h> 39 40 #include "globals.h" 41 42 /* 43 * - reverse endian access every CSR. 44 * - no vtophys() translation, vaddr_t == paddr_t. 45 * - PIPT writeback cache aware. 46 */ 47 #define CSR_READ_4(l, r) in32rb((l)->csr+(r)) 48 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) 49 #define CSR_READ_2(l, r) in16rb((l)->csr+(r)) 50 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v)) 51 #define VTOPHYS(va) (uint32_t)(va) 52 #define DEVTOV(pa) (uint32_t)(pa) 53 #define wbinv(adr, siz) _wbinv(VTOPHYS(adr), (uint32_t)(siz)) 54 #define inv(adr, siz) _inv(VTOPHYS(adr), (uint32_t)(siz)) 55 #define DELAY(n) delay(n) 56 #define ALLOC(T,A) (T *)allocaligned(sizeof(T),(A)) 57 58 struct desc { 59 uint32_t xd0, xd1, xd2; 60 uint32_t hole; 61 }; 62 #define T1_OWN (1U << 31) /* 1: empty for HW to load anew */ 63 #define T1_STP (1U << 25) /* first frame segment */ 64 #define T1_ENP (1U << 24) /* last frame segment */ 65 #define T1_ONES 0xf000 /* filler */ 66 #define T1_FLMASK 0x0fff /* Tx segment length */ 67 #define R1_OWN (1U << 31) /* 1: loaded for HW to send */ 68 #define R1_ERR (1U << 30) /* Rx error summary */ 69 #define R1_ONES 0xf000 /* filler */ 70 #define R1_FLMASK 0x0fff /* Rx frame length */ 71 72 #define PCN_RDP 0x10 73 #define PCN_RAP 0x12 74 #define PCN_16RESET 0x14 75 #define PCN_32RESET 0x18 76 #define PCN_BDP 0x1c 77 #define PCN_CSR0 0x00 78 #define C0_IDON (1U << 8) /* initblk done indication */ 79 #define C0_TXON (1U << 5) 80 #define C0_RXON (1U << 4) 81 #define C0_TDMD (1U << 3) /* immediate Tx descriptor poll */ 82 #define C0_STOP (1U << 2) /* reset with abrupt abort */ 83 #define C0_STRT (1U << 1) /* activate whole Tx/Rx DMA */ 84 #define C0_INIT (1U << 0) /* instruct to process initblk */ 85 #define PCN_CSR1 0x01 86 #define PCN_CSR2 0x02 87 #define PCN_CSR3 0x03 88 #define C3_MISSM (1U << 12) 89 #define C3_IDONM (1U << 8) 90 #define C3_DXSUFLO (1U << 6) 91 #define PCN_CSR4 0x04 92 #define C4_DMAPLUS (1U << 14) 93 #define C4_TXDPOLL (1U << 12) /* _disable_ Tx descriptor polling */ 94 #define C4_APAD_XMT (1U << 11) 95 #define C4_MFCOM (1U << 8) 96 #define C4_RCVCCOM (1U << 4) 97 #define C4_TXSTRTM (1U << 6) 98 #define PCN_CSR5 0x05 99 #define PCN_CSR12 0x0c 100 #define PCN_CSR13 0x0d 101 #define PCN_CSR14 0x0e 102 #define PCN_CSR58 0x4a /* mapped to BCR20 */ 103 #define PCN_BCR20 0x14 /* "software style" */ 104 #define PCN_BCR33 0x21 105 #define PCN_BCR34 0x22 106 107 struct pcninit { 108 uint32_t init_mode; 109 uint32_t init_padr[2]; 110 uint16_t init_ladrf[4]; 111 uint32_t init_rdra; 112 uint32_t init_tdra; 113 uint32_t pad; 114 }; 115 116 #define FRAMESIZE 1536 117 118 struct local { 119 struct desc txd[2]; 120 struct desc rxd[2]; 121 uint8_t rxstore[2][FRAMESIZE]; 122 unsigned csr, tx, rx; 123 unsigned phy, bmsr, anlpar; 124 }; 125 126 unsigned pcn_mii_read(struct local *, int, int); 127 void pcn_mii_write(struct local *, int, int, int); 128 static unsigned pcn_csr_read(struct local *, int); 129 static void pcn_csr_write(struct local *, int, int); 130 static unsigned pcn_bcr_read(struct local *, int); 131 static void pcn_bcr_write(struct local *, int, int); 132 static void mii_initphy(struct local *l); 133 134 int 135 pcn_match(unsigned tag, void *data) 136 { 137 unsigned v; 138 139 v = pcicfgread(tag, PCI_ID_REG); 140 return (v == PCI_DEVICE(0x1022, 0x2000)); 141 } 142 143 void * 144 pcn_init(unsigned tag, void *data) 145 { 146 unsigned val, fdx, loop; 147 struct local *l; 148 struct desc *txd, *rxd; 149 uint8_t *en; 150 struct pcninit initblock, *ib; 151 152 l = ALLOC(struct local, 32); /* desc alignment */ 153 memset(l, 0, sizeof(struct local)); 154 l->csr = DEVTOV(pcicfgread(tag, 0x14)); /* use mem space */ 155 156 (void)CSR_READ_2(l, PCN_16RESET); 157 (void)CSR_READ_4(l, PCN_32RESET); 158 DELAY(1000); /* 1 milli second */ 159 /* go 32bit RW mode */ 160 CSR_WRITE_4(l, PCN_RDP, 0); 161 /* use 32bit software structure design "2" */ 162 pcn_bcr_write(l, PCN_BCR20, 2); 163 164 mii_initphy(l); 165 166 en = data; 167 val = pcn_csr_read(l, PCN_CSR12); en[0] = val; en[1] = (val >> 8); 168 val = pcn_csr_read(l, PCN_CSR13); en[2] = val; en[3] = (val >> 8); 169 val = pcn_csr_read(l, PCN_CSR14); en[4] = val; en[5] = (val >> 8); 170 #if 1 171 printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", 172 en[0], en[1], en[2], en[3], en[4], en[5]); 173 #endif 174 /* speed and duplexity are found in MII ANR24 */ 175 val = pcn_mii_read(l, l->phy, 24); 176 fdx = !!(val & (1U << 2)); 177 printf("%s", (val & (1U << 0)) ? "100Mbps" : "10Mbps"); 178 if (fdx) 179 printf("-FDX"); 180 printf("\n"); 181 182 txd = &l->txd[0]; 183 rxd = &l->rxd[0]; 184 rxd[0].xd0 = htole32(VTOPHYS(l->rxstore[0])); 185 rxd[0].xd1 = htole32(R1_OWN | R1_ONES | FRAMESIZE); 186 rxd[1].xd0 = htole32(VTOPHYS(l->rxstore[1])); 187 rxd[1].xd1 = htole32(R1_OWN | R1_ONES | FRAMESIZE); 188 l->tx = l->rx = 0; 189 190 ib = &initblock; 191 ib->init_mode = htole32((0 << 28) | (1 << 20) | 0); 192 ib->init_padr[0] = 193 htole32(en[0] | (en[1] << 8) | (en[2] << 16) | (en[3] << 24)); 194 ib->init_padr[1] = 195 htole32(en[4] | (en[5] << 8)); 196 ib->init_rdra = htole32(VTOPHYS(rxd)); 197 ib->init_tdra = htole32(VTOPHYS(txd)); 198 199 pcn_csr_write(l, PCN_CSR3, C3_MISSM|C3_IDONM|C3_DXSUFLO); 200 pcn_csr_write(l, PCN_CSR4, C4_DMAPLUS|C4_APAD_XMT| 201 C4_MFCOM|C4_RCVCCOM|C4_TXSTRTM); 202 pcn_csr_write(l, PCN_CSR5, 0); 203 204 wbinv(&initblock, sizeof(initblock)); 205 pcn_csr_write(l, PCN_CSR1, VTOPHYS(&initblock) & 0xffff); 206 pcn_csr_write(l, PCN_CSR2, (VTOPHYS(&initblock) >> 16) & 0xffff); 207 pcn_csr_write(l, PCN_CSR0, C0_INIT); 208 loop = 10000; 209 do { 210 DELAY(10); 211 } while (--loop > 0 && !(pcn_csr_read(l, PCN_CSR0) & C0_IDON)); 212 if (loop == 0) 213 printf("pcn: timeout processing init block\n"); 214 215 pcn_csr_write(l, PCN_CSR0, C0_STRT); 216 217 return l; 218 } 219 220 int 221 pcn_send(void *dev, char *buf, unsigned len) 222 { 223 struct local *l = dev; 224 volatile struct desc *txd; 225 unsigned loop; 226 int tlen; 227 228 wbinv(buf, len); 229 txd = &l->txd[l->tx]; 230 tlen = (-len) & T1_FLMASK; /* two's complement */ 231 txd->xd0 = htole32(VTOPHYS(buf)); 232 txd->xd1 = htole32(T1_OWN | T1_STP | T1_ENP | T1_ONES | tlen); 233 wbinv(txd, sizeof(struct desc)); 234 /* pcn_csr_write(l, PCN_CSR0, C0_TDMD); */ 235 loop = 100; 236 do { 237 if ((le32toh(txd->xd1) & T1_OWN) == 0) 238 goto done; 239 DELAY(10); 240 inv(txd, sizeof(struct desc)); 241 } while (--loop > 0); 242 printf("xmit failed\n"); 243 return -1; 244 done: 245 l->tx ^= 1; 246 return len; 247 } 248 249 int 250 pcn_recv(void *dev, char *buf, unsigned maxlen, unsigned timo) 251 { 252 struct local *l = dev; 253 volatile struct desc *rxd; 254 unsigned bound, rxstat, len; 255 uint8_t *ptr; 256 257 bound = 1000 * timo; 258 printf("recving with %u sec. timeout\n", timo); 259 again: 260 rxd = &l->rxd[l->rx]; 261 do { 262 inv(rxd, sizeof(struct desc)); 263 rxstat = le32toh(rxd->xd1); 264 if ((rxstat & R1_OWN) == 0) 265 goto gotone; 266 DELAY(1000); /* 1 milli second */ 267 } while (--bound > 0); 268 errno = 0; 269 return -1; 270 gotone: 271 if (rxstat & R1_ERR) { 272 rxd->xd1 |= htole32(R1_OWN); 273 rxd->xd2 = 0; 274 wbinv(rxd, sizeof(struct desc)); 275 l->rx ^= 1; 276 goto again; 277 } 278 /* good frame */ 279 len = (rxstat & R1_FLMASK) - 4 /* HASFCS */; 280 if (len > maxlen) 281 len = maxlen; 282 ptr = l->rxstore[l->rx]; 283 inv(ptr, len); 284 memcpy(buf, ptr, len); 285 rxd->xd1 |= htole32(R1_OWN); 286 rxd->xd2 = 0; 287 wbinv(rxd, sizeof(struct desc)); 288 l->rx ^= 1; 289 return len; 290 } 291 292 #define MREG(v) ((v)<< 0) 293 #define MPHY(v) ((v)<< 5) 294 #define MIIMD 0xffff 295 296 unsigned 297 pcn_mii_read(struct local *l, int phy, int reg) 298 { 299 pcn_bcr_write(l, PCN_BCR33, MREG(reg) | MPHY(phy)); 300 return (pcn_bcr_read(l, PCN_BCR34) & MIIMD); 301 } 302 303 void 304 pcn_mii_write(struct local *l, int phy, int reg, int val) 305 { 306 pcn_bcr_write(l, PCN_BCR33, MREG(reg) | MPHY(phy)); 307 pcn_bcr_write(l, PCN_BCR34, val); 308 } 309 310 static unsigned 311 pcn_csr_read(struct local *l, int r) 312 { 313 CSR_WRITE_4(l, PCN_RAP, r); 314 return CSR_READ_4(l, PCN_RDP); 315 } 316 317 static void 318 pcn_csr_write(struct local *l, int r, int v) 319 { 320 CSR_WRITE_4(l, PCN_RAP, r); 321 CSR_WRITE_4(l, PCN_RDP, v); 322 } 323 324 static unsigned 325 pcn_bcr_read(struct local *l, int r) 326 { 327 CSR_WRITE_4(l, PCN_RAP, r); 328 return CSR_READ_4(l, PCN_BDP); 329 } 330 331 static void 332 pcn_bcr_write(struct local *l, int r, int v) 333 { 334 CSR_WRITE_4(l, PCN_RAP, r); 335 CSR_WRITE_4(l, PCN_BDP, v); 336 } 337 338 #define MII_BMCR 0x00 /* Basic mode control register (rw) */ 339 #define BMCR_RESET 0x8000 /* reset */ 340 #define BMCR_AUTOEN 0x1000 /* autonegotiation enable */ 341 #define BMCR_ISO 0x0400 /* isolate */ 342 #define BMCR_STARTNEG 0x0200 /* restart autonegotiation */ 343 #define MII_BMSR 0x01 /* Basic mode status register (ro) */ 344 345 static void 346 mii_initphy(struct local *l) 347 { 348 int phy, ctl, sts, bound; 349 350 for (phy = 0; phy < 32; phy++) { 351 ctl = pcn_mii_read(l, phy, MII_BMCR); 352 sts = pcn_mii_read(l, phy, MII_BMSR); 353 if (ctl != 0xffff && sts != 0xffff) 354 goto found; 355 } 356 printf("MII: no PHY found\n"); 357 return; 358 found: 359 ctl = pcn_mii_read(l, phy, MII_BMCR); 360 pcn_mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET); 361 bound = 100; 362 do { 363 DELAY(10); 364 ctl = pcn_mii_read(l, phy, MII_BMCR); 365 if (ctl == 0xffff) { 366 printf("MII: PHY %d has died after reset\n", phy); 367 return; 368 } 369 } while (bound-- > 0 && (ctl & BMCR_RESET)); 370 if (bound == 0) { 371 printf("PHY %d reset failed\n", phy); 372 } 373 ctl &= ~BMCR_ISO; 374 pcn_mii_write(l, phy, MII_BMCR, ctl); 375 sts = pcn_mii_read(l, phy, MII_BMSR) | 376 pcn_mii_read(l, phy, MII_BMSR); /* read twice */ 377 l->phy = phy; 378 l->bmsr = sts; 379 } 380 381 #if 0 382 static void 383 mii_dealan(struct local *, unsigned timo) 384 { 385 unsigned anar, bound; 386 387 anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA; 388 pcn_mii_write(l, l->phy, MII_ANAR, anar); 389 pcn_mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 390 l->anlpar = 0; 391 bound = getsecs() + timo; 392 do { 393 l->bmsr = pcn_mii_read(l, l->phy, MII_BMSR) | 394 pcn_mii_read(l, l->phy, MII_BMSR); /* read twice */ 395 if ((l->bmsr & BMSR_LINK) && (l->bmsr & BMSR_ACOMP)) { 396 l->anlpar = pcn_mii_read(l, l->phy, MII_ANLPAR); 397 break; 398 } 399 DELAY(10 * 1000); 400 } while (getsecs() < bound); 401 return; 402 } 403 #endif 404
Indexes created Tue Oct 14 15:09:51 GMT 2025