rge.c revision 1.3
1 /* $NetBSD: rge.c,v 1.3 2011/03/27 19:09:43 phx Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 34 #include <netinet/in.h> 35 #include <netinet/in_systm.h> 36 37 #include <lib/libsa/stand.h> 38 #include <lib/libsa/net.h> 39 40 #include "globals.h" 41 42 /* 43 * - reverse endian access every CSR. 44 * - no vtophys() translation, vaddr_t == paddr_t. 45 * - PIPT writeback cache aware. 46 */ 47 #define CSR_WRITE_1(l, r, v) *(volatile uint8_t *)((l)->csr+(r)) = (v) 48 #define CSR_READ_1(l, r) *(volatile uint8_t *)((l)->csr+(r)) 49 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v)) 50 #define CSR_READ_2(l, r) in16rb((l)->csr+(r)) 51 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) 52 #define CSR_READ_4(l, r) in32rb((l)->csr+(r)) 53 #define VTOPHYS(va) (uint32_t)(va) 54 #define DEVTOV(pa) (uint32_t)(pa) 55 #define wbinv(adr, siz) _wbinv(VTOPHYS(adr), (uint32_t)(siz)) 56 #define inv(adr, siz) _inv(VTOPHYS(adr), (uint32_t)(siz)) 57 #define DELAY(n) delay(n) 58 #define ALLOC(T,A) (T *)allocaligned(sizeof(T),(A)) 59 60 struct desc { 61 uint32_t xd0, xd1, xd2, xd3; 62 }; 63 #define T0_OWN 0x80000000 /* loaded for HW to send */ 64 #define T0_EOR 0x40000000 /* end of ring */ 65 #define T0_FS 0x20000000 /* first descriptor */ 66 #define T0_LS 0x10000000 /* last descriptor */ 67 #define T0_FRMASK 0x0000ffff 68 69 #define R0_OWN 0x80000000 /* empty for HW to load anew */ 70 #define R0_EOR 0x40000000 /* end mark to form a ring */ 71 #define R0_BUFLEN 0x00003ff8 /* max frag. size to receive */ 72 #define R0_FS 0x20000000 /* start of frame */ 73 #define R0_LS 0x10000000 /* end of frame */ 74 #define R0_RES 0x00200000 /* Rx error summary */ 75 #define R0_RUNT 0x00100000 /* runt frame received */ 76 #define R0_CRC 0x00080000 /* CRC error found */ 77 #define R0_FRMASK 0x00003fff /* 13:0 frame length */ 78 79 #define RGE_IDR0 0x00 /* MAC address [0] */ 80 #define RGE_IDR1 0x01 /* MAC address [1] */ 81 #define RGE_IDR2 0x02 /* MAC address [2] */ 82 #define RGE_IDR3 0x03 /* MAC address [3] */ 83 #define RGE_IDR4 0x04 /* MAC address [4] */ 84 #define RGE_IDR5 0x05 /* MAC address [5] */ 85 #define RGE_TNPDS 0x20 /* Tx descriptor base paddr */ 86 #define RGE_THPDS 0x28 /* high pro. Tx des. base paddr */ 87 #define RGE_CR 0x37 /* command */ 88 #define CR_RESET (1U << 4) /* reset S1C */ 89 #define CR_RXEN (1U << 3) /* Rx enable */ 90 #define CR_TXEN (1U << 2) /* Tx enable */ 91 #define RGE_TPPOLL 0x38 /* activate desc polling */ 92 #define RGE_IMR 0x3c /* interrupt mask */ 93 #define RGE_ISR 0x3e /* interrupt status */ 94 #define RGE_TCR 0x40 /* Tx control */ 95 #define TCR_MAXDMA 0x0700 /* 10:8 Tx DMA burst size */ 96 #define RGE_RCR 0x44 /* Rx control */ 97 #define RCR_RXTFH 0xe000 /* 15:13 Rx FIFO threshold */ 98 #define RCR_MAXDMA 0x0700 /* 10:8 Rx DMA burst size */ 99 #define RCR_AE (1U << 5) /* accept error frame */ 100 #define RCR_RE (1U << 4) /* accept runt frame */ 101 #define RCR_AB (1U << 3) /* accept broadcast frame */ 102 #define RCR_AM (1U << 2) /* accept multicast frame */ 103 #define RCR_APM (1U << 1) /* accept unicast frame */ 104 #define RCR_AAP (1U << 0) /* promiscuous */ 105 #define RGE_PHYAR 0x60 /* PHY access */ 106 #define RGE_PHYSR 0x6c /* PHY status */ 107 #define RGE_RMS 0xda /* Rx maximum frame size */ 108 #define RGE_RDSAR 0xe4 /* Rx descriptor base paddr */ 109 #define RGE_ETTHR 0xec /* Tx threshold */ 110 111 #define FRAMESIZE 1536 112 113 struct local { 114 struct desc txd[2]; /* 256B align */ 115 uint8_t _hole0[256 - 2 * sizeof(struct desc)]; 116 struct desc rxd[2]; /* 256B align */ 117 uint8_t _hole1[256 - 2 * sizeof(struct desc)]; 118 uint8_t rxstore[2][FRAMESIZE]; 119 unsigned csr, tx, rx; 120 unsigned phy, bmsr, anlpar; 121 unsigned tcr, rcr; 122 }; 123 124 static int mii_read(struct local *, int, int); 125 static void mii_write(struct local *, int, int, int); 126 static void mii_initphy(struct local *); 127 static void mii_dealan(struct local *, unsigned); 128 129 int 130 rge_match(unsigned tag, void *data) 131 { 132 unsigned v; 133 134 v = pcicfgread(tag, PCI_ID_REG); 135 switch (v) { 136 case PCI_DEVICE(0x10ec, 0x8167): 137 case PCI_DEVICE(0x10ec, 0x8169): 138 return 1; 139 } 140 return 0; 141 } 142 143 void * 144 rge_init(unsigned tag, void *data) 145 { 146 unsigned val; 147 struct local *l; 148 struct desc *txd, *rxd; 149 uint8_t *en = data; 150 151 l = ALLOC(struct local, 256); /* desc alignment */ 152 memset(l, 0, sizeof(struct local)); 153 l->csr = DEVTOV(pcicfgread(tag, 0x14)); /* use mem space */ 154 155 CSR_WRITE_1(l, RGE_CR, CR_RESET); 156 do { 157 val = CSR_READ_1(l, RGE_CR); 158 } while (val & CR_RESET); 159 160 mii_initphy(l); 161 162 en = data; 163 en[0] = CSR_READ_1(l, RGE_IDR0); 164 en[1] = CSR_READ_1(l, RGE_IDR1); 165 en[2] = CSR_READ_1(l, RGE_IDR2); 166 en[3] = CSR_READ_1(l, RGE_IDR3); 167 en[4] = CSR_READ_1(l, RGE_IDR4); 168 en[5] = CSR_READ_1(l, RGE_IDR5); 169 170 printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", 171 en[0], en[1], en[2], en[3], en[4], en[5]); 172 DPRINTF(("PHY %d (%04x.%04x)\n", l->phy, 173 mii_read(l, l->phy, 2), mii_read(l, l->phy, 3))); 174 175 mii_dealan(l, 5); 176 177 /* speed and duplexity can be seen in PHYSR */ 178 val = CSR_READ_1(l, RGE_PHYSR); 179 if (val & (1U << 4)) 180 printf("1000Mbps"); 181 if (val & (1U << 3)) 182 printf("100Mbps"); 183 if (val & (1U << 2)) 184 printf("10Mbps"); 185 if (val & (1U << 0)) 186 printf("-FDX"); 187 printf("\n"); 188 189 txd = &l->txd[0]; 190 txd[1].xd0 = htole32(T0_EOR); 191 rxd = &l->rxd[0]; 192 rxd[0].xd0 = htole32(R0_OWN | FRAMESIZE); 193 rxd[0].xd2 = htole32(VTOPHYS(l->rxstore[0])); 194 rxd[1].xd0 = htole32(R0_OWN | R0_EOR | FRAMESIZE); 195 rxd[1].xd2 = htole32(VTOPHYS(l->rxstore[1])); 196 wbinv(l, sizeof(struct local)); 197 l->tx = l->rx = 0; 198 199 l->tcr = (03 << 24) | (07 << 8); 200 l->rcr = (07 << 13) | (07 << 8) | RCR_APM; 201 CSR_WRITE_1(l, RGE_CR, CR_TXEN | CR_RXEN); 202 CSR_WRITE_1(l, RGE_ETTHR, 0x3f); 203 CSR_WRITE_2(l, RGE_RMS, FRAMESIZE); 204 CSR_WRITE_4(l, RGE_TCR, l->tcr); 205 CSR_WRITE_4(l, RGE_RCR, l->rcr); 206 CSR_WRITE_4(l, RGE_TNPDS, VTOPHYS(txd)); 207 CSR_WRITE_4(l, RGE_RDSAR, VTOPHYS(rxd)); 208 CSR_WRITE_4(l, RGE_TNPDS + 4, 0); 209 CSR_WRITE_4(l, RGE_RDSAR + 4, 0); 210 CSR_WRITE_2(l, RGE_ISR, ~0); 211 CSR_WRITE_2(l, RGE_IMR, 0); 212 return l; 213 } 214 215 int 216 rge_send(void *dev, char *buf, unsigned len) 217 { 218 struct local *l = dev; 219 volatile struct desc *txd; 220 unsigned loop; 221 222 wbinv(buf, len); 223 txd = &l->txd[l->tx]; 224 txd->xd2 = htole32(VTOPHYS(buf)); 225 txd->xd0 &= htole32(T0_EOR); 226 txd->xd0 |= htole32(T0_OWN | T0_FS | T0_LS | (len & T0_FRMASK)); 227 wbinv(txd, sizeof(struct desc)); 228 CSR_WRITE_1(l, RGE_TPPOLL, 0x40); 229 loop = 100; 230 do { 231 if ((le32toh(txd->xd0) & T0_OWN) == 0) 232 goto done; 233 DELAY(10); 234 inv(txd, sizeof(struct desc)); 235 } while (--loop > 0); 236 printf("xmit failed\n"); 237 return -1; 238 done: 239 l->tx ^= 1; 240 return len; 241 } 242 243 int 244 rge_recv(void *dev, char *buf, unsigned maxlen, unsigned timo) 245 { 246 struct local *l = dev; 247 volatile struct desc *rxd; 248 unsigned bound, rxstat, len; 249 uint8_t *ptr; 250 251 bound = 1000 * timo; 252 #if 0 253 printf("recving with %u sec. timeout\n", timo); 254 #endif 255 again: 256 rxd = &l->rxd[l->rx]; 257 do { 258 inv(rxd, sizeof(struct desc)); 259 rxstat = le32toh(rxd->xd0); 260 if ((rxstat & R0_OWN) == 0) 261 goto gotone; 262 DELAY(1000); /* 1 milli second */ 263 } while (--bound > 0); 264 errno = 0; 265 return -1; 266 gotone: 267 if (rxstat & R0_RES) { 268 rxd->xd0 &= htole32(R0_EOR); 269 rxd->xd0 |= htole32(R0_OWN | FRAMESIZE); 270 wbinv(rxd, sizeof(struct desc)); 271 l->rx ^= 1; 272 goto again; 273 } 274 len = rxstat & R0_FRMASK; 275 if (len > maxlen) 276 len = maxlen; 277 ptr = l->rxstore[l->rx]; 278 inv(ptr, len); 279 memcpy(buf, ptr, len); 280 rxd->xd0 &= htole32(R0_EOR); 281 rxd->xd0 |= htole32(R0_OWN | FRAMESIZE); 282 wbinv(rxd, sizeof(struct desc)); 283 l->rx ^= 1; 284 return len; 285 } 286 287 static int 288 mii_read(struct local *l, int phy, int reg) 289 { 290 unsigned v; 291 292 v = reg << 16; 293 CSR_WRITE_4(l, RGE_PHYAR, v); 294 DELAY(1000); 295 do { 296 DELAY(100); 297 v = CSR_READ_4(l, RGE_PHYAR); 298 } while ((v & (1U << 31)) == 0); /* wait for 0 -> 1 */ 299 return v & 0xffff; 300 } 301 302 static void 303 mii_write(struct local *l, int phy, int reg, int data) 304 { 305 unsigned v; 306 307 v = (reg << 16) | (data & 0xffff) | (1U << 31); 308 CSR_WRITE_4(l, RGE_PHYAR, v); 309 DELAY(1000); 310 do { 311 DELAY(100); 312 v = CSR_READ_4(l, RGE_PHYAR); 313 } while (v & (1U << 31)); /* wait for 1 -> 0 */ 314 } 315 316 #define MII_BMCR 0x00 /* Basic mode control register (rw) */ 317 #define BMCR_RESET 0x8000 /* reset */ 318 #define BMCR_AUTOEN 0x1000 /* autonegotiation enable */ 319 #define BMCR_ISO 0x0400 /* isolate */ 320 #define BMCR_STARTNEG 0x0200 /* restart autonegotiation */ 321 #define MII_BMSR 0x01 /* Basic mode status register (ro) */ 322 #define BMSR_ACOMP 0x0020 /* Autonegotiation complete */ 323 #define BMSR_LINK 0x0004 /* Link status */ 324 #define MII_ANAR 0x04 /* Autonegotiation advertisement (rw) */ 325 #define ANAR_FC 0x0400 /* local device supports PAUSE */ 326 #define ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */ 327 #define ANAR_TX 0x0080 /* local device supports 100bTx */ 328 #define ANAR_10_FD 0x0040 /* local device supports 10bT FD */ 329 #define ANAR_10 0x0020 /* local device supports 10bT */ 330 #define ANAR_CSMA 0x0001 /* protocol selector CSMA/CD */ 331 #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */ 332 #define MII_GTCR 0x09 /* 1000baseT control */ 333 #define GANA_1000TFDX 0x0200 /* advertise 1000baseT FDX */ 334 #define GANA_1000THDX 0x0100 /* advertise 1000baseT HDX */ 335 #define MII_GTSR 0x0a /* 1000baseT status */ 336 #define GLPA_1000TFDX 0x0800 /* link partner 1000baseT FDX capable */ 337 #define GLPA_1000THDX 0x0400 /* link partner 1000baseT HDX capable */ 338 #define GLPA_ASM_DIR 0x0200 /* link partner asym. pause dir. capable */ 339 340 static void 341 mii_initphy(struct local *l) 342 { 343 int bound, ctl, phy, sts; 344 345 phy = 7; /* internal rgephy, always at 7 */ 346 ctl = mii_read(l, phy, MII_BMCR); 347 mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET); 348 bound = 100; 349 do { 350 DELAY(10); 351 ctl = mii_read(l, phy, MII_BMCR); 352 if (ctl == 0xffff) { 353 printf("MII: PHY %d has died after reset\n", phy); 354 return; 355 } 356 } while (bound-- > 0 && (ctl & BMCR_RESET)); 357 if (bound == 0) { 358 printf("PHY %d reset failed\n", phy); 359 } 360 ctl &= ~BMCR_ISO; 361 mii_write(l, phy, MII_BMCR, ctl); 362 sts = mii_read(l, phy, MII_BMSR) | 363 mii_read(l, phy, MII_BMSR); /* read twice */ 364 l->phy = phy; 365 l->bmsr = sts; 366 } 367 368 void 369 mii_dealan(struct local *l, unsigned timo) 370 { 371 unsigned anar, gtcr, bound; 372 373 anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA; 374 anar |= ANAR_FC; 375 gtcr = GANA_1000TFDX | GANA_1000THDX; 376 mii_write(l, l->phy, MII_ANAR, anar); 377 mii_write(l, l->phy, MII_GTCR, gtcr); 378 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 379 l->anlpar = 0; 380 bound = getsecs() + timo; 381 do { 382 l->bmsr = mii_read(l, l->phy, MII_BMSR) | 383 mii_read(l, l->phy, MII_BMSR); /* read twice */ 384 if ((l->bmsr & BMSR_LINK) && (l->bmsr & BMSR_ACOMP)) { 385 l->anlpar = mii_read(l, l->phy, MII_ANLPAR); 386 break; 387 } 388 DELAY(10 * 1000); 389 } while (getsecs() < bound); 390 return; 391 } 392
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