Home | History | Annotate | Line # | Download | only in altboot
siisata.c revision 1.4 
      1 /* $NetBSD: siisata.c,v 1.4 2011/05/30 19:48:12 phx Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2008 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Tohru Nishimura.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <sys/param.h>
     33 
     34 #include <lib/libsa/stand.h>
     35 
     36 #include "globals.h"
     37 
     38 static uint32_t pciiobase = PCI_XIOBASE;
     39 
     40 int
     41 siisata_match(unsigned tag, void *data)
     42 {
     43 	unsigned v;
     44 
     45 	v = pcicfgread(tag, PCI_ID_REG);
     46 	switch (v) {
     47 	case PCI_DEVICE(0x1095, 0x3112): /* SiI 3112 SATALink */
     48 	case PCI_DEVICE(0x1095, 0x3512): /*     3512 SATALink */
     49 	case PCI_DEVICE(0x1095, 0x3114): /* SiI 3114 SATALink */
     50 		return 1;
     51 	}
     52 	return 0;
     53 }
     54 
     55 void *
     56 siisata_init(unsigned tag, void *data)
     57 {
     58 	unsigned idreg;
     59 	int n, nchan, retries;
     60 	struct dkdev_ata *l;
     61 
     62 	l = alloc(sizeof(struct dkdev_ata));
     63 	memset(l, 0, sizeof(struct dkdev_ata));
     64 	l->iobuf = allocaligned(512, 16);
     65 	l->tag = tag;
     66 
     67 	idreg = pcicfgread(tag, PCI_ID_REG);
     68 	l->bar[0] = pciiobase + (pcicfgread(tag, 0x10) &~ 01);
     69 	l->bar[1] = pciiobase + (pcicfgread(tag, 0x14) &~ 01);
     70 	l->bar[2] = pciiobase + (pcicfgread(tag, 0x18) &~ 01);
     71 	l->bar[3] = pciiobase + (pcicfgread(tag, 0x1c) &~ 01);
     72 	l->bar[4] = pciiobase + (pcicfgread(tag, 0x20) &~ 01);
     73 	l->bar[5] = pcicfgread(tag, 0x24) &~ 0x3ff;
     74 
     75 	if ((PCI_PRODUCT(idreg) & 0xf) == 0x2) {
     76 		/* 3112/3512 */
     77 		l->chan[0].cmd = l->bar[0];
     78 		l->chan[0].ctl = l->chan[0].alt = l->bar[1] | 02;
     79 		l->chan[0].dma = l->bar[4] + 0x0;
     80 		l->chan[1].cmd = l->bar[2];
     81 		l->chan[1].ctl = l->chan[1].alt = l->bar[3] | 02;
     82 		l->chan[1].dma = l->bar[4] + 0x8;
     83 		nchan = 2;
     84 	}
     85 	else {
     86 		/* 3114 - assume BA5 access is possible XXX */
     87 		l->chan[0].cmd = l->bar[5] + 0x080;
     88 		l->chan[0].ctl = l->chan[0].alt = (l->bar[5] + 0x088) | 02;
     89 		l->chan[1].cmd = l->bar[5] + 0x0c0;
     90 		l->chan[1].ctl = l->chan[1].alt = (l->bar[5] + 0x0c8) | 02;
     91 		l->chan[2].cmd = l->bar[5] + 0x280;
     92 		l->chan[2].ctl = l->chan[2].alt = (l->bar[5] + 0x288) | 02;
     93 		l->chan[3].cmd = l->bar[5] + 0x2c0;
     94 		l->chan[3].ctl = l->chan[3].alt = (l->bar[5] + 0x2c8) | 02;
     95 		nchan = 4;
     96 	}
     97 
     98 	/* configure PIO transfer mode */
     99 	pcicfgwrite(tag, 0x80, 0x00);
    100 	pcicfgwrite(tag, 0x84, 0x00);
    101 
    102 	for (n = 0, retries = 0; n < nchan; n++) {
    103 		l->presense[n] = 0;
    104 
    105 		if (satapresense(l, n)) {
    106 			/* drive present, now check whether soft reset works */
    107 			while (retries++ < 10) {
    108 				if (perform_atareset(l, n)) {
    109 					DPRINTF(("port %d device present\n", n));
    110 					l->presense[n] = 1;
    111 					break;
    112 				}
    113 				/* give the drive another second to spin up */
    114 				if (retries < 10)
    115 					delay(1000 * 1000);
    116 			}
    117 		}
    118 	}
    119 	return l;
    120 }
    121