skg.c revision 1.1
1 /* $NetBSD: skg.c,v 1.1 2011/01/23 01:05:30 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Frank Wille. 5 * All rights reserved. 6 * 7 * Written by Frank Wille for The NetBSD Project. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 33 #include <netinet/in.h> 34 #include <netinet/in_systm.h> 35 36 #include <lib/libsa/stand.h> 37 #include <lib/libsa/net.h> 38 39 #include "globals.h" 40 41 /* 42 * - reverse endian access every CSR. 43 * - no vtophys() translation, vaddr_t == paddr_t. 44 * - PIPT writeback cache aware. 45 */ 46 #define CSR_WRITE_1(l, r, v) *(volatile uint8_t *)((l)->csr+(r)) = (v) 47 #define CSR_READ_1(l, r) *(volatile uint8_t *)((l)->csr+(r)) 48 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v)) 49 #define CSR_READ_2(l, r) in16rb((l)->csr+(r)) 50 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) 51 #define CSR_READ_4(l, r) in32rb((l)->csr+(r)) 52 #define VTOPHYS(va) (uint32_t)(va) 53 #define DEVTOV(pa) (uint32_t)(pa) 54 #define wbinv(adr, siz) _wbinv(VTOPHYS(adr), (uint32_t)(siz)) 55 #define inv(adr, siz) _inv(VTOPHYS(adr), (uint32_t)(siz)) 56 #define DELAY(n) delay(n) 57 #define ALLOC(T,A) (T *)allocaligned(sizeof(T),(A)) 58 59 struct desc { 60 uint32_t xd0, xd1, xd2, xd3, xd4; 61 uint32_t rsrvd[3]; 62 }; 63 #define CTL_LS 0x20000000 64 #define CTL_FS 0x40000000 65 #define CTL_OWN 0x80000000 66 #define CTL_DEFOPC 0x00550000 67 #define FRAMEMASK 0x0000ffff 68 #define RXSTAT_RXOK 0x00000100 69 70 #define SK_CSR 0x0004 71 #define CSR_SW_RESET 0x0001 72 #define CSR_SW_UNRESET 0x0002 73 #define CSR_MASTER_RESET 0x0004 74 #define CSR_MASTER_UNRESET 0x0008 75 #define SK_IMR 0x000c 76 #define SK_BMU_RX_CSR0 0x0060 77 #define SK_BMU_TXS_CSR0 0x0068 78 #define SK_MAC0 0x0100 79 #define SK_MAC1 0x0108 80 #define SK_GPIO 0x015c 81 #define SK_RAMCTL 0x01a0 82 #define SK_TXAR1_COUNTERCTL 0x0210 83 #define TXARCTL_ON 0x02 84 #define TXARCTL_FSYNC_ON 0x80 85 #define SK_RXQ1_CURADDR_LO 0x0420 86 #define SK_RXQ1_CURADDR_HI 0x0424 87 #define SK_RXQ1_BMU_CSR 0x0434 88 #define RXBMU_CLR_IRQ_EOF 0x00000002 89 #define RXBMU_RX_START 0x00000010 90 #define RXBMU_RX_STOP 0x00000020 91 #define RXBMU_POLL_ON 0x00000080 92 #define RXBMU_TRANSFER_SM_UNRESET 0x00000200 93 #define RXBMU_DESCWR_SM_UNRESET 0x00000800 94 #define RXBMU_DESCRD_SM_UNRESET 0x00002000 95 #define RXBMU_SUPERVISOR_SM_UNRESET 0x00008000 96 #define RXBMU_PFI_SM_UNRESET 0x00020000 97 #define RXBMU_FIFO_UNRESET 0x00080000 98 #define RXBMU_DESC_UNRESET 0x00200000 99 #define SK_TXQS1_CURADDR_LO 0x0620 100 #define SK_TXQS1_CURADDR_HI 0x0624 101 #define SK_TXQS1_BMU_CSR 0x0634 102 #define TXBMU_CLR_IRQ_EOF 0x00000002 103 #define TXBMU_TX_START 0x00000010 104 #define TXBMU_TX_STOP 0x00000020 105 #define TXBMU_POLL_ON 0x00000080 106 #define TXBMU_TRANSFER_SM_UNRESET 0x00000200 107 #define TXBMU_DESCWR_SM_UNRESET 0x00000800 108 #define TXBMU_DESCRD_SM_UNRESET 0x00002000 109 #define TXBMU_SUPERVISOR_SM_UNRESET 0x00008000 110 #define TXBMU_PFI_SM_UNRESET 0x00020000 111 #define TXBMU_FIFO_UNRESET 0x00080000 112 #define TXBMU_DESC_UNRESET 0x00200000 113 #define SK_RXRB1_START 0x0800 114 #define SK_RXRB1_END 0x0804 115 #define SK_RXRB1_WR_PTR 0x0808 116 #define SK_RXRB1_RD_PTR 0x080c 117 #define SK_RXRB1_CTLTST 0x0828 118 #define RBCTL_UNRESET 0x02 119 #define RBCTL_ON 0x08 120 #define RBCTL_STORENFWD_ON 0x20 121 #define SK_TXRBS1_START 0x0a00 122 #define SK_TXRBS1_END 0x0a04 123 #define SK_TXRBS1_WR_PTR 0x0a08 124 #define SK_TXRBS1_RD_PTR 0x0a0c 125 #define SK_TXRBS1_CTLTST 0x0a28 126 #define SK_RXMF1_CTRL_TEST 0x0c48 127 #define RFCTL_OPERATION_ON 0x00000008 128 #define RFCTL_RESET_CLEAR 0x00000002 129 #define SK_TXMF1_CTRL_TEST 0x0D48 130 #define TFCTL_OPERATION_ON 0x00000008 131 #define TFCTL_RESET_CLEAR 0x00000002 132 #define SK_GMAC_CTRL 0x0f00 133 #define GMAC_LOOP_OFF 0x00000010 134 #define GMAC_PAUSE_ON 0x00000008 135 #define GMAC_RESET_CLEAR 0x00000002 136 #define GMAC_RESET_SET 0x00000001 137 #define SK_GPHY_CTRL 0x0f04 138 #define GPHY_INT_POL_HI 0x08000000 139 #define GPHY_DIS_FC 0x02000000 140 #define GPHY_DIS_SLEEP 0x01000000 141 #define GPHY_ENA_XC 0x00040000 142 #define GPHY_ENA_PAUSE 0x00002000 143 #define GPHY_RESET_CLEAR 0x00000002 144 #define GPHY_RESET_SET 0x00000001 145 #define GPHY_ANEG_ALL 0x0009c000 146 #define GPHY_COPPER 0x00f00000 147 #define SK_LINK_CTRL 0x0f10 148 #define LINK_RESET_CLEAR 0x0002 149 #define LINK_RESET_SET 0x0001 150 151 #define YUKON_GPCR 0x2804 152 #define GPCR_TXEN 0x1000 153 #define GPCR_RXEN 0x0800 154 #define YUKON_SA1 0x281c 155 #define YUKON_SA2 0x2828 156 #define YUKON_SMICR 0x2880 157 #define SMICR_PHYAD(x) (((x) & 0x1f) << 11) 158 #define SMICR_REGAD(x) (((x) & 0x1f) << 6) 159 #define SMICR_OP_READ 0x0020 160 #define SMICR_OP_WRITE 0x0000 161 #define SMICR_READ_VALID 0x0010 162 #define SMICR_BUSY 0x0008 163 #define YUKON_SMIDR 0x2884 164 165 #define MII_PSSR 0x11 /* MAKPHY status register */ 166 #define PSSR_DUPLEX 0x2000 /* FDX */ 167 #define PSSR_RESOLVED 0x0800 /* speed and duplex resolved */ 168 #define PSSR_LINK 0x0400 /* link indication */ 169 #define PSSR_SPEED(x) (((x) >> 14) & 0x3) 170 #define SPEED10 0 171 #define SPEED100 1 172 #define SPEED1000 2 173 174 #define FRAMESIZE 1536 175 176 struct local { 177 struct desc txd[2]; 178 struct desc rxd[2]; 179 uint8_t rxstore[2][FRAMESIZE]; 180 unsigned csr, rx, tx, phy; 181 uint16_t pssr, anlpar; 182 }; 183 184 static int mii_read(struct local *, int, int); 185 static void mii_write(struct local *, int, int, int); 186 static void mii_initphy(struct local *); 187 static void mii_dealan(struct local *, unsigned); 188 189 int 190 skg_match(unsigned tag, void *data) 191 { 192 unsigned v; 193 194 v = pcicfgread(tag, PCI_ID_REG); 195 switch (v) { 196 case PCI_DEVICE(0x11ab, 0x4320): 197 return 1; 198 } 199 return 0; 200 } 201 202 void * 203 skg_init(unsigned tag, void *data) 204 { 205 struct local *l; 206 struct desc *txd, *rxd; 207 uint8_t *en; 208 unsigned i; 209 uint16_t reg; 210 211 l = ALLOC(struct local, 32); /* desc alignment */ 212 memset(l, 0, sizeof(struct local)); 213 l->csr = DEVTOV(pcicfgread(tag, 0x10)); /* use mem space */ 214 215 /* reset the chip */ 216 CSR_WRITE_2(l, SK_CSR, CSR_SW_RESET); 217 CSR_WRITE_2(l, SK_CSR, CSR_MASTER_RESET); 218 CSR_WRITE_2(l, SK_LINK_CTRL, LINK_RESET_SET); 219 DELAY(1000); 220 CSR_WRITE_2(l, SK_CSR, CSR_SW_UNRESET); 221 DELAY(2); 222 CSR_WRITE_2(l, SK_CSR, CSR_MASTER_UNRESET); 223 CSR_WRITE_2(l, SK_LINK_CTRL, LINK_RESET_CLEAR); 224 CSR_WRITE_4(l, SK_RAMCTL, 2); /* enable RAM interface */ 225 226 mii_initphy(l); 227 228 /* read ethernet address */ 229 en = data; 230 if (brdtype == BRD_SYNOLOGY) 231 read_mac_from_flash(en); 232 else 233 for (i = 0; i < 6; i++) 234 en[i] = CSR_READ_1(l, SK_MAC0 + i); 235 printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", 236 en[0], en[1], en[2], en[3], en[4], en[5]); 237 printf("PHY %d (%04x.%04x)\n", l->phy, 238 mii_read(l, l->phy, 2), mii_read(l, l->phy, 3)); 239 240 /* set station address */ 241 for (i = 0; i < 3; i++) 242 CSR_WRITE_2(l, YUKON_SA1 + i * 4, 243 (en[i * 2] << 8) | en[i * 2 + 1]); 244 245 /* configure RX and TX MAC FIFO */ 246 CSR_WRITE_1(l, SK_RXMF1_CTRL_TEST, RFCTL_RESET_CLEAR); 247 CSR_WRITE_4(l, SK_RXMF1_CTRL_TEST, RFCTL_OPERATION_ON); 248 CSR_WRITE_1(l, SK_TXMF1_CTRL_TEST, TFCTL_RESET_CLEAR); 249 CSR_WRITE_4(l, SK_TXMF1_CTRL_TEST, TFCTL_OPERATION_ON); 250 251 mii_dealan(l, 5); 252 253 switch (PSSR_SPEED(l->pssr)) { 254 case SPEED1000: 255 printf("1000Mbps"); 256 break; 257 case SPEED100: 258 printf("100Mbps"); 259 break; 260 case SPEED10: 261 printf("10Mbps"); 262 break; 263 } 264 if (l->pssr & PSSR_DUPLEX) 265 printf("-FDX"); 266 printf("\n"); 267 268 /* configure RAM buffers, assuming 64k RAM */ 269 CSR_WRITE_4(l, SK_RXRB1_CTLTST, RBCTL_UNRESET); 270 CSR_WRITE_4(l, SK_RXRB1_START, 0); 271 CSR_WRITE_4(l, SK_RXRB1_WR_PTR, 0); 272 CSR_WRITE_4(l, SK_RXRB1_RD_PTR, 0); 273 CSR_WRITE_4(l, SK_RXRB1_END, 0xfff); 274 CSR_WRITE_4(l, SK_RXRB1_CTLTST, RBCTL_ON); 275 CSR_WRITE_4(l, SK_TXRBS1_CTLTST, RBCTL_UNRESET); 276 CSR_WRITE_4(l, SK_TXRBS1_CTLTST, RBCTL_STORENFWD_ON); 277 CSR_WRITE_4(l, SK_TXRBS1_START, 0x1000); 278 CSR_WRITE_4(l, SK_TXRBS1_WR_PTR, 0x1000); 279 CSR_WRITE_4(l, SK_TXRBS1_RD_PTR, 0x1000); 280 CSR_WRITE_4(l, SK_TXRBS1_END, 0x1fff); 281 CSR_WRITE_4(l, SK_TXRBS1_CTLTST, RBCTL_ON); 282 283 /* setup descriptors and BMU */ 284 CSR_WRITE_1(l, SK_TXAR1_COUNTERCTL, TXARCTL_ON|TXARCTL_FSYNC_ON); 285 286 txd = &l->txd[0]; 287 txd[0].xd1 = htole32(VTOPHYS(&txd[1])); 288 txd[1].xd1 = htole32(VTOPHYS(&txd[0])); 289 rxd = &l->rxd[0]; 290 rxd[0].xd0 = htole32(FRAMESIZE|CTL_DEFOPC|CTL_LS|CTL_FS|CTL_OWN); 291 rxd[0].xd1 = htole32(VTOPHYS(&rxd[1])); 292 rxd[0].xd2 = htole32(VTOPHYS(l->rxstore[0])); 293 rxd[1].xd0 = htole32(FRAMESIZE|CTL_DEFOPC|CTL_LS|CTL_FS|CTL_OWN); 294 rxd[1].xd1 = htole32(VTOPHYS(&rxd[0])); 295 rxd[1].xd2 = htole32(VTOPHYS(l->rxstore[1])); 296 wbinv(l, sizeof(struct local)); 297 298 CSR_WRITE_4(l, SK_RXQ1_BMU_CSR, 299 RXBMU_TRANSFER_SM_UNRESET|RXBMU_DESCWR_SM_UNRESET| 300 RXBMU_DESCRD_SM_UNRESET|RXBMU_SUPERVISOR_SM_UNRESET| 301 RXBMU_PFI_SM_UNRESET|RXBMU_FIFO_UNRESET| 302 RXBMU_DESC_UNRESET); 303 CSR_WRITE_4(l, SK_RXQ1_CURADDR_LO, VTOPHYS(rxd)); 304 CSR_WRITE_4(l, SK_RXQ1_CURADDR_HI, 0); 305 306 CSR_WRITE_4(l, SK_TXQS1_BMU_CSR, 307 TXBMU_TRANSFER_SM_UNRESET|TXBMU_DESCWR_SM_UNRESET| 308 TXBMU_DESCRD_SM_UNRESET|TXBMU_SUPERVISOR_SM_UNRESET| 309 TXBMU_PFI_SM_UNRESET|TXBMU_FIFO_UNRESET| 310 TXBMU_DESC_UNRESET|TXBMU_POLL_ON); 311 CSR_WRITE_4(l, SK_TXQS1_CURADDR_LO, VTOPHYS(txd)); 312 CSR_WRITE_4(l, SK_TXQS1_CURADDR_HI, 0); 313 314 CSR_WRITE_4(l, SK_IMR, 0); 315 CSR_WRITE_4(l, SK_RXQ1_BMU_CSR, RXBMU_RX_START); 316 reg = CSR_READ_2(l, YUKON_GPCR); 317 reg |= GPCR_TXEN | GPCR_RXEN; 318 CSR_WRITE_2(l, YUKON_GPCR, reg); 319 320 return l; 321 } 322 323 int 324 skg_send(void *dev, char *buf, unsigned len) 325 { 326 struct local *l = dev; 327 volatile struct desc *txd; 328 unsigned loop; 329 330 wbinv(buf, len); 331 txd = &l->txd[l->tx]; 332 txd->xd2 = htole32(VTOPHYS(buf)); 333 txd->xd0 = htole32((len & FRAMEMASK)|CTL_DEFOPC|CTL_FS|CTL_LS|CTL_OWN); 334 wbinv(txd, sizeof(struct desc)); 335 CSR_WRITE_4(l, SK_BMU_TXS_CSR0, TXBMU_TX_START); 336 loop = 100; 337 do { 338 if ((le32toh(txd->xd0) & CTL_OWN) == 0) 339 goto done; 340 DELAY(10); 341 inv(txd, sizeof(struct desc)); 342 } while (--loop > 0); 343 printf("xmit failed\n"); 344 return -1; 345 done: 346 l->tx ^= 1; 347 return len; 348 } 349 350 int 351 skg_recv(void *dev, char *buf, unsigned maxlen, unsigned timo) 352 { 353 struct local *l = dev; 354 volatile struct desc *rxd; 355 unsigned bound, ctl, rxstat, len; 356 uint8_t *ptr; 357 358 bound = 1000 * timo; 359 #if 0 360 printf("recving with %u sec. timeout\n", timo); 361 #endif 362 again: 363 rxd = &l->rxd[l->rx]; 364 do { 365 inv(rxd, sizeof(struct desc)); 366 ctl = le32toh(rxd->xd0); 367 if ((ctl & CTL_OWN) == 0) 368 goto gotone; 369 DELAY(1000); /* 1 milli second */ 370 } while (--bound > 0); 371 errno = 0; 372 return -1; 373 gotone: 374 rxstat = le32toh(rxd->xd4); 375 if ((rxstat & RXSTAT_RXOK) == 0) { 376 rxd->xd0 = htole32(FRAMESIZE|CTL_DEFOPC|CTL_LS|CTL_FS|CTL_OWN); 377 wbinv(rxd, sizeof(struct desc)); 378 l->rx ^= 1; 379 goto again; 380 } 381 len = ctl & FRAMEMASK; 382 if (len > maxlen) 383 len = maxlen; 384 ptr = l->rxstore[l->rx]; 385 inv(ptr, len); 386 memcpy(buf, ptr, len); 387 rxd->xd0 = htole32(FRAMESIZE|CTL_DEFOPC|CTL_LS|CTL_FS|CTL_OWN); 388 wbinv(rxd, sizeof(struct desc)); 389 l->rx ^= 1; 390 return len; 391 } 392 393 static int 394 mii_read(struct local *l, int phy, int reg) 395 { 396 unsigned loop, v; 397 398 CSR_WRITE_2(l, YUKON_SMICR, SMICR_PHYAD(phy) | SMICR_REGAD(reg) | 399 SMICR_OP_READ); 400 loop = 1000; 401 do { 402 DELAY(1); 403 v = CSR_READ_2(l, YUKON_SMICR); 404 } while ((v & SMICR_READ_VALID) == 0 && --loop); 405 if (loop == 0) { 406 printf("mii_read timeout!\n"); 407 return 0; 408 } 409 return CSR_READ_2(l, YUKON_SMIDR); 410 } 411 412 static void 413 mii_write(struct local *l, int phy, int reg, int data) 414 { 415 unsigned loop, v; 416 417 CSR_WRITE_2(l, YUKON_SMIDR, data); 418 CSR_WRITE_2(l, YUKON_SMICR, SMICR_PHYAD(phy) | SMICR_REGAD(reg) | 419 SMICR_OP_WRITE); 420 loop = 1000; 421 do { 422 DELAY(1); 423 v = CSR_READ_2(l, YUKON_SMICR); 424 } while ((v & SMICR_BUSY) != 0 && --loop); 425 if (loop == 0) 426 printf("mii_write timeout!\n"); 427 } 428 429 #define MII_BMCR 0x00 /* Basic mode control register (rw) */ 430 #define BMCR_AUTOEN 0x1000 /* autonegotiation enable */ 431 #define BMCR_STARTNEG 0x0200 /* restart autonegotiation */ 432 #define MII_BMSR 0x01 /* Basic mode status register (ro) */ 433 #define BMSR_ACOMP 0x0020 /* Autonegotiation complete */ 434 #define BMSR_LINK 0x0004 /* Link status */ 435 #define MII_ANAR 0x04 /* Autonegotiation advertisement (rw) */ 436 #define ANAR_FC 0x0400 /* local device supports PAUSE */ 437 #define ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */ 438 #define ANAR_TX 0x0080 /* local device supports 100bTx */ 439 #define ANAR_10_FD 0x0040 /* local device supports 10bT FD */ 440 #define ANAR_10 0x0020 /* local device supports 10bT */ 441 #define ANAR_CSMA 0x0001 /* protocol selector CSMA/CD */ 442 #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */ 443 #define MII_GTCR 0x09 /* 1000baseT control */ 444 #define GANA_1000TFDX 0x0200 /* advertise 1000baseT FDX */ 445 #define GANA_1000THDX 0x0100 /* advertise 1000baseT HDX */ 446 #define MII_GTSR 0x0a /* 1000baseT status */ 447 #define GLPA_1000TFDX 0x0800 /* link partner 1000baseT FDX capable */ 448 #define GLPA_1000THDX 0x0400 /* link partner 1000baseT HDX capable */ 449 450 static void 451 mii_initphy(struct local *l) 452 { 453 unsigned val; 454 455 l->phy = 0; 456 457 /* take PHY out of reset */ 458 val = CSR_READ_4(l, SK_GPIO); 459 CSR_WRITE_4(l, SK_GPIO, (val | 0x2000000) & ~0x200); 460 461 /* GMAC and GPHY reset */ 462 CSR_WRITE_4(l, SK_GPHY_CTRL, GPHY_RESET_SET); 463 CSR_WRITE_4(l, SK_GMAC_CTRL, GMAC_RESET_SET); 464 DELAY(1000); 465 CSR_WRITE_4(l, SK_GMAC_CTRL, GMAC_RESET_CLEAR); 466 CSR_WRITE_4(l, SK_GMAC_CTRL, GMAC_RESET_SET); 467 DELAY(1000); 468 469 val = GPHY_INT_POL_HI | GPHY_DIS_FC | GPHY_DIS_SLEEP | GPHY_ENA_XC | 470 GPHY_ANEG_ALL | GPHY_ENA_PAUSE | GPHY_COPPER; 471 CSR_WRITE_4(l, SK_GPHY_CTRL, val | GPHY_RESET_SET); 472 DELAY(1000); 473 CSR_WRITE_4(l, SK_GPHY_CTRL, val | GPHY_RESET_CLEAR); 474 CSR_WRITE_4(l, SK_GMAC_CTRL, GMAC_LOOP_OFF | GMAC_PAUSE_ON | 475 GMAC_RESET_CLEAR); 476 } 477 478 static void 479 mii_dealan(struct local *l, unsigned timo) 480 { 481 unsigned bmsr, bound; 482 483 mii_write(l, l->phy, MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 484 ANAR_10 | ANAR_CSMA | ANAR_FC); 485 mii_write(l, l->phy, MII_GTCR, GANA_1000TFDX | GANA_1000THDX); 486 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 487 l->anlpar = 0; 488 bound = getsecs() + timo; 489 do { 490 bmsr = mii_read(l, l->phy, MII_BMSR) | 491 mii_read(l, l->phy, MII_BMSR); /* read twice */ 492 if ((bmsr & BMSR_LINK) && (bmsr & BMSR_ACOMP)) { 493 l->pssr = mii_read(l, l->phy, MII_PSSR); 494 l->anlpar = mii_read(l, l->phy, MII_ANLPAR); 495 if ((l->pssr & PSSR_RESOLVED) == 0) 496 continue; 497 break; 498 } 499 DELAY(10 * 1000); 500 } while (getsecs() < bound); 501 } 502
Indexes created Tue Sep 30 11:09:46 GMT 2025