stg.c revision 1.3
1 /* $NetBSD: stg.c,v 1.3 2011/03/10 21:11:50 phx Exp $ */ 2 3 /*- 4 * Copyright (c) 2011 Frank Wille. 5 * All rights reserved. 6 * 7 * Written by Frank Wille for The NetBSD Project. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 33 #include <netinet/in.h> 34 #include <netinet/in_systm.h> 35 36 #include <lib/libsa/stand.h> 37 #include <lib/libsa/net.h> 38 39 #include "globals.h" 40 41 #define CSR_WRITE_1(l, r, v) *(volatile uint8_t *)((l)->csr+(r)) = (v) 42 #define CSR_READ_1(l, r) *(volatile uint8_t *)((l)->csr+(r)) 43 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v)) 44 #define CSR_READ_2(l, r) in16rb((l)->csr+(r)) 45 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) 46 #define CSR_READ_4(l, r) in32rb((l)->csr+(r)) 47 #define VTOPHYS(va) (uint32_t)(va) 48 #define DEVTOV(pa) (uint32_t)(pa) 49 #define wbinv(adr, siz) _wbinv(VTOPHYS(adr), (uint32_t)(siz)) 50 #define inv(adr, siz) _inv(VTOPHYS(adr), (uint32_t)(siz)) 51 #define DELAY(n) delay(n) 52 #define ALLOC(T,A) (T *)allocaligned(sizeof(T),(A)) 53 54 struct desc { 55 uint64_t xd0, xd1, xd2, dummy; 56 }; 57 #define T1_EMPTY (1U << 31) /* no Tx frame available */ 58 #define T1_NOALIGN (03 << 16) /* allow any Tx alignment */ 59 #define T1_CNTSHIFT 24 /* Tx fragment count */ 60 #define T2_LENSHIFT 48 /* Tx frame length */ 61 #define R1_DONE (1U << 31) /* desc has a Rx frame */ 62 #define R1_FL_MASK 0xffff /* Rx frame length */ 63 #define R1_ER_MASK 0x3f0000 /* Rx error indication */ 64 65 #define STGE_DMACtrl 0x00 66 #define DMAC_RxDMAPollNow (1U << 4) 67 #define DMAC_TxDMAPollNow (1U << 12) 68 #define STGE_TFDListPtrLo 0x10 69 #define STGE_TFDListPtrHi 0x14 70 #define STGE_RFDListPtrLo 0x1c 71 #define STGE_RFDListPtrHi 0x20 72 #define STGE_DebugCtrl 0x2c 73 #define STGE_AsicCtrl 0x30 74 #define AC_PhyMedia (1U << 7) 75 #define AC_GlobalReset (1U << 16) 76 #define AC_RxReset (1U << 17) 77 #define AC_TxReset (1U << 18) 78 #define AC_DMA (1U << 19) 79 #define AC_FIFO (1U << 20) 80 #define AC_Network (1U << 21) 81 #define AC_Host (1U << 22) 82 #define AC_AutoInit (1U << 23) 83 #define AC_RstOut (1U << 24) 84 #define AC_ResetBusy (1U << 26) 85 #define STGE_EepromData 0x48 86 #define STGE_EepromCtrl 0x4a 87 #define EC_EepromAddress(x) ((x) & 0xff) 88 #define EC_EepromOpcode(x) ((x) << 8) 89 #define EC_OP_RR 2 90 #define EC_EepromBusy (1U << 15) 91 #define STGE_IntEnable 0x5c 92 #define STGE_MACCtrl 0x6c 93 #define MC_DuplexSelect (1U << 5) 94 #define MC_StatisticsDisable (1U << 22) 95 #define MC_TxEnable (1U << 24) 96 #define MC_RxEnable (1U << 27) 97 #define STGE_PhyCtrl 0x76 98 #define PC_MgmtClk (1U << 0) 99 #define PC_MgmtData (1U << 1) 100 #define PC_MgmtDir (1U << 2) 101 #define PC_PhyDuplexPolarity (1U << 3) 102 #define PC_PhyDuplexStatus (1U << 4) 103 #define PC_PhyLnkPolarity (1U << 5) 104 #define PC_LinkSpeed(x) (((x) >> 6) & 3) 105 #define PC_LinkSpeed_Down 0 106 #define PC_LinkSpeed_10 1 107 #define PC_LinkSpeed_100 2 108 #define PC_LinkSpeed_1000 3 109 #define STGE_StationAddress0 0x78 110 #define STGE_StationAddress1 0x7a 111 #define STGE_StationAddress2 0x7c 112 #define STGE_MaxFrameSize 0x84 113 #define STGE_ReceiveMode 0x88 114 #define RM_ReceiveUnicast (1U << 0) 115 #define RM_ReceiveMulticast (1U << 1) 116 #define RM_ReceiveBroadcast (1U << 2) 117 #define RM_ReceiveAllFrames (1U << 3) 118 #define RM_ReceiveMulticastHash (1U << 4) 119 #define RM_ReceiveIPMulticast (1U << 5) 120 121 #define STGE_EEPROM_SA0 0x10 122 123 #define FRAMESIZE 1536 124 125 struct local { 126 struct desc txd[2]; 127 struct desc rxd[2]; 128 uint8_t rxstore[2][FRAMESIZE]; 129 unsigned csr, rx, tx, phy; 130 uint16_t bmsr, anlpar; 131 uint8_t phyctrl_saved; 132 }; 133 134 static int mii_read(struct local *, int, int); 135 static void mii_write(struct local *, int, int, int); 136 static void mii_initphy(struct local *); 137 static void mii_dealan(struct local *, unsigned); 138 static void mii_bitbang_sync(struct local *); 139 static void mii_bitbang_send(struct local *, uint32_t, int); 140 static void mii_bitbang_clk(struct local *, uint8_t); 141 static int eeprom_wait(struct local *); 142 143 int 144 stg_match(unsigned tag, void *data) 145 { 146 unsigned v; 147 148 v = pcicfgread(tag, PCI_ID_REG); 149 switch (v) { 150 case PCI_DEVICE(0x13f0, 0x1023): /* ST1023, IP1000A */ 151 return 1; 152 } 153 return 0; 154 } 155 156 void * 157 stg_init(unsigned tag, void *data) 158 { 159 struct local *l; 160 struct desc *txd, *rxd; 161 uint8_t *en; 162 unsigned i; 163 uint32_t macctl, reg; 164 165 l = ALLOC(struct local, 32); /* desc alignment */ 166 memset(l, 0, sizeof(struct local)); 167 l->csr = DEVTOV(pcicfgread(tag, 0x14)); /* first try mem space */ 168 if (l->csr == 0) 169 l->csr = DEVTOV(PCI_XIOBASE + (pcicfgread(tag, 0x10) & ~01)); 170 171 /* reset the chip */ 172 reg = CSR_READ_4(l, STGE_AsicCtrl); 173 CSR_WRITE_4(l, STGE_AsicCtrl, reg | AC_GlobalReset | AC_RxReset | 174 AC_TxReset | AC_DMA | AC_FIFO | AC_Network | AC_Host | 175 AC_AutoInit | ((reg & AC_PhyMedia) ? AC_RstOut : 0)); 176 DELAY(50000); 177 for (i = 0; i < 1000; i++) { 178 DELAY(5000); 179 if ((CSR_READ_4(l, STGE_AsicCtrl) & AC_ResetBusy) == 0) 180 break; 181 } 182 if (i >= 1000) 183 printf("NIC reset failed to complete!\n"); 184 DELAY(1000); 185 186 mii_initphy(l); 187 188 /* read ethernet address */ 189 en = data; 190 if (PCI_PRODUCT(pcicfgread(tag, PCI_ID_REG)) != 0x1023) { 191 /* read from station address registers when not ST1023 */ 192 en[0] = CSR_READ_2(l, STGE_StationAddress0) & 0xff; 193 en[1] = CSR_READ_2(l, STGE_StationAddress0) >> 8; 194 en[2] = CSR_READ_2(l, STGE_StationAddress1) & 0xff; 195 en[3] = CSR_READ_2(l, STGE_StationAddress1) >> 8; 196 en[4] = CSR_READ_2(l, STGE_StationAddress2) & 0xff; 197 en[5] = CSR_READ_2(l, STGE_StationAddress2) >> 8; 198 } else { 199 /* ST1023: read the address from the serial EEPROM */ 200 static uint8_t bad[2][6] = { 201 { 0x00,0x00,0x00,0x00,0x00,0x00 }, 202 { 0xff,0xff,0xff,0xff,0xff,0xff } 203 }; 204 uint16_t addr[3]; 205 206 for (i = 0; i < 3; i++) { 207 if (eeprom_wait(l) != 0) 208 printf("NIC: serial EEPROM is not ready!\n"); 209 CSR_WRITE_2(l, STGE_EepromCtrl, 210 EC_EepromAddress(STGE_EEPROM_SA0 + i) | 211 EC_EepromOpcode(EC_OP_RR)); 212 if (eeprom_wait(l) != 0) 213 printf("NIC: serial EEPROM read time out!\n"); 214 addr[i] = le16toh(CSR_READ_2(l, STGE_EepromData)); 215 } 216 (void)memcpy(en, addr, 6); 217 218 /* try to read MAC from Flash, when EEPROM is empty/missing */ 219 if (memcmp(en, bad[0], 6) == 0 || memcmp(en, bad[1], 6) == 0) 220 read_mac_from_flash(en); 221 222 /* set the station address now */ 223 for (i = 0; i < 6; i++) 224 CSR_WRITE_1(l, STGE_StationAddress0 + i, en[i]); 225 } 226 printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", 227 en[0], en[1], en[2], en[3], en[4], en[5]); 228 229 DPRINTF(("PHY %d (%04x.%04x)\n", l->phy, 230 mii_read(l, l->phy, 2), mii_read(l, l->phy, 3))); 231 232 /* setup descriptors */ 233 txd = &l->txd[0]; 234 txd[0].xd0 = htole64(VTOPHYS(&txd[1])); 235 txd[0].xd1 = htole64(T1_EMPTY); 236 txd[1].xd0 = htole64(VTOPHYS(&txd[0])); 237 txd[1].xd1 = htole64(T1_EMPTY); 238 rxd = &l->rxd[0]; 239 rxd[0].xd0 = htole64(VTOPHYS(&rxd[1])); 240 rxd[0].xd2 = htole64((uint64_t)VTOPHYS(l->rxstore[0]) | 241 ((uint64_t)FRAMESIZE << 48)); 242 rxd[1].xd0 = htole64(VTOPHYS(&rxd[0])); 243 rxd[1].xd2 = htole64((uint64_t)VTOPHYS(l->rxstore[1]) | 244 ((uint64_t)FRAMESIZE << 48)); 245 wbinv(l, sizeof(struct local)); 246 247 CSR_WRITE_2(l, STGE_IntEnable, 0); 248 CSR_WRITE_2(l, STGE_ReceiveMode, RM_ReceiveUnicast | 249 RM_ReceiveBroadcast | RM_ReceiveAllFrames | RM_ReceiveMulticast); 250 CSR_WRITE_4(l, STGE_TFDListPtrHi, 0); 251 CSR_WRITE_4(l, STGE_TFDListPtrLo, VTOPHYS(txd)); 252 CSR_WRITE_4(l, STGE_RFDListPtrHi, 0); 253 CSR_WRITE_4(l, STGE_RFDListPtrLo, VTOPHYS(rxd)); 254 CSR_WRITE_2(l, STGE_MaxFrameSize, FRAMESIZE); 255 CSR_WRITE_4(l, STGE_MACCtrl, 0); /* do IFSSelect(0) first */ 256 macctl = MC_StatisticsDisable | MC_TxEnable | MC_RxEnable; 257 258 if (PCI_REVISION(pcicfgread(tag, PCI_CLASS_REG)) >= 6) { 259 /* some workarounds for revisions >= 6 */ 260 CSR_WRITE_2(l, STGE_DebugCtrl, 261 CSR_READ_2(l, STGE_DebugCtrl) | 0x0200); 262 CSR_WRITE_2(l, STGE_DebugCtrl, 263 CSR_READ_2(l, STGE_DebugCtrl) | 0x0010); 264 CSR_WRITE_2(l, STGE_DebugCtrl, 265 CSR_READ_2(l, STGE_DebugCtrl) | 0x0020); 266 } 267 268 /* auto negotiation, set the current media */ 269 mii_dealan(l, 5); 270 271 reg = CSR_READ_1(l, STGE_PhyCtrl); 272 switch (PC_LinkSpeed(reg)) { 273 case PC_LinkSpeed_1000: 274 printf("1000Mbps"); 275 break; 276 case PC_LinkSpeed_100: 277 printf("100Mbps"); 278 break; 279 case PC_LinkSpeed_10: 280 printf("10Mbps"); 281 break; 282 } 283 if (reg & PC_PhyDuplexStatus) { 284 macctl |= MC_DuplexSelect; 285 printf("-FDX"); 286 } 287 printf("\n"); 288 CSR_WRITE_4(l, STGE_MACCtrl, macctl); 289 290 return l; 291 } 292 293 int 294 stg_send(void *dev, char *buf, unsigned len) 295 { 296 struct local *l = dev; 297 volatile struct desc *txd; 298 unsigned loop; 299 300 wbinv(buf, len); 301 txd = &l->txd[l->tx]; 302 txd->xd2 = htole64(VTOPHYS(buf) | ((uint64_t)len << 48)); 303 txd->xd1 = htole64(T1_NOALIGN | (1 << 24)); 304 wbinv(txd, sizeof(struct desc)); 305 CSR_WRITE_4(l, STGE_DMACtrl, DMAC_TxDMAPollNow); 306 loop = 100; 307 do { 308 if ((le64toh(txd->xd1) & T1_EMPTY) != 0) 309 goto done; 310 DELAY(10); 311 inv(txd, sizeof(struct desc)); 312 } while (--loop > 0); 313 printf("xmit failed\n"); 314 return -1; 315 done: 316 l->tx ^= 1; 317 return len; 318 } 319 320 int 321 stg_recv(void *dev, char *buf, unsigned maxlen, unsigned timo) 322 { 323 struct local *l = dev; 324 volatile struct desc *rxd; 325 uint32_t sts; 326 unsigned bound, len; 327 uint8_t *ptr; 328 329 bound = 1000 * timo; 330 again: 331 rxd = &l->rxd[l->rx]; 332 do { 333 inv(rxd, sizeof(struct desc)); 334 sts = (uint32_t)le64toh(rxd->xd1); 335 if ((sts & R1_DONE) != 0) 336 goto gotone; 337 DELAY(1000); /* 1 milli second */ 338 } while (--bound > 0); 339 errno = 0; 340 return -1; 341 gotone: 342 if ((sts & R1_ER_MASK) != 0) { 343 rxd->xd1 = 0; 344 wbinv(rxd, sizeof(struct desc)); 345 l->rx ^= 1; 346 goto again; 347 } 348 len = sts & R1_FL_MASK; 349 if (len > maxlen) 350 len = maxlen; 351 ptr = l->rxstore[l->rx]; 352 inv(ptr, len); 353 memcpy(buf, ptr, len); 354 rxd->xd1 = 0; 355 wbinv(rxd, sizeof(struct desc)); 356 l->rx ^= 1; 357 return len; 358 } 359 360 #define R0110 6 /* 0110b read op */ 361 #define W0101 5 /* 0101b write op */ 362 #define A10 2 /* 10b ack turn around */ 363 364 /* read the MII by bitbanging STGE_PhyCtrl */ 365 static int 366 mii_read(struct local *l, int phy, int reg) 367 { 368 unsigned data; 369 int i; 370 uint8_t v; 371 372 /* initiate read access */ 373 data = (R0110 << 10) | (phy << 5) | reg; 374 mii_bitbang_sync(l); 375 mii_bitbang_send(l, data, 14); /* 4OP + 5PHY + 5REG */ 376 377 /* switch direction to PHY->host */ 378 v = l->phyctrl_saved; 379 CSR_WRITE_1(l, STGE_PhyCtrl, v); 380 381 /* read data */ 382 data = 0; 383 for (i = 0; i < 18; i++) { /* 2TA + 16DATA */ 384 data <<= 1; 385 data |= !!(CSR_READ_1(l, STGE_PhyCtrl) & PC_MgmtData); 386 mii_bitbang_clk(l, v); 387 } 388 389 return data & 0xffff; 390 } 391 392 /* write the MII by bitbanging STGE_PhyCtrl */ 393 static void 394 mii_write(struct local *l, int phy, int reg, int val) 395 { 396 unsigned data; 397 398 data = (W0101 << 28) | (phy << 23) | (reg << 18) | (A10 << 16); 399 data |= val; 400 401 mii_bitbang_sync(l); 402 mii_bitbang_send(l, data, 32); /* 4OP + 5PHY + 5REG + 2TA + 16DATA */ 403 } 404 405 #define MII_BMCR 0x00 /* Basic mode control register (rw) */ 406 #define BMCR_RESET 0x8000 /* reset */ 407 #define BMCR_AUTOEN 0x1000 /* autonegotiation enable */ 408 #define BMCR_ISO 0x0400 /* isolate */ 409 #define BMCR_STARTNEG 0x0200 /* restart autonegotiation */ 410 #define MII_BMSR 0x01 /* Basic mode status register (ro) */ 411 #define BMSR_ACOMP 0x0020 /* Autonegotiation complete */ 412 #define BMSR_LINK 0x0004 /* Link status */ 413 #define MII_ANAR 0x04 /* Autonegotiation advertisement (rw) */ 414 #define ANAR_FC 0x0400 /* local device supports PAUSE */ 415 #define ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */ 416 #define ANAR_TX 0x0080 /* local device supports 100bTx */ 417 #define ANAR_10_FD 0x0040 /* local device supports 10bT FD */ 418 #define ANAR_10 0x0020 /* local device supports 10bT */ 419 #define ANAR_CSMA 0x0001 /* protocol selector CSMA/CD */ 420 #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */ 421 422 static void 423 mii_initphy(struct local *l) 424 { 425 int phy, ctl, sts, bound; 426 427 l->phyctrl_saved = CSR_READ_1(l, STGE_PhyCtrl) & 428 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 429 430 for (phy = 0; phy < 32; phy++) { 431 ctl = mii_read(l, phy, MII_BMCR); 432 sts = mii_read(l, phy, MII_BMSR); 433 if (ctl != 0xffff && sts != 0xffff && sts != 0) 434 goto found; 435 } 436 printf("MII: no PHY found\n"); 437 return; 438 439 found: 440 ctl = mii_read(l, phy, MII_BMCR); 441 mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET); 442 443 bound = 100; 444 do { 445 DELAY(10); 446 ctl = mii_read(l, phy, MII_BMCR); 447 if (ctl == 0xffff) { 448 printf("MII: PHY %d has died after reset\n", phy); 449 return; 450 } 451 } while (bound-- > 0 && (ctl & BMCR_RESET)); 452 if (bound == 0) 453 printf("PHY %d reset failed\n", phy); 454 455 ctl &= ~BMCR_ISO; 456 mii_write(l, phy, MII_BMCR, ctl); 457 sts = mii_read(l, phy, MII_BMSR) | 458 mii_read(l, phy, MII_BMSR); /* read twice */ 459 l->phy = phy; 460 l->bmsr = sts; 461 } 462 463 static void 464 mii_dealan(struct local *l, unsigned timo) 465 { 466 unsigned anar, bound; 467 468 anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA; 469 mii_write(l, l->phy, MII_ANAR, anar); 470 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 471 l->anlpar = 0; 472 bound = getsecs() + timo; 473 do { 474 l->bmsr = mii_read(l, l->phy, MII_BMSR) | 475 mii_read(l, l->phy, MII_BMSR); /* read twice */ 476 if ((l->bmsr & BMSR_LINK) && (l->bmsr & BMSR_ACOMP)) { 477 l->anlpar = mii_read(l, l->phy, MII_ANLPAR); 478 break; 479 } 480 DELAY(10 * 1000); 481 } while (getsecs() < bound); 482 } 483 484 static void 485 mii_bitbang_sync(struct local *l) 486 { 487 int i; 488 uint8_t v; 489 490 v = l->phyctrl_saved | PC_MgmtDir | PC_MgmtData; 491 CSR_WRITE_1(l, STGE_PhyCtrl, v); 492 DELAY(1); 493 for (i = 0; i < 32; i++) 494 mii_bitbang_clk(l, v); 495 } 496 497 static void 498 mii_bitbang_send(struct local *l, uint32_t data, int nbits) 499 { 500 uint32_t i; 501 uint8_t v; 502 503 v = l->phyctrl_saved | PC_MgmtDir; 504 CSR_WRITE_1(l, STGE_PhyCtrl, v); 505 DELAY(1); 506 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 507 if (data & i) 508 v |= PC_MgmtData; 509 else 510 v &= ~PC_MgmtData; 511 CSR_WRITE_1(l, STGE_PhyCtrl, v); 512 DELAY(1); 513 mii_bitbang_clk(l, v); 514 } 515 } 516 517 static void 518 mii_bitbang_clk(struct local *l, uint8_t v) 519 { 520 521 CSR_WRITE_1(l, STGE_PhyCtrl, v | PC_MgmtClk); 522 DELAY(1); 523 CSR_WRITE_1(l, STGE_PhyCtrl, v); 524 DELAY(1); 525 } 526 527 static int 528 eeprom_wait(struct local *l) 529 { 530 int i; 531 532 for (i = 0; i < 1000; i++) { 533 DELAY(1000); 534 if ((CSR_READ_2(l, STGE_EepromCtrl) & EC_EepromBusy) == 0) 535 return 0; 536 } 537 return 1; 538 } 539
Indexes created Tue Sep 30 11:09:46 GMT 2025