stg.c revision 1.4
1 /* $NetBSD: stg.c,v 1.4 2011/03/11 17:46:30 phx Exp $ */ 2 3 /*- 4 * Copyright (c) 2011 Frank Wille. 5 * All rights reserved. 6 * 7 * Written by Frank Wille for The NetBSD Project. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/param.h> 32 33 #include <netinet/in.h> 34 #include <netinet/in_systm.h> 35 36 #include <lib/libsa/stand.h> 37 #include <lib/libsa/net.h> 38 39 #include "globals.h" 40 41 #define CSR_WRITE_1(l, r, v) *(volatile uint8_t *)((l)->csr+(r)) = (v) 42 #define CSR_READ_1(l, r) *(volatile uint8_t *)((l)->csr+(r)) 43 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v)) 44 #define CSR_READ_2(l, r) in16rb((l)->csr+(r)) 45 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) 46 #define CSR_READ_4(l, r) in32rb((l)->csr+(r)) 47 #define VTOPHYS(va) (uint32_t)(va) 48 #define DEVTOV(pa) (uint32_t)(pa) 49 #define wbinv(adr, siz) _wbinv(VTOPHYS(adr), (uint32_t)(siz)) 50 #define inv(adr, siz) _inv(VTOPHYS(adr), (uint32_t)(siz)) 51 #define DELAY(n) delay(n) 52 #define ALLOC(T,A) (T *)allocaligned(sizeof(T),(A)) 53 54 struct desc { 55 uint64_t xd0, xd1, xd2, dummy; 56 }; 57 #define T1_EMPTY (1U << 31) /* no Tx frame available */ 58 #define T1_NOALIGN (3U << 16) /* allow any Tx alignment */ 59 #define T1_CNTSHIFT 24 /* Tx fragment count */ 60 #define T2_LENSHIFT 48 /* Tx fragment length */ 61 #define R1_DONE (1U << 31) /* desc has a Rx frame */ 62 #define R1_FL_MASK 0xffff /* Rx frame length */ 63 #define R1_ER_MASK 0x3f0000 /* Rx error indication */ 64 #define R2_LENSHIFT 48 /* Rx fragment length */ 65 66 #define STGE_DMACtrl 0x00 67 #define DMAC_RxDMAPollNow (1U << 4) 68 #define DMAC_TxDMAPollNow (1U << 12) 69 #define STGE_TFDListPtrLo 0x10 70 #define STGE_TFDListPtrHi 0x14 71 #define STGE_RFDListPtrLo 0x1c 72 #define STGE_RFDListPtrHi 0x20 73 #define STGE_DebugCtrl 0x2c 74 #define STGE_AsicCtrl 0x30 75 #define AC_PhyMedia (1U << 7) 76 #define AC_GlobalReset (1U << 16) 77 #define AC_RxReset (1U << 17) 78 #define AC_TxReset (1U << 18) 79 #define AC_DMA (1U << 19) 80 #define AC_FIFO (1U << 20) 81 #define AC_Network (1U << 21) 82 #define AC_Host (1U << 22) 83 #define AC_AutoInit (1U << 23) 84 #define AC_RstOut (1U << 24) 85 #define AC_ResetBusy (1U << 26) 86 #define STGE_EepromData 0x48 87 #define STGE_EepromCtrl 0x4a 88 #define EC_EepromAddress(x) ((x) & 0xff) 89 #define EC_EepromOpcode(x) ((x) << 8) 90 #define EC_OP_RR 2 91 #define EC_EepromBusy (1U << 15) 92 #define STGE_IntEnable 0x5c 93 #define STGE_MACCtrl 0x6c 94 #define MC_DuplexSelect (1U << 5) 95 #define MC_StatisticsDisable (1U << 22) 96 #define MC_TxEnable (1U << 24) 97 #define MC_RxEnable (1U << 27) 98 #define STGE_PhyCtrl 0x76 99 #define PC_MgmtClk (1U << 0) 100 #define PC_MgmtData (1U << 1) 101 #define PC_MgmtDir (1U << 2) 102 #define PC_PhyDuplexPolarity (1U << 3) 103 #define PC_PhyDuplexStatus (1U << 4) 104 #define PC_PhyLnkPolarity (1U << 5) 105 #define PC_LinkSpeed(x) (((x) >> 6) & 3) 106 #define PC_LinkSpeed_Down 0 107 #define PC_LinkSpeed_10 1 108 #define PC_LinkSpeed_100 2 109 #define PC_LinkSpeed_1000 3 110 #define STGE_StationAddress0 0x78 111 #define STGE_StationAddress1 0x7a 112 #define STGE_StationAddress2 0x7c 113 #define STGE_MaxFrameSize 0x84 114 #define STGE_ReceiveMode 0x88 115 #define RM_ReceiveUnicast (1U << 0) 116 #define RM_ReceiveMulticast (1U << 1) 117 #define RM_ReceiveBroadcast (1U << 2) 118 #define RM_ReceiveAllFrames (1U << 3) 119 #define RM_ReceiveMulticastHash (1U << 4) 120 #define RM_ReceiveIPMulticast (1U << 5) 121 122 #define STGE_EEPROM_SA0 0x10 123 124 #define FRAMESIZE 1536 125 126 struct local { 127 struct desc txd[2]; 128 struct desc rxd[2]; 129 uint8_t rxstore[2][FRAMESIZE]; 130 unsigned csr, rx, tx, phy; 131 uint16_t bmsr, anlpar; 132 uint8_t phyctrl_saved; 133 }; 134 135 static int mii_read(struct local *, int, int); 136 static void mii_write(struct local *, int, int, int); 137 static void mii_initphy(struct local *); 138 static void mii_dealan(struct local *, unsigned); 139 static void mii_bitbang_sync(struct local *); 140 static void mii_bitbang_send(struct local *, uint32_t, int); 141 static void mii_bitbang_clk(struct local *, uint8_t); 142 static int eeprom_wait(struct local *); 143 144 int 145 stg_match(unsigned tag, void *data) 146 { 147 unsigned v; 148 149 v = pcicfgread(tag, PCI_ID_REG); 150 switch (v) { 151 case PCI_DEVICE(0x13f0, 0x1023): /* ST1023, IP1000A */ 152 return 1; 153 } 154 return 0; 155 } 156 157 void * 158 stg_init(unsigned tag, void *data) 159 { 160 struct local *l; 161 struct desc *txd, *rxd; 162 uint8_t *en; 163 unsigned i; 164 uint32_t macctl, reg; 165 static uint8_t bad[2][6] = { 166 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, 167 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff } 168 }; 169 170 l = ALLOC(struct local, 32); /* desc alignment */ 171 memset(l, 0, sizeof(struct local)); 172 l->csr = DEVTOV(pcicfgread(tag, 0x14)); /* first try mem space */ 173 if (l->csr == 0) 174 l->csr = DEVTOV(PCI_XIOBASE + (pcicfgread(tag, 0x10) & ~01)); 175 176 /* reset the chip */ 177 reg = CSR_READ_4(l, STGE_AsicCtrl); 178 CSR_WRITE_4(l, STGE_AsicCtrl, reg | AC_GlobalReset | AC_RxReset | 179 AC_TxReset | AC_DMA | AC_FIFO | AC_Network | AC_Host | 180 AC_AutoInit | ((reg & AC_PhyMedia) ? AC_RstOut : 0)); 181 DELAY(50000); 182 for (i = 0; i < 1000; i++) { 183 DELAY(5000); 184 if ((CSR_READ_4(l, STGE_AsicCtrl) & AC_ResetBusy) == 0) 185 break; 186 } 187 if (i >= 1000) 188 printf("NIC reset failed to complete!\n"); 189 DELAY(1000); 190 191 mii_initphy(l); 192 193 /* read ethernet address */ 194 en = data; 195 for (i = 0; i < 6; i++) 196 en[i] = CSR_READ_1(l, STGE_StationAddress0 + i); 197 198 if (memcmp(en, bad[0], 6) == 0 || memcmp(en, bad[1], 6) == 0) { 199 uint16_t addr[3]; 200 201 for (i = 0; i < 3; i++) { 202 if (eeprom_wait(l) != 0) 203 printf("NIC: serial EEPROM is not ready!\n"); 204 CSR_WRITE_2(l, STGE_EepromCtrl, 205 EC_EepromAddress(STGE_EEPROM_SA0 + i) | 206 EC_EepromOpcode(EC_OP_RR)); 207 if (eeprom_wait(l) != 0) 208 printf("NIC: serial EEPROM read time out!\n"); 209 addr[i] = le16toh(CSR_READ_2(l, STGE_EepromData)); 210 } 211 (void)memcpy(en, addr, 6); 212 213 /* try to read MAC from Flash, when EEPROM is empty/missing */ 214 if (memcmp(en, bad[0], 6) == 0 || memcmp(en, bad[1], 6) == 0) 215 read_mac_from_flash(en); 216 217 /* set the station address now */ 218 for (i = 0; i < 6; i++) 219 CSR_WRITE_1(l, STGE_StationAddress0 + i, en[i]); 220 } 221 222 printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", 223 en[0], en[1], en[2], en[3], en[4], en[5]); 224 225 DPRINTF(("PHY %d (%04x.%04x)\n", l->phy, 226 mii_read(l, l->phy, 2), mii_read(l, l->phy, 3))); 227 228 /* setup descriptors */ 229 txd = &l->txd[0]; 230 txd[0].xd0 = htole64(VTOPHYS(&txd[1])); 231 txd[0].xd1 = htole64(T1_EMPTY); 232 txd[1].xd0 = htole64(VTOPHYS(&txd[0])); 233 txd[1].xd1 = htole64(T1_EMPTY); 234 rxd = &l->rxd[0]; 235 rxd[0].xd0 = htole64(VTOPHYS(&rxd[1])); 236 rxd[0].xd2 = htole64(VTOPHYS(l->rxstore[0]) | 237 ((uint64_t)FRAMESIZE << 48)); 238 rxd[1].xd0 = htole64(VTOPHYS(&rxd[0])); 239 rxd[1].xd2 = htole64(VTOPHYS(l->rxstore[1]) | 240 ((uint64_t)FRAMESIZE << 48)); 241 wbinv(l, sizeof(struct local)); 242 243 CSR_WRITE_2(l, STGE_IntEnable, 0); 244 CSR_WRITE_2(l, STGE_ReceiveMode, RM_ReceiveUnicast | 245 RM_ReceiveBroadcast | RM_ReceiveAllFrames | RM_ReceiveMulticast); 246 CSR_WRITE_4(l, STGE_TFDListPtrHi, 0); 247 CSR_WRITE_4(l, STGE_TFDListPtrLo, VTOPHYS(txd)); 248 CSR_WRITE_4(l, STGE_RFDListPtrHi, 0); 249 CSR_WRITE_4(l, STGE_RFDListPtrLo, VTOPHYS(rxd)); 250 CSR_WRITE_2(l, STGE_MaxFrameSize, FRAMESIZE); 251 CSR_WRITE_4(l, STGE_MACCtrl, 0); /* do IFSSelect(0) first */ 252 macctl = MC_StatisticsDisable | MC_TxEnable | MC_RxEnable; 253 254 if (PCI_REVISION(pcicfgread(tag, PCI_CLASS_REG)) >= 6) { 255 /* some workarounds for revisions >= 6 */ 256 CSR_WRITE_2(l, STGE_DebugCtrl, 257 CSR_READ_2(l, STGE_DebugCtrl) | 0x0200); 258 CSR_WRITE_2(l, STGE_DebugCtrl, 259 CSR_READ_2(l, STGE_DebugCtrl) | 0x0010); 260 CSR_WRITE_2(l, STGE_DebugCtrl, 261 CSR_READ_2(l, STGE_DebugCtrl) | 0x0020); 262 } 263 264 /* auto negotiation, set the current media */ 265 mii_dealan(l, 5); 266 267 reg = CSR_READ_1(l, STGE_PhyCtrl); 268 switch (PC_LinkSpeed(reg)) { 269 case PC_LinkSpeed_1000: 270 printf("1000Mbps"); 271 break; 272 case PC_LinkSpeed_100: 273 printf("100Mbps"); 274 break; 275 case PC_LinkSpeed_10: 276 printf("10Mbps"); 277 break; 278 } 279 if (reg & PC_PhyDuplexStatus) { 280 macctl |= MC_DuplexSelect; 281 printf("-FDX"); 282 } 283 printf("\n"); 284 CSR_WRITE_4(l, STGE_MACCtrl, macctl); 285 286 return l; 287 } 288 289 int 290 stg_send(void *dev, char *buf, unsigned len) 291 { 292 struct local *l = dev; 293 volatile struct desc *txd; 294 unsigned loop; 295 296 wbinv(buf, len); 297 txd = &l->txd[l->tx]; 298 txd->xd2 = htole64(VTOPHYS(buf) | ((uint64_t)len << 48)); 299 txd->xd1 = htole64(T1_NOALIGN | (1 << 24)); 300 wbinv(txd, sizeof(struct desc)); 301 CSR_WRITE_4(l, STGE_DMACtrl, DMAC_TxDMAPollNow); 302 loop = 100; 303 do { 304 if ((le64toh(txd->xd1) & T1_EMPTY) != 0) 305 goto done; 306 DELAY(10); 307 inv(txd, sizeof(struct desc)); 308 } while (--loop > 0); 309 printf("xmit failed\n"); 310 return -1; 311 done: 312 l->tx ^= 1; 313 return len; 314 } 315 316 int 317 stg_recv(void *dev, char *buf, unsigned maxlen, unsigned timo) 318 { 319 struct local *l = dev; 320 volatile struct desc *rxd; 321 uint32_t sts; 322 unsigned bound, len; 323 uint8_t *ptr; 324 325 bound = 1000 * timo; 326 again: 327 rxd = &l->rxd[l->rx]; 328 do { 329 inv(rxd, sizeof(struct desc)); 330 sts = (uint32_t)le64toh(rxd->xd1); 331 if ((sts & R1_DONE) != 0) 332 goto gotone; 333 DELAY(1000); /* 1 milli second */ 334 } while (--bound > 0); 335 errno = 0; 336 return -1; 337 gotone: 338 if ((sts & R1_ER_MASK) != 0) { 339 rxd->xd1 = 0; 340 wbinv(rxd, sizeof(struct desc)); 341 l->rx ^= 1; 342 goto again; 343 } 344 len = sts & R1_FL_MASK; 345 if (len > maxlen) 346 len = maxlen; 347 ptr = l->rxstore[l->rx]; 348 inv(ptr, len); 349 memcpy(buf, ptr, len); 350 rxd->xd1 = 0; 351 wbinv(rxd, sizeof(struct desc)); 352 l->rx ^= 1; 353 return len; 354 } 355 356 #define R0110 6 /* 0110b read op */ 357 #define W0101 5 /* 0101b write op */ 358 #define A10 2 /* 10b ack turn around */ 359 360 /* read the MII by bitbanging STGE_PhyCtrl */ 361 static int 362 mii_read(struct local *l, int phy, int reg) 363 { 364 unsigned data; 365 int i; 366 uint8_t v; 367 368 /* initiate read access */ 369 data = (R0110 << 10) | (phy << 5) | reg; 370 mii_bitbang_sync(l); 371 mii_bitbang_send(l, data, 14); /* 4OP + 5PHY + 5REG */ 372 373 /* switch direction to PHY->host */ 374 v = l->phyctrl_saved; 375 CSR_WRITE_1(l, STGE_PhyCtrl, v); 376 377 /* read data */ 378 data = 0; 379 for (i = 0; i < 18; i++) { /* 2TA + 16DATA */ 380 data <<= 1; 381 data |= !!(CSR_READ_1(l, STGE_PhyCtrl) & PC_MgmtData); 382 mii_bitbang_clk(l, v); 383 } 384 385 return data & 0xffff; 386 } 387 388 /* write the MII by bitbanging STGE_PhyCtrl */ 389 static void 390 mii_write(struct local *l, int phy, int reg, int val) 391 { 392 unsigned data; 393 394 data = (W0101 << 28) | (phy << 23) | (reg << 18) | (A10 << 16); 395 data |= val; 396 397 mii_bitbang_sync(l); 398 mii_bitbang_send(l, data, 32); /* 4OP + 5PHY + 5REG + 2TA + 16DATA */ 399 } 400 401 #define MII_BMCR 0x00 /* Basic mode control register (rw) */ 402 #define BMCR_RESET 0x8000 /* reset */ 403 #define BMCR_AUTOEN 0x1000 /* autonegotiation enable */ 404 #define BMCR_ISO 0x0400 /* isolate */ 405 #define BMCR_STARTNEG 0x0200 /* restart autonegotiation */ 406 #define MII_BMSR 0x01 /* Basic mode status register (ro) */ 407 #define BMSR_ACOMP 0x0020 /* Autonegotiation complete */ 408 #define BMSR_LINK 0x0004 /* Link status */ 409 #define MII_ANAR 0x04 /* Autonegotiation advertisement (rw) */ 410 #define ANAR_FC 0x0400 /* local device supports PAUSE */ 411 #define ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */ 412 #define ANAR_TX 0x0080 /* local device supports 100bTx */ 413 #define ANAR_10_FD 0x0040 /* local device supports 10bT FD */ 414 #define ANAR_10 0x0020 /* local device supports 10bT */ 415 #define ANAR_CSMA 0x0001 /* protocol selector CSMA/CD */ 416 #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */ 417 418 static void 419 mii_initphy(struct local *l) 420 { 421 int phy, ctl, sts, bound; 422 423 l->phyctrl_saved = CSR_READ_1(l, STGE_PhyCtrl) & 424 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity); 425 426 for (phy = 0; phy < 32; phy++) { 427 ctl = mii_read(l, phy, MII_BMCR); 428 sts = mii_read(l, phy, MII_BMSR); 429 if (ctl != 0xffff && sts != 0xffff && sts != 0) 430 goto found; 431 } 432 printf("MII: no PHY found\n"); 433 return; 434 435 found: 436 ctl = mii_read(l, phy, MII_BMCR); 437 mii_write(l, phy, MII_BMCR, ctl | BMCR_RESET); 438 439 bound = 100; 440 do { 441 DELAY(10); 442 ctl = mii_read(l, phy, MII_BMCR); 443 if (ctl == 0xffff) { 444 printf("MII: PHY %d has died after reset\n", phy); 445 return; 446 } 447 } while (bound-- > 0 && (ctl & BMCR_RESET)); 448 if (bound == 0) 449 printf("PHY %d reset failed\n", phy); 450 451 ctl &= ~BMCR_ISO; 452 mii_write(l, phy, MII_BMCR, ctl); 453 sts = mii_read(l, phy, MII_BMSR) | 454 mii_read(l, phy, MII_BMSR); /* read twice */ 455 l->phy = phy; 456 l->bmsr = sts; 457 } 458 459 static void 460 mii_dealan(struct local *l, unsigned timo) 461 { 462 unsigned anar, bound; 463 464 anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA; 465 mii_write(l, l->phy, MII_ANAR, anar); 466 mii_write(l, l->phy, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 467 l->anlpar = 0; 468 bound = getsecs() + timo; 469 do { 470 l->bmsr = mii_read(l, l->phy, MII_BMSR) | 471 mii_read(l, l->phy, MII_BMSR); /* read twice */ 472 if ((l->bmsr & BMSR_LINK) && (l->bmsr & BMSR_ACOMP)) { 473 l->anlpar = mii_read(l, l->phy, MII_ANLPAR); 474 break; 475 } 476 DELAY(10 * 1000); 477 } while (getsecs() < bound); 478 } 479 480 static void 481 mii_bitbang_sync(struct local *l) 482 { 483 int i; 484 uint8_t v; 485 486 v = l->phyctrl_saved | PC_MgmtDir | PC_MgmtData; 487 CSR_WRITE_1(l, STGE_PhyCtrl, v); 488 DELAY(1); 489 for (i = 0; i < 32; i++) 490 mii_bitbang_clk(l, v); 491 } 492 493 static void 494 mii_bitbang_send(struct local *l, uint32_t data, int nbits) 495 { 496 uint32_t i; 497 uint8_t v; 498 499 v = l->phyctrl_saved | PC_MgmtDir; 500 CSR_WRITE_1(l, STGE_PhyCtrl, v); 501 DELAY(1); 502 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 503 if (data & i) 504 v |= PC_MgmtData; 505 else 506 v &= ~PC_MgmtData; 507 CSR_WRITE_1(l, STGE_PhyCtrl, v); 508 DELAY(1); 509 mii_bitbang_clk(l, v); 510 } 511 } 512 513 static void 514 mii_bitbang_clk(struct local *l, uint8_t v) 515 { 516 517 CSR_WRITE_1(l, STGE_PhyCtrl, v | PC_MgmtClk); 518 DELAY(1); 519 CSR_WRITE_1(l, STGE_PhyCtrl, v); 520 DELAY(1); 521 } 522 523 static int 524 eeprom_wait(struct local *l) 525 { 526 int i; 527 528 for (i = 0; i < 1000; i++) { 529 DELAY(1000); 530 if ((CSR_READ_2(l, STGE_EepromCtrl) & EC_EepromBusy) == 0) 531 return 0; 532 } 533 return 1; 534 } 535
Indexes created Tue Sep 30 17:09:57 GMT 2025