int.c revision 1.1
1 /* $NetBSD: int.c,v 1.1 2004/01/19 00:12:31 sekiya Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Christopher SEKIYA 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * INT/INT2/INT3 interrupt controller (used in ip1x and ip2x-class machines) 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: int.c,v 1.1 2004/01/19 00:12:31 sekiya Exp $"); 36 37 #include "opt_cputype.h" 38 #include "opt_machtypes.h" 39 40 #include <sys/param.h> 41 #include <sys/proc.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 46 #include <dev/ic/i8253reg.h> 47 #include <machine/sysconf.h> 48 #include <machine/machtype.h> 49 #include <machine/bus.h> 50 #include <mips/locore.h> 51 52 #include <mips/cache.h> 53 54 #include <sgimips/dev/int2reg.h> 55 56 static bus_space_handle_t ioh; 57 static bus_space_tag_t iot; 58 59 struct int_softc { 60 struct device sc_dev; 61 }; 62 63 64 static int int_match(struct device *, struct cfdata *, void *); 65 static void int_attach(struct device *, struct device *, void *); 66 void int_local0_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 67 void int_local1_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 68 int int_mappable_intr(void *); 69 void int_intr(u_int, u_int, u_int, u_int); 70 void *int_intr_establish(int, int, int (*)(void *), void *); 71 unsigned long int_cal_timer(void); 72 void int_8254_cal(void); 73 74 CFATTACH_DECL(int, sizeof(struct int_softc), 75 int_match, int_attach, NULL, NULL); 76 77 static int 78 int_match(struct device *parent, struct cfdata *match, void *aux) 79 { 80 if ( (mach_type == MACH_SGI_IP12) || (mach_type == MACH_SGI_IP20) || 81 (mach_type == MACH_SGI_IP22) ) 82 return 1; 83 84 return 0; 85 } 86 87 static void 88 int_attach(struct device *parent, struct device *self, void *aux) 89 { 90 int i; 91 unsigned long cps; 92 unsigned long ctrdiff[3]; 93 u_int32_t address; 94 95 if (mach_type == MACH_SGI_IP12) 96 address = INT_IP12; 97 else if (mach_type == MACH_SGI_IP20) 98 address = INT_IP20; 99 else if (mach_type == MACH_SGI_IP22) { 100 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 101 address = INT_IP22; 102 else 103 address = INT_IP24; 104 } 105 else 106 panic("\nint0: passed match, but failed attach?"); 107 108 printf(" addr 0x%x", address); 109 110 bus_space_map(iot, address, 0, 0, &ioh); 111 iot = SGIMIPS_BUS_SPACE_NORMAL; 112 113 /* Clean out interrupt masks */ 114 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, 0); 115 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, 0); 116 bus_space_write_4(iot, ioh, INT2_MAP_MASK0, 0); 117 bus_space_write_4(iot, ioh, INT2_MAP_MASK1, 0); 118 119 /* Reset timer interrupts */ 120 bus_space_write_4(iot, ioh, INT2_TIMER_CLEAR, 0x03); 121 122 switch (mach_type) { 123 case MACH_SGI_IP12: 124 platform.intr1 = int_local0_intr; 125 platform.intr2 = int_local1_intr; 126 int_8254_cal(); 127 break; 128 case MACH_SGI_IP20: 129 case MACH_SGI_IP22: 130 platform.intr0 = int_local0_intr; 131 platform.intr1 = int_local1_intr; 132 133 /* calibrate timer */ 134 int_cal_timer(); 135 136 cps = 0; 137 for (i = 0; i < sizeof(ctrdiff) / sizeof(ctrdiff[0]); i++) { 138 do { 139 ctrdiff[i] = int_cal_timer(); 140 } while (ctrdiff[i] == 0); 141 142 cps += ctrdiff[i]; 143 } 144 145 cps = cps / (sizeof(ctrdiff) / sizeof(ctrdiff[0])); 146 147 printf(": bus %luMHz, CPU %luMHz", cps / 10000, cps / 5000); 148 149 /* R4k/R4400/R4600/R5k count at half CPU frequency */ 150 curcpu()->ci_cpu_freq = 2 * cps * hz; 151 152 break; 153 default: 154 panic("int0: unsupported machine type %i\n", mach_type); 155 break; 156 } 157 158 printf("\n"); 159 160 curcpu()->ci_cycles_per_hz = curcpu()->ci_cpu_freq / (2 * hz); 161 curcpu()->ci_divisor_delay = curcpu()->ci_cpu_freq / (2 * 1000000); 162 MIPS_SET_CI_RECIPRICAL(curcpu()); 163 164 if (mach_type == MACH_SGI_IP22) { 165 /* Wire interrupts 7, 11 to mappable interrupt 0,1 handlers */ 166 intrtab[7].ih_fun = int_mappable_intr; 167 intrtab[7].ih_arg = (void*) 0; 168 169 intrtab[11].ih_fun = int_mappable_intr; 170 intrtab[11].ih_arg = (void*) 1; 171 } 172 173 platform.intr_establish = int_intr_establish; 174 } 175 176 int 177 int_mappable_intr(void *arg) 178 { 179 int i; 180 int ret; 181 int intnum; 182 u_int32_t mstat; 183 u_int32_t mmask; 184 int which = (int)arg; 185 186 ret = 0; 187 mstat = bus_space_read_4(iot, ioh, INT2_MAP_STATUS); 188 mmask = bus_space_read_4(iot, ioh, INT2_MAP_MASK0 + (which << 2)); 189 190 mstat &= mmask; 191 192 for (i = 0; i < 8; i++) { 193 intnum = i + 16 + (which << 3); 194 if (mstat & (1 << i)) { 195 if (intrtab[intnum].ih_fun != NULL) 196 ret |= (intrtab[intnum].ih_fun) 197 (intrtab[intnum].ih_arg); 198 else 199 printf("int0: unexpected mapped interrupt %d\n", 200 intnum); 201 } 202 } 203 204 return ret; 205 } 206 207 void 208 int_local0_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending) 209 { 210 int i; 211 int ret; 212 u_int32_t l0stat; 213 u_int32_t l0mask; 214 215 ret = 0; 216 l0stat = bus_space_read_4(iot, ioh, INT2_LOCAL0_STATUS); 217 l0mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 218 219 l0stat &= l0mask; 220 221 for (i = 0; i < 8; i++) { 222 if (l0stat & (1 << i)) { 223 if (intrtab[i].ih_fun != NULL) 224 ret |= (intrtab[i].ih_fun)(intrtab[i].ih_arg); 225 else 226 printf("int0: unexpected local0 interrupt %d\n", i); 227 } 228 } 229 } 230 231 void 232 int_local1_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending) 233 { 234 int i; 235 int ret; 236 u_int32_t l1stat; 237 u_int32_t l1mask; 238 239 l1stat = bus_space_read_4(iot, ioh, INT2_LOCAL1_STATUS); 240 l1mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 241 242 l1stat &= l1mask; 243 244 ret = 0; 245 for (i = 0; i < 8; i++) { 246 if (l1stat & (1 << i)) { 247 if (intrtab[8 + i].ih_fun != NULL) 248 ret |= (intrtab[8 + i].ih_fun) 249 (intrtab[8 + i].ih_arg); 250 else 251 printf("int0: unexpected local1 interrupt %x\n", 252 8 + i ); 253 } 254 } 255 } 256 257 void * 258 int_intr_establish(int level, int ipl, int (*handler) (void *), void *arg) 259 { 260 u_int32_t mask; 261 262 if (level < 0 || level >= NINTR) 263 panic("invalid interrupt level"); 264 265 if (intrtab[level].ih_fun != NULL) 266 { 267 printf("int0: cannot share interrupts yet.\n"); 268 return (void *)NULL; 269 } 270 271 intrtab[level].ih_fun = handler; 272 intrtab[level].ih_arg = arg; 273 274 if (level < 8) { 275 mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 276 mask |= (1 << level); 277 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, mask); 278 } else if (level < 16) { 279 mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 280 mask |= (1 << (level - 8)); 281 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, mask); 282 } else if (level < 24) { 283 /* Map0 interrupt maps to l0 bit 7, so turn that on too */ 284 mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 285 mask |= (1 << 7); 286 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, mask); 287 288 mask = bus_space_read_4(iot, ioh, INT2_MAP_MASK0); 289 mask |= (1 << (level - 16)); 290 bus_space_write_4(iot, ioh, INT2_MAP_MASK0, mask); 291 } else { 292 /* Map1 interrupt maps to l1 bit 3, so turn that on too */ 293 mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 294 mask |= (1 << 3); 295 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, mask); 296 297 mask = bus_space_read_4(iot, ioh, INT2_MAP_MASK1); 298 mask |= (1 << (level - 24)); 299 bus_space_write_4(iot, ioh, INT2_MAP_MASK1, mask); 300 } 301 302 return (void *)NULL; 303 } 304 305 unsigned long 306 int_cal_timer(void) 307 { 308 int s; 309 int roundtime; 310 int sampletime; 311 int startmsb, lsb, msb; 312 unsigned long startctr, endctr; 313 314 /* 315 * NOTE: HZ must be greater than 15 for this to work, as otherwise 316 * we'll overflow the counter. We round the answer to hearest 1 317 * MHz of the master (2x) clock. 318 */ 319 roundtime = (1000000 / hz) / 2; 320 sampletime = (1000000 / hz) + 0xff; 321 startmsb = (sampletime >> 8); 322 323 s = splhigh(); 324 325 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, 326 ( TIMER_SEL2 | TIMER_16BIT | TIMER_RATEGEN) ); 327 bus_space_write_4(iot, ioh, INT2_TIMER_2, (sampletime & 0xff)); 328 bus_space_write_4(iot, ioh, INT2_TIMER_2, (sampletime >> 8)); 329 330 startctr = mips3_cp0_count_read(); 331 332 /* Wait for the MSB to count down to zero */ 333 do { 334 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, TIMER_SEL2 ); 335 lsb = bus_space_read_4(iot, ioh, INT2_TIMER_2) & 0xff; 336 msb = bus_space_read_4(iot, ioh, INT2_TIMER_2) & 0xff; 337 338 endctr = mips3_cp0_count_read(); 339 } while (msb); 340 341 /* Turn off timer */ 342 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, 343 ( TIMER_SEL2 | TIMER_16BIT | TIMER_SWSTROBE) ); 344 345 splx(s); 346 347 return (endctr - startctr) / roundtime * roundtime; 348 } 349 350 void 351 int_8254_cal(void) 352 { 353 int s; 354 355 s = splhigh(); 356 357 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 15, 358 TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT); 359 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 3, (20000 / hz) % 256); 360 wbflush(); 361 delay(4); 362 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 3, (20000 / hz) / 256); 363 364 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 15, 365 TIMER_SEL2|TIMER_RATEGEN|TIMER_16BIT); 366 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 11, 50); 367 wbflush(); 368 delay(4); 369 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 11, 0); 370 splx(s); 371 } 372
Indexes created Mon Sep 22 21:09:42 GMT 2025