int.c revision 1.15
1 /* $NetBSD: int.c,v 1.15 2006/12/29 07:00:11 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Christopher SEKIYA 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * INT/INT2/INT3 interrupt controller (used in Indy's, Indigo's, etc..) 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: int.c,v 1.15 2006/12/29 07:00:11 rumble Exp $"); 36 37 #include "opt_cputype.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/systm.h> 42 #include <sys/timetc.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <dev/ic/i8253reg.h> 48 #include <machine/sysconf.h> 49 #include <machine/machtype.h> 50 #include <machine/bus.h> 51 #include <mips/locore.h> 52 53 #include <mips/cache.h> 54 55 #include <sgimips/dev/int2reg.h> 56 #include <sgimips/dev/int2var.h> 57 58 static bus_space_handle_t ioh; 59 static bus_space_tag_t iot; 60 61 struct int_softc { 62 struct device sc_dev; 63 }; 64 65 66 static int int_match(struct device *, struct cfdata *, void *); 67 static void int_attach(struct device *, struct device *, void *); 68 static void int_local0_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 69 static void int_local1_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 70 static int int_mappable_intr(void *); 71 static void *int_intr_establish(int, int, int (*)(void *), void *); 72 static void int_8254_cal(void); 73 static u_int int_8254_get_timecount(struct timecounter *); 74 static void int_8254_intr0(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 75 static void int_8254_intr1(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 76 77 #ifdef MIPS3 78 static u_long int_cal_timer(void); 79 #endif 80 81 static struct timecounter int_8254_timecounter = { 82 int_8254_get_timecount, /* get_timecount */ 83 0, /* no poll_pps */ 84 ~0u, /* counter_mask */ 85 500000, /* frequency */ 86 "int i8254", /* name */ 87 100, /* quality */ 88 NULL, /* prev */ 89 NULL, /* next */ 90 }; 91 92 static u_long int_8254_tc_count; 93 94 CFATTACH_DECL(int, sizeof(struct int_softc), 95 int_match, int_attach, NULL, NULL); 96 97 static int 98 int_match(struct device *parent, struct cfdata *match, void *aux) 99 { 100 101 if ((mach_type == MACH_SGI_IP12) || (mach_type == MACH_SGI_IP20) || 102 (mach_type == MACH_SGI_IP22) ) 103 return 1; 104 105 return 0; 106 } 107 108 static void 109 int_attach(struct device *parent, struct device *self, void *aux) 110 { 111 u_int32_t address; 112 113 if (mach_type == MACH_SGI_IP12) 114 address = INT_IP12; 115 else if (mach_type == MACH_SGI_IP20) 116 address = INT_IP20; 117 else if (mach_type == MACH_SGI_IP22) { 118 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 119 address = INT_IP22; 120 else 121 address = INT_IP24; 122 } else 123 panic("\nint0: passed match, but failed attach?"); 124 125 printf(" addr 0x%x", address); 126 127 bus_space_map(iot, address, 0, 0, &ioh); 128 iot = SGIMIPS_BUS_SPACE_NORMAL; 129 130 /* Clean out interrupt masks */ 131 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, 0); 132 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, 0); 133 bus_space_write_4(iot, ioh, INT2_MAP_MASK0, 0); 134 bus_space_write_4(iot, ioh, INT2_MAP_MASK1, 0); 135 136 /* Reset timer interrupts */ 137 bus_space_write_4(iot, ioh, INT2_TIMER_CLEAR, 0x03); 138 139 switch (mach_type) { 140 case MACH_SGI_IP12: 141 platform.intr1 = int_local0_intr; 142 platform.intr2 = int_local1_intr; 143 platform.intr3 = int_8254_intr0; 144 platform.intr4 = int_8254_intr1; 145 int_8254_cal(); 146 tc_init(&int_8254_timecounter); 147 break; 148 #ifdef MIPS3 149 case MACH_SGI_IP20: 150 case MACH_SGI_IP22: 151 { 152 int i; 153 unsigned long cps; 154 unsigned long ctrdiff[3]; 155 156 platform.intr0 = int_local0_intr; 157 platform.intr1 = int_local1_intr; 158 159 /* calibrate timer */ 160 int_cal_timer(); 161 162 cps = 0; 163 for (i = 0; 164 i < sizeof(ctrdiff) / sizeof(ctrdiff[0]); i++) { 165 do { 166 ctrdiff[i] = int_cal_timer(); 167 } while (ctrdiff[i] == 0); 168 169 cps += ctrdiff[i]; 170 } 171 172 cps = cps / (sizeof(ctrdiff) / sizeof(ctrdiff[0])); 173 174 printf(": bus %luMHz, CPU %luMHz", 175 cps / 10000, cps / 5000); 176 177 /* R4k/R4400/R4600/R5k count at half CPU frequency */ 178 curcpu()->ci_cpu_freq = 2 * cps * hz; 179 } 180 #endif /* MIPS3 */ 181 182 break; 183 default: 184 panic("int0: unsupported machine type %i\n", mach_type); 185 break; 186 } 187 188 printf("\n"); 189 190 curcpu()->ci_cycles_per_hz = curcpu()->ci_cpu_freq / (2 * hz); 191 curcpu()->ci_divisor_delay = curcpu()->ci_cpu_freq / (2 * 1000000); 192 MIPS_SET_CI_RECIPRICAL(curcpu()); 193 194 if (mach_type == MACH_SGI_IP22) { 195 /* Wire interrupts 7, 11 to mappable interrupt 0,1 handlers */ 196 intrtab[7].ih_fun = int_mappable_intr; 197 intrtab[7].ih_arg = (void*) 0; 198 199 intrtab[11].ih_fun = int_mappable_intr; 200 intrtab[11].ih_arg = (void*) 1; 201 } 202 203 platform.intr_establish = int_intr_establish; 204 } 205 206 int 207 int_mappable_intr(void *arg) 208 { 209 int i; 210 int ret; 211 int intnum; 212 u_int32_t mstat; 213 u_int32_t mmask; 214 int which = (int)arg; 215 struct sgimips_intrhand *ih; 216 217 ret = 0; 218 mstat = bus_space_read_4(iot, ioh, INT2_MAP_STATUS); 219 mmask = bus_space_read_4(iot, ioh, INT2_MAP_MASK0 + (which << 2)); 220 221 mstat &= mmask; 222 223 for (i = 0; i < 8; i++) { 224 intnum = i + 16 + (which << 3); 225 if (mstat & (1 << i)) { 226 for (ih = &intrtab[intnum]; ih != NULL; 227 ih = ih->ih_next) { 228 if (ih->ih_fun != NULL) 229 ret |= (ih->ih_fun)(ih->ih_arg); 230 else 231 printf("int0: unexpected mapped " 232 "interrupt %d\n", intnum); 233 } 234 } 235 } 236 237 return ret; 238 } 239 240 void 241 int_local0_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, 242 u_int32_t ipending) 243 { 244 int i; 245 u_int32_t l0stat; 246 u_int32_t l0mask; 247 struct sgimips_intrhand *ih; 248 249 l0stat = bus_space_read_4(iot, ioh, INT2_LOCAL0_STATUS); 250 l0mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 251 252 l0stat &= l0mask; 253 254 for (i = 0; i < 8; i++) { 255 if (l0stat & (1 << i)) { 256 for (ih = &intrtab[i]; ih != NULL; ih = ih->ih_next) { 257 if (ih->ih_fun != NULL) 258 (ih->ih_fun)(ih->ih_arg); 259 else 260 printf("int0: unexpected local0 " 261 "interrupt %d\n", i); 262 } 263 } 264 } 265 } 266 267 void 268 int_local1_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, 269 u_int32_t ipending) 270 { 271 int i; 272 u_int32_t l1stat; 273 u_int32_t l1mask; 274 struct sgimips_intrhand *ih; 275 276 l1stat = bus_space_read_4(iot, ioh, INT2_LOCAL1_STATUS); 277 l1mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 278 279 l1stat &= l1mask; 280 281 for (i = 0; i < 8; i++) { 282 if (l1stat & (1 << i)) { 283 for (ih = &intrtab[8+i]; ih != NULL; ih = ih->ih_next) { 284 if (ih->ih_fun != NULL) 285 (ih->ih_fun)(ih->ih_arg); 286 else 287 printf("int0: unexpected local1 " 288 " interrupt %x\n", 8 + i); 289 } 290 } 291 } 292 } 293 294 void * 295 int_intr_establish(int level, int ipl, int (*handler) (void *), void *arg) 296 { 297 u_int32_t mask; 298 299 if (level < 0 || level >= NINTR) 300 panic("invalid interrupt level"); 301 302 if (intrtab[level].ih_fun == NULL) { 303 intrtab[level].ih_fun = handler; 304 intrtab[level].ih_arg = arg; 305 intrtab[level].ih_next = NULL; 306 } else { 307 struct sgimips_intrhand *n, *ih = malloc(sizeof *ih, 308 M_DEVBUF, M_NOWAIT); 309 310 if (ih == NULL) { 311 printf("int_intr_establish: can't allocate handler\n"); 312 return (void *)NULL; 313 } 314 315 ih->ih_fun = handler; 316 ih->ih_arg = arg; 317 ih->ih_next = NULL; 318 319 for (n = &intrtab[level]; n->ih_next != NULL; n = n->ih_next) 320 ; 321 322 n->ih_next = ih; 323 324 return (void *)NULL; /* vector already set */ 325 } 326 327 328 if (level < 8) { 329 mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 330 mask |= (1 << level); 331 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, mask); 332 } else if (level < 16) { 333 mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 334 mask |= (1 << (level - 8)); 335 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, mask); 336 } else if (level < 24) { 337 /* Map0 interrupt maps to l0 bit 7, so turn that on too */ 338 mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 339 mask |= (1 << 7); 340 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, mask); 341 342 mask = bus_space_read_4(iot, ioh, INT2_MAP_MASK0); 343 mask |= (1 << (level - 16)); 344 bus_space_write_4(iot, ioh, INT2_MAP_MASK0, mask); 345 } else { 346 /* Map1 interrupt maps to l1 bit 3, so turn that on too */ 347 mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 348 mask |= (1 << 3); 349 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, mask); 350 351 mask = bus_space_read_4(iot, ioh, INT2_MAP_MASK1); 352 mask |= (1 << (level - 24)); 353 bus_space_write_4(iot, ioh, INT2_MAP_MASK1, mask); 354 } 355 356 return (void *)NULL; 357 } 358 359 #ifdef MIPS3 360 static u_long 361 int_cal_timer(void) 362 { 363 int s; 364 int roundtime; 365 int sampletime; 366 int startmsb, lsb, msb; 367 unsigned long startctr, endctr; 368 369 /* 370 * NOTE: HZ must be greater than 15 for this to work, as otherwise 371 * we'll overflow the counter. We round the answer to hearest 1 372 * MHz of the master (2x) clock. 373 */ 374 roundtime = (1000000 / hz) / 2; 375 sampletime = (1000000 / hz) + 0xff; 376 startmsb = (sampletime >> 8); 377 378 s = splhigh(); 379 380 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, 381 ( TIMER_SEL2 | TIMER_16BIT | TIMER_RATEGEN) ); 382 bus_space_write_4(iot, ioh, INT2_TIMER_2, (sampletime & 0xff)); 383 bus_space_write_4(iot, ioh, INT2_TIMER_2, (sampletime >> 8)); 384 385 startctr = mips3_cp0_count_read(); 386 387 /* Wait for the MSB to count down to zero */ 388 do { 389 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, TIMER_SEL2 ); 390 lsb = bus_space_read_4(iot, ioh, INT2_TIMER_2) & 0xff; 391 msb = bus_space_read_4(iot, ioh, INT2_TIMER_2) & 0xff; 392 393 endctr = mips3_cp0_count_read(); 394 } while (msb); 395 396 /* Turn off timer */ 397 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, 398 ( TIMER_SEL2 | TIMER_16BIT | TIMER_SWSTROBE) ); 399 400 splx(s); 401 402 return (endctr - startctr) / roundtime * roundtime; 403 } 404 #endif /* MIPS3 */ 405 406 /* 407 * A 1.000MHz master clock is wired to TIMER2, which in turn clocks the two 408 * other timers. On IP12 TIMER1 interrupts on MIPS interrupt 1 and TIMER2 409 * on MIPS interrupt 2. 410 * 411 * Apparently int2 doesn't like counting down from one, but two works, so 412 * we get a good 500000Hz. 413 */ 414 void 415 int_8254_cal(void) 416 { 417 int s; 418 419 s = splhigh(); 420 421 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15, 422 TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT); 423 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 3, (500000 / hz) % 256); 424 wbflush(); 425 delay(4); 426 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 3, (500000 / hz) / 256); 427 428 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15, 429 TIMER_SEL1|TIMER_RATEGEN|TIMER_16BIT); 430 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 7, 0xff); 431 wbflush(); 432 delay(4); 433 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 7, 0xff); 434 435 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15, 436 TIMER_SEL2|TIMER_RATEGEN|TIMER_16BIT); 437 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 11, 2); 438 wbflush(); 439 delay(4); 440 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 11, 0); 441 442 splx(s); 443 } 444 445 446 static u_int 447 int_8254_get_timecount(struct timecounter *tc) 448 { 449 int s; 450 u_int count; 451 u_char lo, hi; 452 453 s = splhigh(); 454 455 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15, 456 TIMER_SEL1 | TIMER_LATCH); 457 lo = bus_space_read_1(iot, ioh, INT2_TIMER_0 + 7); 458 hi = bus_space_read_1(iot, ioh, INT2_TIMER_0 + 7); 459 count = 0xffff - ((hi << 8) | lo); 460 461 splx(s); 462 463 return (int_8254_tc_count + count); 464 } 465 466 static void 467 int_8254_intr0(u_int32_t status, u_int32_t cause, u_int32_t pc, 468 u_int32_t ipending) 469 { 470 struct clockframe cf; 471 472 cf.pc = pc; 473 cf.sr = status; 474 475 hardclock(&cf); 476 477 bus_space_write_4(iot, ioh, INT2_TIMER_CLEAR, 1); 478 } 479 480 481 static void 482 int_8254_intr1(u_int32_t status, u_int32_t cause, u_int32_t pc, 483 u_int32_t ipending) 484 { 485 int s; 486 487 s = splhigh(); 488 489 int_8254_tc_count += 0xffff; 490 bus_space_write_4(iot, ioh, INT2_TIMER_CLEAR, 2); 491 492 splx(s); 493 } 494 495 void 496 int2_wait_fifo(u_int32_t flag) 497 { 498 if (ioh == 0) 499 delay(5000); 500 else 501 while (bus_space_read_4(iot, ioh, INT2_LOCAL0_STATUS) & flag) 502 ; 503 } 504
Indexes created Tue Sep 23 07:09:52 GMT 2025