int.c revision 1.18
1 /* $NetBSD: int.c,v 1.18 2008/05/26 15:59:30 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Christopher SEKIYA 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * INT/INT2/INT3 interrupt controller (used in Indy's, Indigo's, etc..) 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: int.c,v 1.18 2008/05/26 15:59:30 tsutsui Exp $"); 36 37 #include "opt_cputype.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/systm.h> 42 #include <sys/timetc.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <dev/ic/i8253reg.h> 48 #include <machine/sysconf.h> 49 #include <machine/machtype.h> 50 #include <machine/bus.h> 51 #include <mips/locore.h> 52 53 #include <mips/cache.h> 54 55 #include <sgimips/dev/int2reg.h> 56 #include <sgimips/dev/int2var.h> 57 58 static bus_space_handle_t ioh; 59 static bus_space_tag_t iot; 60 61 struct int_softc { 62 struct device sc_dev; 63 }; 64 65 66 static int int_match(struct device *, struct cfdata *, void *); 67 static void int_attach(struct device *, struct device *, void *); 68 static void int_local0_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 69 static void int_local1_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 70 static int int_mappable_intr(void *); 71 static void *int_intr_establish(int, int, int (*)(void *), void *); 72 static void int_8254_cal(void); 73 static u_int int_8254_get_timecount(struct timecounter *); 74 static void int_8254_intr0(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 75 static void int_8254_intr1(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 76 77 #ifdef MIPS3 78 static u_long int_cal_timer(void); 79 #endif 80 81 static struct timecounter int_8254_timecounter = { 82 int_8254_get_timecount, /* get_timecount */ 83 0, /* no poll_pps */ 84 ~0u, /* counter_mask */ 85 500000, /* frequency */ 86 "int i8254", /* name */ 87 100, /* quality */ 88 NULL, /* prev */ 89 NULL, /* next */ 90 }; 91 92 static u_long int_8254_tc_count; 93 94 CFATTACH_DECL(int, sizeof(struct int_softc), 95 int_match, int_attach, NULL, NULL); 96 97 static int 98 int_match(struct device *parent, struct cfdata *match, void *aux) 99 { 100 101 if ((mach_type == MACH_SGI_IP12) || (mach_type == MACH_SGI_IP20) || 102 (mach_type == MACH_SGI_IP22) ) 103 return 1; 104 105 return 0; 106 } 107 108 static void 109 int_attach(struct device *parent, struct device *self, void *aux) 110 { 111 u_int32_t address; 112 113 if (mach_type == MACH_SGI_IP12) 114 address = INT_IP12; 115 else if (mach_type == MACH_SGI_IP20) 116 address = INT_IP20; 117 else if (mach_type == MACH_SGI_IP22) { 118 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 119 address = INT_IP22; 120 else 121 address = INT_IP24; 122 } else 123 panic("\nint0: passed match, but failed attach?"); 124 125 printf(" addr 0x%x\n", address); 126 127 bus_space_map(iot, address, 0, 0, &ioh); 128 iot = SGIMIPS_BUS_SPACE_NORMAL; 129 130 /* Clean out interrupt masks */ 131 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, 0); 132 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, 0); 133 bus_space_write_4(iot, ioh, INT2_MAP_MASK0, 0); 134 bus_space_write_4(iot, ioh, INT2_MAP_MASK1, 0); 135 136 /* Reset timer interrupts */ 137 bus_space_write_4(iot, ioh, INT2_TIMER_CLEAR, 0x03); 138 139 switch (mach_type) { 140 case MACH_SGI_IP12: 141 platform.intr1 = int_local0_intr; 142 platform.intr2 = int_local1_intr; 143 platform.intr3 = int_8254_intr0; 144 platform.intr4 = int_8254_intr1; 145 int_8254_cal(); 146 tc_init(&int_8254_timecounter); 147 break; 148 #ifdef MIPS3 149 case MACH_SGI_IP20: 150 case MACH_SGI_IP22: 151 { 152 int i; 153 unsigned long cps; 154 unsigned long ctrdiff[3]; 155 156 platform.intr0 = int_local0_intr; 157 platform.intr1 = int_local1_intr; 158 159 /* calibrate timer */ 160 int_cal_timer(); 161 162 cps = 0; 163 for (i = 0; 164 i < sizeof(ctrdiff) / sizeof(ctrdiff[0]); i++) { 165 do { 166 ctrdiff[i] = int_cal_timer(); 167 } while (ctrdiff[i] == 0); 168 169 cps += ctrdiff[i]; 170 } 171 172 cps = cps / (sizeof(ctrdiff) / sizeof(ctrdiff[0])); 173 174 printf("%s: bus %luMHz, CPU %luMHz\n", 175 self->dv_xname, cps / 10000, cps / 5000); 176 177 /* R4k/R4400/R4600/R5k count at half CPU frequency */ 178 curcpu()->ci_cpu_freq = 2 * cps * hz; 179 } 180 #endif /* MIPS3 */ 181 182 break; 183 default: 184 panic("int0: unsupported machine type %i\n", mach_type); 185 break; 186 } 187 188 curcpu()->ci_cycles_per_hz = curcpu()->ci_cpu_freq / (2 * hz); 189 curcpu()->ci_divisor_delay = curcpu()->ci_cpu_freq / (2 * 1000000); 190 191 if (mach_type == MACH_SGI_IP22) { 192 /* Wire interrupts 7, 11 to mappable interrupt 0,1 handlers */ 193 intrtab[7].ih_fun = int_mappable_intr; 194 intrtab[7].ih_arg = (void*) 0; 195 196 intrtab[11].ih_fun = int_mappable_intr; 197 intrtab[11].ih_arg = (void*) 1; 198 } 199 200 platform.intr_establish = int_intr_establish; 201 } 202 203 int 204 int_mappable_intr(void *arg) 205 { 206 int i; 207 int ret; 208 int intnum; 209 u_int32_t mstat; 210 u_int32_t mmask; 211 int which = (int)arg; 212 struct sgimips_intrhand *ih; 213 214 ret = 0; 215 mstat = bus_space_read_4(iot, ioh, INT2_MAP_STATUS); 216 mmask = bus_space_read_4(iot, ioh, INT2_MAP_MASK0 + (which << 2)); 217 218 mstat &= mmask; 219 220 for (i = 0; i < 8; i++) { 221 intnum = i + 16 + (which << 3); 222 if (mstat & (1 << i)) { 223 for (ih = &intrtab[intnum]; ih != NULL; 224 ih = ih->ih_next) { 225 if (ih->ih_fun != NULL) 226 ret |= (ih->ih_fun)(ih->ih_arg); 227 else 228 printf("int0: unexpected mapped " 229 "interrupt %d\n", intnum); 230 } 231 } 232 } 233 234 return ret; 235 } 236 237 void 238 int_local0_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, 239 u_int32_t ipending) 240 { 241 int i; 242 u_int32_t l0stat; 243 u_int32_t l0mask; 244 struct sgimips_intrhand *ih; 245 246 l0stat = bus_space_read_4(iot, ioh, INT2_LOCAL0_STATUS); 247 l0mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 248 249 l0stat &= l0mask; 250 251 for (i = 0; i < 8; i++) { 252 if (l0stat & (1 << i)) { 253 for (ih = &intrtab[i]; ih != NULL; ih = ih->ih_next) { 254 if (ih->ih_fun != NULL) 255 (ih->ih_fun)(ih->ih_arg); 256 else 257 printf("int0: unexpected local0 " 258 "interrupt %d\n", i); 259 } 260 } 261 } 262 } 263 264 void 265 int_local1_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, 266 u_int32_t ipending) 267 { 268 int i; 269 u_int32_t l1stat; 270 u_int32_t l1mask; 271 struct sgimips_intrhand *ih; 272 273 l1stat = bus_space_read_4(iot, ioh, INT2_LOCAL1_STATUS); 274 l1mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 275 276 l1stat &= l1mask; 277 278 for (i = 0; i < 8; i++) { 279 if (l1stat & (1 << i)) { 280 for (ih = &intrtab[8+i]; ih != NULL; ih = ih->ih_next) { 281 if (ih->ih_fun != NULL) 282 (ih->ih_fun)(ih->ih_arg); 283 else 284 printf("int0: unexpected local1 " 285 " interrupt %x\n", 8 + i); 286 } 287 } 288 } 289 } 290 291 void * 292 int_intr_establish(int level, int ipl, int (*handler) (void *), void *arg) 293 { 294 u_int32_t mask; 295 296 if (level < 0 || level >= NINTR) 297 panic("invalid interrupt level"); 298 299 if (intrtab[level].ih_fun == NULL) { 300 intrtab[level].ih_fun = handler; 301 intrtab[level].ih_arg = arg; 302 intrtab[level].ih_next = NULL; 303 } else { 304 struct sgimips_intrhand *n, *ih = malloc(sizeof *ih, 305 M_DEVBUF, M_NOWAIT); 306 307 if (ih == NULL) { 308 printf("int_intr_establish: can't allocate handler\n"); 309 return (void *)NULL; 310 } 311 312 ih->ih_fun = handler; 313 ih->ih_arg = arg; 314 ih->ih_next = NULL; 315 316 for (n = &intrtab[level]; n->ih_next != NULL; n = n->ih_next) 317 ; 318 319 n->ih_next = ih; 320 321 return (void *)NULL; /* vector already set */ 322 } 323 324 325 if (level < 8) { 326 mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 327 mask |= (1 << level); 328 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, mask); 329 } else if (level < 16) { 330 mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 331 mask |= (1 << (level - 8)); 332 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, mask); 333 } else if (level < 24) { 334 /* Map0 interrupt maps to l0 bit 7, so turn that on too */ 335 mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 336 mask |= (1 << 7); 337 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, mask); 338 339 mask = bus_space_read_4(iot, ioh, INT2_MAP_MASK0); 340 mask |= (1 << (level - 16)); 341 bus_space_write_4(iot, ioh, INT2_MAP_MASK0, mask); 342 } else { 343 /* Map1 interrupt maps to l1 bit 3, so turn that on too */ 344 mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 345 mask |= (1 << 3); 346 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, mask); 347 348 mask = bus_space_read_4(iot, ioh, INT2_MAP_MASK1); 349 mask |= (1 << (level - 24)); 350 bus_space_write_4(iot, ioh, INT2_MAP_MASK1, mask); 351 } 352 353 return (void *)NULL; 354 } 355 356 #ifdef MIPS3 357 static u_long 358 int_cal_timer(void) 359 { 360 int s; 361 int roundtime; 362 int sampletime; 363 int startmsb, lsb, msb; 364 unsigned long startctr, endctr; 365 366 /* 367 * NOTE: HZ must be greater than 15 for this to work, as otherwise 368 * we'll overflow the counter. We round the answer to hearest 1 369 * MHz of the master (2x) clock. 370 */ 371 roundtime = (1000000 / hz) / 2; 372 sampletime = (1000000 / hz) + 0xff; 373 startmsb = (sampletime >> 8); 374 375 s = splhigh(); 376 377 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, 378 ( TIMER_SEL2 | TIMER_16BIT | TIMER_RATEGEN) ); 379 bus_space_write_4(iot, ioh, INT2_TIMER_2, (sampletime & 0xff)); 380 bus_space_write_4(iot, ioh, INT2_TIMER_2, (sampletime >> 8)); 381 382 startctr = mips3_cp0_count_read(); 383 384 /* Wait for the MSB to count down to zero */ 385 do { 386 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, TIMER_SEL2 ); 387 lsb = bus_space_read_4(iot, ioh, INT2_TIMER_2) & 0xff; 388 msb = bus_space_read_4(iot, ioh, INT2_TIMER_2) & 0xff; 389 390 endctr = mips3_cp0_count_read(); 391 } while (msb); 392 393 /* Turn off timer */ 394 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, 395 ( TIMER_SEL2 | TIMER_16BIT | TIMER_SWSTROBE) ); 396 397 splx(s); 398 399 return (endctr - startctr) / roundtime * roundtime; 400 } 401 #endif /* MIPS3 */ 402 403 /* 404 * A 1.000MHz master clock is wired to TIMER2, which in turn clocks the two 405 * other timers. On IP12 TIMER1 interrupts on MIPS interrupt 1 and TIMER2 406 * on MIPS interrupt 2. 407 * 408 * Apparently int2 doesn't like counting down from one, but two works, so 409 * we get a good 500000Hz. 410 */ 411 void 412 int_8254_cal(void) 413 { 414 int s; 415 416 s = splhigh(); 417 418 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15, 419 TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT); 420 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 3, (500000 / hz) % 256); 421 wbflush(); 422 delay(4); 423 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 3, (500000 / hz) / 256); 424 425 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15, 426 TIMER_SEL1|TIMER_RATEGEN|TIMER_16BIT); 427 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 7, 0xff); 428 wbflush(); 429 delay(4); 430 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 7, 0xff); 431 432 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15, 433 TIMER_SEL2|TIMER_RATEGEN|TIMER_16BIT); 434 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 11, 2); 435 wbflush(); 436 delay(4); 437 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 11, 0); 438 439 splx(s); 440 } 441 442 443 static u_int 444 int_8254_get_timecount(struct timecounter *tc) 445 { 446 int s; 447 u_int count; 448 u_char lo, hi; 449 450 s = splhigh(); 451 452 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15, 453 TIMER_SEL1 | TIMER_LATCH); 454 lo = bus_space_read_1(iot, ioh, INT2_TIMER_0 + 7); 455 hi = bus_space_read_1(iot, ioh, INT2_TIMER_0 + 7); 456 count = 0xffff - ((hi << 8) | lo); 457 458 splx(s); 459 460 return (int_8254_tc_count + count); 461 } 462 463 static void 464 int_8254_intr0(u_int32_t status, u_int32_t cause, u_int32_t pc, 465 u_int32_t ipending) 466 { 467 struct clockframe cf; 468 469 cf.pc = pc; 470 cf.sr = status; 471 472 hardclock(&cf); 473 474 bus_space_write_4(iot, ioh, INT2_TIMER_CLEAR, 1); 475 } 476 477 478 static void 479 int_8254_intr1(u_int32_t status, u_int32_t cause, u_int32_t pc, 480 u_int32_t ipending) 481 { 482 int s; 483 484 s = splhigh(); 485 486 int_8254_tc_count += 0xffff; 487 bus_space_write_4(iot, ioh, INT2_TIMER_CLEAR, 2); 488 489 splx(s); 490 } 491 492 void 493 int2_wait_fifo(u_int32_t flag) 494 { 495 if (ioh == 0) 496 delay(5000); 497 else 498 while (bus_space_read_4(iot, ioh, INT2_LOCAL0_STATUS) & flag) 499 ; 500 } 501
Indexes created Thu Oct 02 14:10:14 GMT 2025