int.c revision 1.19
1 /* $NetBSD: int.c,v 1.19 2008/08/23 17:25:54 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Christopher SEKIYA 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * INT/INT2/INT3 interrupt controller (used in Indy's, Indigo's, etc..) 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: int.c,v 1.19 2008/08/23 17:25:54 tsutsui Exp $"); 36 37 #include "opt_cputype.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/systm.h> 42 #include <sys/timetc.h> 43 #include <sys/kernel.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <dev/ic/i8253reg.h> 48 #include <machine/sysconf.h> 49 #include <machine/machtype.h> 50 #include <machine/bus.h> 51 #include <mips/locore.h> 52 53 #include <mips/cache.h> 54 55 #include <sgimips/dev/int2reg.h> 56 #include <sgimips/dev/int2var.h> 57 58 static bus_space_handle_t ioh; 59 static bus_space_tag_t iot; 60 61 struct int_softc { 62 struct device sc_dev; 63 }; 64 65 66 static int int_match(struct device *, struct cfdata *, void *); 67 static void int_attach(struct device *, struct device *, void *); 68 static void int_local0_intr(uint32_t, uint32_t, uint32_t, uint32_t); 69 static void int_local1_intr(uint32_t, uint32_t, uint32_t, uint32_t); 70 static int int_mappable_intr(void *); 71 static void *int_intr_establish(int, int, int (*)(void *), void *); 72 static void int_8254_cal(void); 73 static u_int int_8254_get_timecount(struct timecounter *); 74 static void int_8254_intr0(uint32_t, uint32_t, uint32_t, uint32_t); 75 static void int_8254_intr1(uint32_t, uint32_t, uint32_t, uint32_t); 76 77 #ifdef MIPS3 78 static u_long int_cal_timer(void); 79 #endif 80 81 static struct timecounter int_8254_timecounter = { 82 int_8254_get_timecount, /* get_timecount */ 83 0, /* no poll_pps */ 84 ~0u, /* counter_mask */ 85 500000, /* frequency */ 86 "int i8254", /* name */ 87 100, /* quality */ 88 NULL, /* prev */ 89 NULL, /* next */ 90 }; 91 92 static u_long int_8254_tc_count; 93 94 CFATTACH_DECL(int, sizeof(struct int_softc), 95 int_match, int_attach, NULL, NULL); 96 97 static int 98 int_match(struct device *parent, struct cfdata *match, void *aux) 99 { 100 101 if ((mach_type == MACH_SGI_IP12) || (mach_type == MACH_SGI_IP20) || 102 (mach_type == MACH_SGI_IP22) ) 103 return 1; 104 105 return 0; 106 } 107 108 static void 109 int_attach(struct device *parent, struct device *self, void *aux) 110 { 111 uint32_t address; 112 113 if (mach_type == MACH_SGI_IP12) 114 address = INT_IP12; 115 else if (mach_type == MACH_SGI_IP20) 116 address = INT_IP20; 117 else if (mach_type == MACH_SGI_IP22) { 118 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 119 address = INT_IP22; 120 else 121 address = INT_IP24; 122 } else 123 panic("\nint0: passed match, but failed attach?"); 124 125 printf(" addr 0x%x\n", address); 126 127 bus_space_map(iot, address, 0, 0, &ioh); 128 iot = SGIMIPS_BUS_SPACE_NORMAL; 129 130 /* Clean out interrupt masks */ 131 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, 0); 132 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, 0); 133 bus_space_write_4(iot, ioh, INT2_MAP_MASK0, 0); 134 bus_space_write_4(iot, ioh, INT2_MAP_MASK1, 0); 135 136 /* Reset timer interrupts */ 137 bus_space_write_4(iot, ioh, INT2_TIMER_CLEAR, 0x03); 138 139 switch (mach_type) { 140 case MACH_SGI_IP12: 141 platform.intr1 = int_local0_intr; 142 platform.intr2 = int_local1_intr; 143 platform.intr3 = int_8254_intr0; 144 platform.intr4 = int_8254_intr1; 145 int_8254_cal(); 146 tc_init(&int_8254_timecounter); 147 break; 148 #ifdef MIPS3 149 case MACH_SGI_IP20: 150 case MACH_SGI_IP22: 151 { 152 int i; 153 unsigned long cps; 154 unsigned long ctrdiff[3]; 155 156 platform.intr0 = int_local0_intr; 157 platform.intr1 = int_local1_intr; 158 159 /* calibrate timer */ 160 int_cal_timer(); 161 162 cps = 0; 163 for (i = 0; i < sizeof(ctrdiff) / sizeof(ctrdiff[0]); i++) { 164 do { 165 ctrdiff[i] = int_cal_timer(); 166 } while (ctrdiff[i] == 0); 167 168 cps += ctrdiff[i]; 169 } 170 171 cps = cps / (sizeof(ctrdiff) / sizeof(ctrdiff[0])); 172 173 printf("%s: bus %luMHz, CPU %luMHz\n", 174 self->dv_xname, cps / 10000, cps / 5000); 175 176 /* R4k/R4400/R4600/R5k count at half CPU frequency */ 177 curcpu()->ci_cpu_freq = 2 * cps * hz; 178 } 179 #endif /* MIPS3 */ 180 181 break; 182 default: 183 panic("int0: unsupported machine type %i\n", mach_type); 184 break; 185 } 186 187 curcpu()->ci_cycles_per_hz = curcpu()->ci_cpu_freq / (2 * hz); 188 curcpu()->ci_divisor_delay = curcpu()->ci_cpu_freq / (2 * 1000000); 189 190 if (mach_type == MACH_SGI_IP22) { 191 /* Wire interrupts 7, 11 to mappable interrupt 0,1 handlers */ 192 intrtab[7].ih_fun = int_mappable_intr; 193 intrtab[7].ih_arg = (void*) 0; 194 195 intrtab[11].ih_fun = int_mappable_intr; 196 intrtab[11].ih_arg = (void*) 1; 197 } 198 199 platform.intr_establish = int_intr_establish; 200 } 201 202 int 203 int_mappable_intr(void *arg) 204 { 205 int i; 206 int ret; 207 int intnum; 208 uint32_t mstat; 209 uint32_t mmask; 210 int which = (int)arg; 211 struct sgimips_intrhand *ih; 212 213 ret = 0; 214 mstat = bus_space_read_4(iot, ioh, INT2_MAP_STATUS); 215 mmask = bus_space_read_4(iot, ioh, INT2_MAP_MASK0 + (which << 2)); 216 217 mstat &= mmask; 218 219 for (i = 0; i < 8; i++) { 220 intnum = i + 16 + (which << 3); 221 if (mstat & (1 << i)) { 222 for (ih = &intrtab[intnum]; ih != NULL; 223 ih = ih->ih_next) { 224 if (ih->ih_fun != NULL) 225 ret |= (ih->ih_fun)(ih->ih_arg); 226 else 227 printf("int0: unexpected mapped " 228 "interrupt %d\n", intnum); 229 } 230 } 231 } 232 233 return ret; 234 } 235 236 void 237 int_local0_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending) 238 { 239 int i; 240 uint32_t l0stat; 241 uint32_t l0mask; 242 struct sgimips_intrhand *ih; 243 244 l0stat = bus_space_read_4(iot, ioh, INT2_LOCAL0_STATUS); 245 l0mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 246 247 l0stat &= l0mask; 248 249 for (i = 0; i < 8; i++) { 250 if (l0stat & (1 << i)) { 251 for (ih = &intrtab[i]; ih != NULL; ih = ih->ih_next) { 252 if (ih->ih_fun != NULL) 253 (ih->ih_fun)(ih->ih_arg); 254 else 255 printf("int0: unexpected local0 " 256 "interrupt %d\n", i); 257 } 258 } 259 } 260 } 261 262 void 263 int_local1_intr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending) 264 { 265 int i; 266 uint32_t l1stat; 267 uint32_t l1mask; 268 struct sgimips_intrhand *ih; 269 270 l1stat = bus_space_read_4(iot, ioh, INT2_LOCAL1_STATUS); 271 l1mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 272 273 l1stat &= l1mask; 274 275 for (i = 0; i < 8; i++) { 276 if (l1stat & (1 << i)) { 277 for (ih = &intrtab[8+i]; ih != NULL; ih = ih->ih_next) { 278 if (ih->ih_fun != NULL) 279 (ih->ih_fun)(ih->ih_arg); 280 else 281 printf("int0: unexpected local1 " 282 " interrupt %x\n", 8 + i); 283 } 284 } 285 } 286 } 287 288 void * 289 int_intr_establish(int level, int ipl, int (*handler) (void *), void *arg) 290 { 291 uint32_t mask; 292 293 if (level < 0 || level >= NINTR) 294 panic("invalid interrupt level"); 295 296 if (intrtab[level].ih_fun == NULL) { 297 intrtab[level].ih_fun = handler; 298 intrtab[level].ih_arg = arg; 299 intrtab[level].ih_next = NULL; 300 } else { 301 struct sgimips_intrhand *n, *ih; 302 303 ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 304 if (ih == NULL) { 305 printf("int_intr_establish: can't allocate handler\n"); 306 return NULL; 307 } 308 309 ih->ih_fun = handler; 310 ih->ih_arg = arg; 311 ih->ih_next = NULL; 312 313 for (n = &intrtab[level]; n->ih_next != NULL; n = n->ih_next) 314 ; 315 316 n->ih_next = ih; 317 318 return NULL; /* vector already set */ 319 } 320 321 322 if (level < 8) { 323 mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 324 mask |= (1 << level); 325 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, mask); 326 } else if (level < 16) { 327 mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 328 mask |= (1 << (level - 8)); 329 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, mask); 330 } else if (level < 24) { 331 /* Map0 interrupt maps to l0 bit 7, so turn that on too */ 332 mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 333 mask |= (1 << 7); 334 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, mask); 335 336 mask = bus_space_read_4(iot, ioh, INT2_MAP_MASK0); 337 mask |= (1 << (level - 16)); 338 bus_space_write_4(iot, ioh, INT2_MAP_MASK0, mask); 339 } else { 340 /* Map1 interrupt maps to l1 bit 3, so turn that on too */ 341 mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 342 mask |= (1 << 3); 343 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, mask); 344 345 mask = bus_space_read_4(iot, ioh, INT2_MAP_MASK1); 346 mask |= (1 << (level - 24)); 347 bus_space_write_4(iot, ioh, INT2_MAP_MASK1, mask); 348 } 349 350 return NULL; 351 } 352 353 #ifdef MIPS3 354 static u_long 355 int_cal_timer(void) 356 { 357 int s; 358 int roundtime; 359 int sampletime; 360 int startmsb, lsb, msb; 361 unsigned long startctr, endctr; 362 363 /* 364 * NOTE: HZ must be greater than 15 for this to work, as otherwise 365 * we'll overflow the counter. We round the answer to hearest 1 366 * MHz of the master (2x) clock. 367 */ 368 roundtime = (1000000 / hz) / 2; 369 sampletime = (1000000 / hz) + 0xff; 370 startmsb = (sampletime >> 8); 371 372 s = splhigh(); 373 374 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, 375 (TIMER_SEL2 | TIMER_16BIT | TIMER_RATEGEN)); 376 bus_space_write_4(iot, ioh, INT2_TIMER_2, (sampletime & 0xff)); 377 bus_space_write_4(iot, ioh, INT2_TIMER_2, (sampletime >> 8)); 378 379 startctr = mips3_cp0_count_read(); 380 381 /* Wait for the MSB to count down to zero */ 382 do { 383 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, TIMER_SEL2); 384 lsb = bus_space_read_4(iot, ioh, INT2_TIMER_2) & 0xff; 385 msb = bus_space_read_4(iot, ioh, INT2_TIMER_2) & 0xff; 386 387 endctr = mips3_cp0_count_read(); 388 } while (msb); 389 390 /* Turn off timer */ 391 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, 392 (TIMER_SEL2 | TIMER_16BIT | TIMER_SWSTROBE)); 393 394 splx(s); 395 396 return (endctr - startctr) / roundtime * roundtime; 397 } 398 #endif /* MIPS3 */ 399 400 /* 401 * A 1.000MHz master clock is wired to TIMER2, which in turn clocks the two 402 * other timers. On IP12 TIMER1 interrupts on MIPS interrupt 1 and TIMER2 403 * on MIPS interrupt 2. 404 * 405 * Apparently int2 doesn't like counting down from one, but two works, so 406 * we get a good 500000Hz. 407 */ 408 void 409 int_8254_cal(void) 410 { 411 int s; 412 413 s = splhigh(); 414 415 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15, 416 TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT); 417 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 3, (500000 / hz) % 256); 418 wbflush(); 419 delay(4); 420 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 3, (500000 / hz) / 256); 421 422 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15, 423 TIMER_SEL1|TIMER_RATEGEN|TIMER_16BIT); 424 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 7, 0xff); 425 wbflush(); 426 delay(4); 427 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 7, 0xff); 428 429 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15, 430 TIMER_SEL2|TIMER_RATEGEN|TIMER_16BIT); 431 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 11, 2); 432 wbflush(); 433 delay(4); 434 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 11, 0); 435 436 splx(s); 437 } 438 439 440 static u_int 441 int_8254_get_timecount(struct timecounter *tc) 442 { 443 int s; 444 u_int count; 445 uint8_t lo, hi; 446 447 s = splhigh(); 448 449 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15, 450 TIMER_SEL1 | TIMER_LATCH); 451 lo = bus_space_read_1(iot, ioh, INT2_TIMER_0 + 7); 452 hi = bus_space_read_1(iot, ioh, INT2_TIMER_0 + 7); 453 count = 0xffff - ((hi << 8) | lo); 454 455 splx(s); 456 457 return int_8254_tc_count + count; 458 } 459 460 static void 461 int_8254_intr0(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending) 462 { 463 struct clockframe cf; 464 465 cf.pc = pc; 466 cf.sr = status; 467 468 hardclock(&cf); 469 470 bus_space_write_4(iot, ioh, INT2_TIMER_CLEAR, 1); 471 } 472 473 474 static void 475 int_8254_intr1(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending) 476 { 477 int s; 478 479 s = splhigh(); 480 481 int_8254_tc_count += 0xffff; 482 bus_space_write_4(iot, ioh, INT2_TIMER_CLEAR, 2); 483 484 splx(s); 485 } 486 487 void 488 int2_wait_fifo(uint32_t flag) 489 { 490 491 if (ioh == 0) 492 delay(5000); 493 else 494 while (bus_space_read_4(iot, ioh, INT2_LOCAL0_STATUS) & flag) 495 ; 496 } 497
Indexes created Wed Sep 24 15:09:51 GMT 2025