int.c revision 1.19.12.2
1 /* $NetBSD: int.c,v 1.19.12.2 2010/12/29 07:15:47 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Christopher SEKIYA 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * INT/INT2/INT3 interrupt controller (used in Indy's, Indigo's, etc..) 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: int.c,v 1.19.12.2 2010/12/29 07:15:47 matt Exp $"); 36 37 #define __INTR_PRIVATE 38 #include "opt_cputype.h" 39 40 #include <sys/param.h> 41 #include <sys/proc.h> 42 #include <sys/systm.h> 43 #include <sys/timetc.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/malloc.h> 47 48 #include <dev/ic/i8253reg.h> 49 #include <machine/sysconf.h> 50 #include <machine/machtype.h> 51 #include <machine/bus.h> 52 #include <mips/locore.h> 53 54 #include <mips/cache.h> 55 56 #include <sgimips/dev/int2reg.h> 57 #include <sgimips/dev/int2var.h> 58 59 static bus_space_handle_t ioh; 60 static bus_space_tag_t iot; 61 62 struct int_softc { 63 struct device sc_dev; 64 }; 65 66 67 static int int_match(struct device *, struct cfdata *, void *); 68 static void int_attach(struct device *, struct device *, void *); 69 static void int_local0_intr(vaddr_t, uint32_t, uint32_t); 70 static void int_local1_intr(vaddr_t, uint32_t, uint32_t); 71 static int int_mappable_intr(void *); 72 static void *int_intr_establish(int, int, int (*)(void *), void *); 73 static void int_8254_cal(void); 74 static u_int int_8254_get_timecount(struct timecounter *); 75 static void int_8254_intr0(vaddr_t, uint32_t, uint32_t); 76 static void int_8254_intr1(vaddr_t, uint32_t, uint32_t); 77 78 #ifdef MIPS3 79 static u_long int_cal_timer(void); 80 #endif 81 82 static struct timecounter int_8254_timecounter = { 83 int_8254_get_timecount, /* get_timecount */ 84 0, /* no poll_pps */ 85 ~0u, /* counter_mask */ 86 500000, /* frequency */ 87 "int i8254", /* name */ 88 100, /* quality */ 89 NULL, /* prev */ 90 NULL, /* next */ 91 }; 92 93 static u_long int_8254_tc_count; 94 95 CFATTACH_DECL(int, sizeof(struct int_softc), 96 int_match, int_attach, NULL, NULL); 97 98 static int 99 int_match(struct device *parent, struct cfdata *match, void *aux) 100 { 101 102 if ((mach_type == MACH_SGI_IP12) || (mach_type == MACH_SGI_IP20) || 103 (mach_type == MACH_SGI_IP22) ) 104 return 1; 105 106 return 0; 107 } 108 109 static void 110 int_attach(struct device *parent, struct device *self, void *aux) 111 { 112 uint32_t address; 113 114 if (mach_type == MACH_SGI_IP12) 115 address = INT_IP12; 116 else if (mach_type == MACH_SGI_IP20) 117 address = INT_IP20; 118 else if (mach_type == MACH_SGI_IP22) { 119 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 120 address = INT_IP22; 121 else 122 address = INT_IP24; 123 } else 124 panic("\nint0: passed match, but failed attach?"); 125 126 printf(" addr 0x%x\n", address); 127 128 bus_space_map(iot, address, 0, 0, &ioh); 129 iot = SGIMIPS_BUS_SPACE_NORMAL; 130 131 /* Clean out interrupt masks */ 132 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, 0); 133 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, 0); 134 bus_space_write_4(iot, ioh, INT2_MAP_MASK0, 0); 135 bus_space_write_4(iot, ioh, INT2_MAP_MASK1, 0); 136 137 /* Reset timer interrupts */ 138 bus_space_write_4(iot, ioh, INT2_TIMER_CLEAR, 0x03); 139 140 switch (mach_type) { 141 case MACH_SGI_IP12: 142 platform.intr1 = int_local0_intr; 143 platform.intr2 = int_local1_intr; 144 platform.intr3 = int_8254_intr0; 145 platform.intr4 = int_8254_intr1; 146 int_8254_cal(); 147 tc_init(&int_8254_timecounter); 148 break; 149 #ifdef MIPS3 150 case MACH_SGI_IP20: 151 case MACH_SGI_IP22: 152 { 153 int i; 154 unsigned long cps; 155 unsigned long ctrdiff[3]; 156 157 platform.intr0 = int_local0_intr; 158 platform.intr1 = int_local1_intr; 159 160 /* calibrate timer */ 161 int_cal_timer(); 162 163 cps = 0; 164 for (i = 0; i < sizeof(ctrdiff) / sizeof(ctrdiff[0]); i++) { 165 do { 166 ctrdiff[i] = int_cal_timer(); 167 } while (ctrdiff[i] == 0); 168 169 cps += ctrdiff[i]; 170 } 171 172 cps = cps / (sizeof(ctrdiff) / sizeof(ctrdiff[0])); 173 174 printf("%s: bus %luMHz, CPU %luMHz\n", 175 self->dv_xname, cps / 10000, cps / 5000); 176 177 /* R4k/R4400/R4600/R5k count at half CPU frequency */ 178 curcpu()->ci_cpu_freq = 2 * cps * hz; 179 } 180 #endif /* MIPS3 */ 181 182 break; 183 default: 184 panic("int0: unsupported machine type %i\n", mach_type); 185 break; 186 } 187 188 curcpu()->ci_cycles_per_hz = curcpu()->ci_cpu_freq / (2 * hz); 189 curcpu()->ci_divisor_delay = curcpu()->ci_cpu_freq / (2 * 1000000); 190 191 if (mach_type == MACH_SGI_IP22) { 192 /* Wire interrupts 7, 11 to mappable interrupt 0,1 handlers */ 193 intrtab[7].ih_fun = int_mappable_intr; 194 intrtab[7].ih_arg = (void*) 0; 195 196 intrtab[11].ih_fun = int_mappable_intr; 197 intrtab[11].ih_arg = (void*) 1; 198 } 199 200 platform.intr_establish = int_intr_establish; 201 } 202 203 int 204 int_mappable_intr(void *arg) 205 { 206 int i; 207 int ret; 208 int intnum; 209 uint32_t mstat; 210 uint32_t mmask; 211 int which = (intptr_t)arg; 212 struct sgimips_intrhand *ih; 213 214 ret = 0; 215 mstat = bus_space_read_4(iot, ioh, INT2_MAP_STATUS); 216 mmask = bus_space_read_4(iot, ioh, INT2_MAP_MASK0 + (which << 2)); 217 218 mstat &= mmask; 219 220 for (i = 0; i < 8; i++) { 221 intnum = i + 16 + (which << 3); 222 if (mstat & (1 << i)) { 223 for (ih = &intrtab[intnum]; ih != NULL; 224 ih = ih->ih_next) { 225 if (ih->ih_fun != NULL) 226 ret |= (ih->ih_fun)(ih->ih_arg); 227 else 228 printf("int0: unexpected mapped " 229 "interrupt %d\n", intnum); 230 } 231 } 232 } 233 234 return ret; 235 } 236 237 void 238 int_local0_intr(vaddr_t pc, uint32_t status, uint32_t ipending) 239 { 240 int i; 241 uint32_t l0stat; 242 uint32_t l0mask; 243 struct sgimips_intrhand *ih; 244 245 l0stat = bus_space_read_4(iot, ioh, INT2_LOCAL0_STATUS); 246 l0mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 247 248 l0stat &= l0mask; 249 250 for (i = 0; i < 8; i++) { 251 if (l0stat & (1 << i)) { 252 for (ih = &intrtab[i]; ih != NULL; ih = ih->ih_next) { 253 if (ih->ih_fun != NULL) 254 (ih->ih_fun)(ih->ih_arg); 255 else 256 printf("int0: unexpected local0 " 257 "interrupt %d\n", i); 258 } 259 } 260 } 261 } 262 263 void 264 int_local1_intr(vaddr_t pc, uint32_t status, uint32_t ipending) 265 { 266 int i; 267 uint32_t l1stat; 268 uint32_t l1mask; 269 struct sgimips_intrhand *ih; 270 271 l1stat = bus_space_read_4(iot, ioh, INT2_LOCAL1_STATUS); 272 l1mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 273 274 l1stat &= l1mask; 275 276 for (i = 0; i < 8; i++) { 277 if (l1stat & (1 << i)) { 278 for (ih = &intrtab[8+i]; ih != NULL; ih = ih->ih_next) { 279 if (ih->ih_fun != NULL) 280 (ih->ih_fun)(ih->ih_arg); 281 else 282 printf("int0: unexpected local1 " 283 " interrupt %x\n", 8 + i); 284 } 285 } 286 } 287 } 288 289 void * 290 int_intr_establish(int level, int ipl, int (*handler) (void *), void *arg) 291 { 292 uint32_t mask; 293 294 if (level < 0 || level >= NINTR) 295 panic("invalid interrupt level"); 296 297 if (intrtab[level].ih_fun == NULL) { 298 intrtab[level].ih_fun = handler; 299 intrtab[level].ih_arg = arg; 300 intrtab[level].ih_next = NULL; 301 } else { 302 struct sgimips_intrhand *n, *ih; 303 304 ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 305 if (ih == NULL) { 306 printf("int_intr_establish: can't allocate handler\n"); 307 return NULL; 308 } 309 310 ih->ih_fun = handler; 311 ih->ih_arg = arg; 312 ih->ih_next = NULL; 313 314 for (n = &intrtab[level]; n->ih_next != NULL; n = n->ih_next) 315 ; 316 317 n->ih_next = ih; 318 319 return NULL; /* vector already set */ 320 } 321 322 323 if (level < 8) { 324 mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 325 mask |= (1 << level); 326 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, mask); 327 } else if (level < 16) { 328 mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 329 mask |= (1 << (level - 8)); 330 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, mask); 331 } else if (level < 24) { 332 /* Map0 interrupt maps to l0 bit 7, so turn that on too */ 333 mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 334 mask |= (1 << 7); 335 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, mask); 336 337 mask = bus_space_read_4(iot, ioh, INT2_MAP_MASK0); 338 mask |= (1 << (level - 16)); 339 bus_space_write_4(iot, ioh, INT2_MAP_MASK0, mask); 340 } else { 341 /* Map1 interrupt maps to l1 bit 3, so turn that on too */ 342 mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 343 mask |= (1 << 3); 344 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, mask); 345 346 mask = bus_space_read_4(iot, ioh, INT2_MAP_MASK1); 347 mask |= (1 << (level - 24)); 348 bus_space_write_4(iot, ioh, INT2_MAP_MASK1, mask); 349 } 350 351 return NULL; 352 } 353 354 #ifdef MIPS3 355 static u_long 356 int_cal_timer(void) 357 { 358 int s; 359 int roundtime; 360 int sampletime; 361 int startmsb, lsb, msb; 362 unsigned long startctr, endctr; 363 364 /* 365 * NOTE: HZ must be greater than 15 for this to work, as otherwise 366 * we'll overflow the counter. We round the answer to hearest 1 367 * MHz of the master (2x) clock. 368 */ 369 roundtime = (1000000 / hz) / 2; 370 sampletime = (1000000 / hz) + 0xff; 371 startmsb = (sampletime >> 8); 372 373 s = splhigh(); 374 375 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, 376 (TIMER_SEL2 | TIMER_16BIT | TIMER_RATEGEN)); 377 bus_space_write_4(iot, ioh, INT2_TIMER_2, (sampletime & 0xff)); 378 bus_space_write_4(iot, ioh, INT2_TIMER_2, (sampletime >> 8)); 379 380 startctr = mips3_cp0_count_read(); 381 382 /* Wait for the MSB to count down to zero */ 383 do { 384 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, TIMER_SEL2); 385 lsb = bus_space_read_4(iot, ioh, INT2_TIMER_2) & 0xff; 386 msb = bus_space_read_4(iot, ioh, INT2_TIMER_2) & 0xff; 387 388 endctr = mips3_cp0_count_read(); 389 } while (msb); 390 391 /* Turn off timer */ 392 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, 393 (TIMER_SEL2 | TIMER_16BIT | TIMER_SWSTROBE)); 394 395 splx(s); 396 397 return (endctr - startctr) / roundtime * roundtime; 398 } 399 #endif /* MIPS3 */ 400 401 /* 402 * A 1.000MHz master clock is wired to TIMER2, which in turn clocks the two 403 * other timers. On IP12 TIMER1 interrupts on MIPS interrupt 1 and TIMER2 404 * on MIPS interrupt 2. 405 * 406 * Apparently int2 doesn't like counting down from one, but two works, so 407 * we get a good 500000Hz. 408 */ 409 void 410 int_8254_cal(void) 411 { 412 int s; 413 414 s = splhigh(); 415 416 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15, 417 TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT); 418 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 3, (500000 / hz) % 256); 419 wbflush(); 420 delay(4); 421 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 3, (500000 / hz) / 256); 422 423 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15, 424 TIMER_SEL1|TIMER_RATEGEN|TIMER_16BIT); 425 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 7, 0xff); 426 wbflush(); 427 delay(4); 428 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 7, 0xff); 429 430 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15, 431 TIMER_SEL2|TIMER_RATEGEN|TIMER_16BIT); 432 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 11, 2); 433 wbflush(); 434 delay(4); 435 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 11, 0); 436 437 splx(s); 438 } 439 440 441 static u_int 442 int_8254_get_timecount(struct timecounter *tc) 443 { 444 int s; 445 u_int count; 446 uint8_t lo, hi; 447 448 s = splhigh(); 449 450 bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15, 451 TIMER_SEL1 | TIMER_LATCH); 452 lo = bus_space_read_1(iot, ioh, INT2_TIMER_0 + 7); 453 hi = bus_space_read_1(iot, ioh, INT2_TIMER_0 + 7); 454 count = 0xffff - ((hi << 8) | lo); 455 456 splx(s); 457 458 return int_8254_tc_count + count; 459 } 460 461 static void 462 int_8254_intr0(vaddr_t pc, uint32_t status, uint32_t ipending) 463 { 464 struct clockframe cf; 465 466 cf.pc = pc; 467 cf.sr = status; 468 469 hardclock(&cf); 470 471 bus_space_write_4(iot, ioh, INT2_TIMER_CLEAR, 1); 472 } 473 474 475 static void 476 int_8254_intr1(vaddr_t pc, uint32_t status, uint32_t ipending) 477 { 478 int s; 479 480 s = splhigh(); 481 482 int_8254_tc_count += 0xffff; 483 bus_space_write_4(iot, ioh, INT2_TIMER_CLEAR, 2); 484 485 splx(s); 486 } 487 488 void 489 int2_wait_fifo(uint32_t flag) 490 { 491 492 if (ioh == 0) 493 delay(5000); 494 else 495 while (bus_space_read_4(iot, ioh, INT2_LOCAL0_STATUS) & flag) 496 ; 497 } 498
Indexes created Thu Oct 02 14:10:14 GMT 2025