int.c revision 1.28.18.1
1 /* $NetBSD: int.c,v 1.28.18.1 2019/06/10 22:06:43 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2009 Stephen M. Rumble 5 * Copyright (c) 2004 Christopher SEKIYA 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * INT1/INT2/INT3 interrupt controllers (IP6, IP10, IP12, IP20, IP22, IP24...) 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: int.c,v 1.28.18.1 2019/06/10 22:06:43 christos Exp $"); 37 38 #define __INTR_PRIVATE 39 #include "opt_cputype.h" 40 41 #include <sys/param.h> 42 #include <sys/proc.h> 43 #include <sys/systm.h> 44 #include <sys/timetc.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 49 #include <dev/ic/i8253reg.h> 50 #include <machine/sysconf.h> 51 #include <machine/machtype.h> 52 #include <sys/bus.h> 53 #include <mips/locore.h> 54 55 #include <mips/cache.h> 56 57 #include <sgimips/dev/int1reg.h> 58 #include <sgimips/dev/int2reg.h> 59 #include <sgimips/dev/int2var.h> 60 61 static bus_space_handle_t ioh; 62 static bus_space_tag_t iot; 63 64 static int int_match(device_t, cfdata_t, void *); 65 static void int_attach(device_t, device_t, void *); 66 static void *int1_intr_establish(int, int, int (*)(void *), void *); 67 static void *int2_intr_establish(int, int, int (*)(void *), void *); 68 static void int1_local_intr(vaddr_t, uint32_t, uint32_t); 69 static void int2_local0_intr(vaddr_t, uint32_t, uint32_t); 70 static void int2_local1_intr(vaddr_t, uint32_t, uint32_t); 71 static int int2_mappable_intr(void *); 72 static void int_8254_cal(void); 73 static u_int int_8254_get_timecount(struct timecounter *); 74 static void int_8254_intr0(vaddr_t, uint32_t, uint32_t); 75 static void int_8254_intr1(vaddr_t, uint32_t, uint32_t); 76 77 #ifdef MIPS3 78 static u_long int2_cpu_freq(device_t); 79 static u_long int2_cal_timer(void); 80 #endif 81 82 static struct timecounter int_8254_timecounter = { 83 int_8254_get_timecount, /* get_timecount */ 84 0, /* no poll_pps */ 85 ~0u, /* counter_mask */ 86 0, /* frequency; set in int_8254_cal */ 87 "int i8254", /* name */ 88 100, /* quality */ 89 NULL, /* prev */ 90 NULL, /* next */ 91 }; 92 93 static u_long int_8254_tc_count; 94 95 CFATTACH_DECL_NEW(int, 0, 96 int_match, int_attach, NULL, NULL); 97 98 static int 99 int_match(device_t parent, cfdata_t match, void *aux) 100 { 101 102 switch (mach_type) { 103 case MACH_SGI_IP6 | MACH_SGI_IP10: 104 case MACH_SGI_IP12: 105 case MACH_SGI_IP20: 106 case MACH_SGI_IP22: 107 return 1; 108 } 109 110 return 0; 111 } 112 113 static void 114 int_attach(device_t parent, device_t self, void *aux) 115 { 116 uint32_t address; 117 int i; 118 119 for (i = 0; i < NINTR; i++) { 120 intrtab[i].ih_fun = NULL; 121 snprintf(intrtab[i].ih_evname, 7, "%d", i); 122 } 123 124 switch (mach_type) { 125 case MACH_SGI_IP6 | MACH_SGI_IP10: 126 address = INT1_IP6_IP10; 127 break; 128 129 case MACH_SGI_IP12: 130 address = INT2_IP12; 131 break; 132 133 case MACH_SGI_IP20: 134 address = INT2_IP20; 135 break; 136 137 case MACH_SGI_IP22: 138 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 139 address = INT2_IP22; 140 else 141 address = INT2_IP24; 142 break; 143 144 default: 145 panic("\nint0: passed match, but failed attach?"); 146 } 147 148 printf(" addr 0x%x\n", address); 149 150 iot = normal_memt; 151 /* 152 * XXX INT1 registers are spread *way* out, but for now this should 153 * work 154 */ 155 bus_space_map(iot, address, 0x100, 0, &ioh); 156 157 switch (mach_type) { 158 case MACH_SGI_IP6 | MACH_SGI_IP10: 159 /* Clean out interrupt masks */ 160 bus_space_write_1(iot, ioh, INT1_LOCAL_MASK, 0); 161 162 /* Turn off timers and clear interrupts */ 163 bus_space_write_1(iot, ioh, INT1_TIMER_CONTROL, 164 (TIMER_SEL0 | TIMER_16BIT | TIMER_SWSTROBE)); 165 bus_space_write_1(iot, ioh, INT1_TIMER_CONTROL, 166 (TIMER_SEL1 | TIMER_16BIT | TIMER_SWSTROBE)); 167 bus_space_write_1(iot, ioh, INT1_TIMER_CONTROL, 168 (TIMER_SEL2 | TIMER_16BIT | TIMER_SWSTROBE)); 169 wbflush(); 170 delay(4); 171 bus_space_read_1(iot, ioh, INT1_TIMER_0_ACK); 172 bus_space_read_1(iot, ioh, INT1_TIMER_1_ACK); 173 174 platform.intr_establish = int1_intr_establish; 175 platform.intr1 = int1_local_intr; 176 platform.intr2 = int_8254_intr0; 177 platform.intr4 = int_8254_intr1; 178 int_8254_cal(); 179 break; 180 181 case MACH_SGI_IP12: 182 case MACH_SGI_IP20: 183 case MACH_SGI_IP22: 184 /* Clean out interrupt masks */ 185 bus_space_write_1(iot, ioh, INT2_LOCAL0_MASK, 0); 186 bus_space_write_1(iot, ioh, INT2_LOCAL1_MASK, 0); 187 bus_space_write_1(iot, ioh, INT2_MAP_MASK0, 0); 188 bus_space_write_1(iot, ioh, INT2_MAP_MASK1, 0); 189 190 /* Reset timer interrupts */ 191 bus_space_write_1(iot, ioh, INT2_TIMER_CONTROL, 192 (TIMER_SEL0 | TIMER_16BIT | TIMER_SWSTROBE)); 193 bus_space_write_1(iot, ioh, INT2_TIMER_CONTROL, 194 (TIMER_SEL1 | TIMER_16BIT | TIMER_SWSTROBE)); 195 bus_space_write_1(iot, ioh, INT2_TIMER_CONTROL, 196 (TIMER_SEL2 | TIMER_16BIT | TIMER_SWSTROBE)); 197 wbflush(); 198 delay(4); 199 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR, 0x03); 200 201 if (mach_type == MACH_SGI_IP12) { 202 platform.intr_establish = int2_intr_establish; 203 platform.intr1 = int2_local0_intr; 204 platform.intr2 = int2_local1_intr; 205 platform.intr3 = int_8254_intr0; 206 platform.intr4 = int_8254_intr1; 207 int_8254_cal(); 208 } else { 209 platform.intr_establish = int2_intr_establish; 210 platform.intr0 = int2_local0_intr; 211 platform.intr1 = int2_local1_intr; 212 #ifdef MIPS3 213 curcpu()->ci_cpu_freq = int2_cpu_freq(self); 214 #endif 215 } 216 break; 217 218 default: 219 panic("int0: unsupported machine type %i\n", mach_type); 220 } 221 222 curcpu()->ci_cycles_per_hz = curcpu()->ci_cpu_freq / (2 * hz); 223 curcpu()->ci_divisor_delay = curcpu()->ci_cpu_freq / (2 * 1000000); 224 225 if (mach_type == MACH_SGI_IP22) { 226 /* Wire interrupts 7, 11 to mappable interrupt 0,1 handlers */ 227 intrtab[7].ih_fun = int2_mappable_intr; 228 intrtab[7].ih_arg = (void*) 0; 229 snprintf(intrtab[7].ih_evname, 7, "map0"); 230 231 intrtab[11].ih_fun = int2_mappable_intr; 232 intrtab[11].ih_arg = (void*) 1; 233 snprintf(intrtab[11].ih_evname, 7, "map1"); 234 } 235 236 for (i = 0; i < NINTR; i++) { 237 evcnt_attach_dynamic(&intrtab[i].ih_evcnt, 238 EVCNT_TYPE_INTR, NULL, 239 "int", intrtab[i].ih_evname); 240 } 241 } 242 243 int 244 int2_mappable_intr(void *arg) 245 { 246 int i; 247 int ret; 248 int intnum; 249 uint32_t mstat; 250 uint32_t mmask; 251 int which = (intptr_t)arg; 252 struct sgimips_intrhand *ih; 253 254 ret = 0; 255 mstat = bus_space_read_1(iot, ioh, INT2_MAP_STATUS); 256 mmask = bus_space_read_1(iot, ioh, INT2_MAP_MASK0 + (which << 2)); 257 258 mstat &= mmask; 259 260 for (i = 0; i < 8; i++) { 261 intnum = i + 16 + (which << 3); 262 if (mstat & (1 << i)) { 263 intrtab[intnum].ih_evcnt.ev_count++; 264 for (ih = &intrtab[intnum]; ih != NULL; 265 ih = ih->ih_next) { 266 if (ih->ih_fun != NULL) 267 ret |= (ih->ih_fun)(ih->ih_arg); 268 else 269 printf("int0: unexpected mapped " 270 "interrupt %d\n", intnum); 271 } 272 } 273 } 274 275 return ret; 276 } 277 278 static void 279 int1_local_intr(vaddr_t pc, uint32_t status, uint32_t ipend) 280 { 281 int i; 282 uint16_t stat; 283 uint8_t mask; 284 struct sgimips_intrhand *ih; 285 286 stat = bus_space_read_2(iot, ioh, INT1_LOCAL_STATUS); 287 mask = bus_space_read_1(iot, ioh, INT1_LOCAL_MASK); 288 289 /* for STATUS, a 0 bit means interrupt is pending */ 290 stat = ~stat & mask; 291 292 for (i = 0; stat != 0; i++, stat >>= 1) { 293 if (stat & 1) { 294 intrtab[i].ih_evcnt.ev_count++; 295 for (ih = &intrtab[i]; ih != NULL; ih = ih->ih_next) { 296 if (ih->ih_fun != NULL) 297 (ih->ih_fun)(ih->ih_arg); 298 else 299 printf("int0: unexpected local " 300 "interrupt %d\n", i); 301 } 302 } 303 } 304 } 305 306 void 307 int2_local0_intr(vaddr_t pc, uint32_t status, uint32_t ipending) 308 { 309 int i; 310 uint32_t l0stat; 311 uint32_t l0mask; 312 struct sgimips_intrhand *ih; 313 314 l0stat = bus_space_read_1(iot, ioh, INT2_LOCAL0_STATUS); 315 l0mask = bus_space_read_1(iot, ioh, INT2_LOCAL0_MASK); 316 317 l0stat &= l0mask; 318 319 for (i = 0; i < 8; i++) { 320 if (l0stat & (1 << i)) { 321 intrtab[i].ih_evcnt.ev_count++; 322 for (ih = &intrtab[i]; ih != NULL; ih = ih->ih_next) { 323 if (ih->ih_fun != NULL) 324 (ih->ih_fun)(ih->ih_arg); 325 else 326 printf("int0: unexpected local0 " 327 "interrupt %d\n", i); 328 } 329 } 330 } 331 } 332 333 void 334 int2_local1_intr(vaddr_t pc, uint32_t status, uint32_t ipending) 335 { 336 int i; 337 uint32_t l1stat; 338 uint32_t l1mask; 339 struct sgimips_intrhand *ih; 340 341 l1stat = bus_space_read_1(iot, ioh, INT2_LOCAL1_STATUS); 342 l1mask = bus_space_read_1(iot, ioh, INT2_LOCAL1_MASK); 343 344 l1stat &= l1mask; 345 346 for (i = 0; i < 8; i++) { 347 if (l1stat & (1 << i)) { 348 intrtab[i].ih_evcnt.ev_count++; 349 for (ih = &intrtab[8+i]; ih != NULL; ih = ih->ih_next) { 350 if (ih->ih_fun != NULL) 351 (ih->ih_fun)(ih->ih_arg); 352 else 353 printf("int0: unexpected local1 " 354 " interrupt %x\n", 8 + i); 355 } 356 } 357 } 358 } 359 360 void * 361 int1_intr_establish(int level, int ipl, int (*handler) (void *), void *arg) 362 { 363 uint8_t mask; 364 365 if (level < 0 || level >= NINTR) 366 panic("invalid interrupt level"); 367 368 if (intrtab[level].ih_fun == NULL) { 369 intrtab[level].ih_fun = handler; 370 intrtab[level].ih_arg = arg; 371 intrtab[level].ih_next = NULL; 372 } else { 373 struct sgimips_intrhand *n, *ih; 374 375 ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 376 if (ih == NULL) { 377 printf("int0: can't allocate handler\n"); 378 return (void *)NULL; 379 } 380 381 ih->ih_fun = handler; 382 ih->ih_arg = arg; 383 ih->ih_next = NULL; 384 385 for (n = &intrtab[level]; n->ih_next != NULL; n = n->ih_next) 386 ; 387 388 n->ih_next = ih; 389 390 return NULL; /* vector already set */ 391 } 392 393 if (level < 8) { 394 mask = bus_space_read_1(iot, ioh, INT1_LOCAL_MASK); 395 mask |= (1 << level); 396 bus_space_write_1(iot, ioh, INT1_LOCAL_MASK, mask); 397 } else { 398 printf("int0: level >= 16 (%d)\n", level); 399 } 400 401 return NULL; 402 } 403 404 void * 405 int2_intr_establish(int level, int ipl, int (*handler) (void *), void *arg) 406 { 407 uint32_t mask; 408 409 if (level < 0 || level >= NINTR) 410 panic("invalid interrupt level"); 411 412 if (intrtab[level].ih_fun == NULL) { 413 intrtab[level].ih_fun = handler; 414 intrtab[level].ih_arg = arg; 415 intrtab[level].ih_next = NULL; 416 } else { 417 struct sgimips_intrhand *n, *ih; 418 419 ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 420 if (ih == NULL) { 421 printf("int0: can't allocate handler\n"); 422 return NULL; 423 } 424 425 ih->ih_fun = handler; 426 ih->ih_arg = arg; 427 ih->ih_next = NULL; 428 429 for (n = &intrtab[level]; n->ih_next != NULL; n = n->ih_next) 430 ; 431 432 n->ih_next = ih; 433 434 return NULL; /* vector already set */ 435 } 436 437 if (level < 8) { 438 mask = bus_space_read_1(iot, ioh, INT2_LOCAL0_MASK); 439 mask |= (1 << level); 440 bus_space_write_1(iot, ioh, INT2_LOCAL0_MASK, mask); 441 } else if (level < 16) { 442 mask = bus_space_read_1(iot, ioh, INT2_LOCAL1_MASK); 443 mask |= (1 << (level - 8)); 444 bus_space_write_1(iot, ioh, INT2_LOCAL1_MASK, mask); 445 } else if (level < 24) { 446 /* Map0 interrupt maps to l0 bit 7, so turn that on too */ 447 mask = bus_space_read_1(iot, ioh, INT2_LOCAL0_MASK); 448 mask |= (1 << 7); 449 bus_space_write_1(iot, ioh, INT2_LOCAL0_MASK, mask); 450 451 mask = bus_space_read_1(iot, ioh, INT2_MAP_MASK0); 452 mask |= (1 << (level - 16)); 453 bus_space_write_1(iot, ioh, INT2_MAP_MASK0, mask); 454 } else { 455 /* Map1 interrupt maps to l1 bit 3, so turn that on too */ 456 mask = bus_space_read_1(iot, ioh, INT2_LOCAL1_MASK); 457 mask |= (1 << 3); 458 bus_space_write_1(iot, ioh, INT2_LOCAL1_MASK, mask); 459 460 mask = bus_space_read_1(iot, ioh, INT2_MAP_MASK1); 461 mask |= (1 << (level - 24)); 462 bus_space_write_1(iot, ioh, INT2_MAP_MASK1, mask); 463 } 464 465 return NULL; 466 } 467 468 #ifdef MIPS3 469 static u_long 470 int2_cpu_freq(device_t self) 471 { 472 int i; 473 unsigned long cps; 474 unsigned long ctrdiff[3]; 475 476 /* calibrate timer */ 477 int2_cal_timer(); 478 479 cps = 0; 480 for (i = 0; 481 i < sizeof(ctrdiff) / sizeof(ctrdiff[0]); i++) { 482 do { 483 ctrdiff[i] = int2_cal_timer(); 484 } while (ctrdiff[i] == 0); 485 486 cps += ctrdiff[i]; 487 } 488 489 cps = cps / (sizeof(ctrdiff) / sizeof(ctrdiff[0])); 490 491 printf("%s: bus %luMHz, CPU %luMHz\n", 492 device_xname(self), cps / 10000, cps / 5000); 493 494 /* R4k/R4400/R4600/R5k count at half CPU frequency */ 495 return (2 * cps * hz); 496 } 497 498 static u_long 499 int2_cal_timer(void) 500 { 501 int s; 502 int roundtime; 503 int sampletime; 504 int msb; 505 unsigned long startctr, endctr; 506 507 /* 508 * NOTE: HZ must be greater than 15 for this to work, as otherwise 509 * we'll overflow the counter. We round the answer to nearest 1 510 * MHz of the master (2x) clock. 511 */ 512 roundtime = (1000000 / hz) / 2; 513 sampletime = (1000000 / hz) + 0xff; 514 515 s = splhigh(); 516 517 bus_space_write_1(iot, ioh, INT2_TIMER_CONTROL, 518 (TIMER_SEL2 | TIMER_16BIT | TIMER_RATEGEN)); 519 bus_space_write_1(iot, ioh, INT2_TIMER_2, (sampletime & 0xff)); 520 bus_space_write_1(iot, ioh, INT2_TIMER_2, (sampletime >> 8)); 521 522 startctr = mips3_cp0_count_read(); 523 524 /* Wait for the MSB to count down to zero */ 525 do { 526 bus_space_write_1(iot, ioh, INT2_TIMER_CONTROL, TIMER_SEL2); 527 (void)bus_space_read_1(iot, ioh, INT2_TIMER_2); 528 msb = bus_space_read_1(iot, ioh, INT2_TIMER_2) & 0xff; 529 530 endctr = mips3_cp0_count_read(); 531 } while (msb); 532 533 /* Turn off timer */ 534 bus_space_write_1(iot, ioh, INT2_TIMER_CONTROL, 535 (TIMER_SEL2 | TIMER_16BIT | TIMER_SWSTROBE)); 536 537 splx(s); 538 539 return (endctr - startctr) / roundtime * roundtime; 540 } 541 #endif /* MIPS3 */ 542 543 /* 544 * A master clock is wired to TIMER_2, which in turn clocks the two other 545 * timers. The master frequencies are as follows: 546 * IP6, IP10: 3.6864MHz 547 * IP12, IP20, IP22: 1MHz 548 * IP17: 10MHz 549 * 550 * TIMER_0 and TIMER_1 interrupts are tied to MIPS interrupts as follows: 551 * IP6, IP10: TIMER_0: INT2, TIMER_1: INT4 552 * IP12: TIMER_0: INT3, TIMER_1: INT4 553 * IP17, IP20, IP22: TIMER_0: INT2, TIMER_1: INT3 554 * 555 * NB: Apparently int2 doesn't like counting down from one, but two works. 556 */ 557 void 558 int_8254_cal(void) 559 { 560 bus_size_t timer_control, timer_0, timer_1, timer_2; 561 int s; 562 563 switch (mach_type) { 564 case MACH_SGI_IP6 | MACH_SGI_IP10: 565 int_8254_timecounter.tc_frequency = 3686400 / 8; 566 timer_control = INT1_TIMER_CONTROL; 567 timer_0 = INT1_TIMER_0; 568 timer_1 = INT1_TIMER_1; 569 timer_2 = INT1_TIMER_2; 570 break; 571 572 case MACH_SGI_IP12: 573 int_8254_timecounter.tc_frequency = 1000000 / 8; 574 timer_control = INT2_TIMER_CONTROL; 575 timer_0 = INT2_TIMER_0; 576 timer_1 = INT2_TIMER_1; 577 timer_2 = INT2_TIMER_2; 578 break; 579 580 default: 581 panic("int_8254_cal"); 582 } 583 584 s = splhigh(); 585 586 /* Timer0 is our hz. */ 587 bus_space_write_1(iot, ioh, timer_control, 588 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 589 bus_space_write_1(iot, ioh, timer_0, 590 (int_8254_timecounter.tc_frequency / hz) % 256); 591 wbflush(); 592 delay(4); 593 bus_space_write_1(iot, ioh, timer_0, 594 (int_8254_timecounter.tc_frequency / hz) / 256); 595 596 /* Timer1 is for timecounting. */ 597 bus_space_write_1(iot, ioh, timer_control, 598 TIMER_SEL1 | TIMER_RATEGEN | TIMER_16BIT); 599 bus_space_write_1(iot, ioh, timer_1, 0xff); 600 wbflush(); 601 delay(4); 602 bus_space_write_1(iot, ioh, timer_1, 0xff); 603 604 /* Timer2 clocks timer0 and timer1. */ 605 bus_space_write_1(iot, ioh, timer_control, 606 TIMER_SEL2 | TIMER_RATEGEN | TIMER_16BIT); 607 bus_space_write_1(iot, ioh, timer_2, 8); 608 wbflush(); 609 delay(4); 610 bus_space_write_1(iot, ioh, timer_2, 0); 611 612 splx(s); 613 614 tc_init(&int_8254_timecounter); 615 } 616 617 static u_int 618 int_8254_get_timecount(struct timecounter *tc) 619 { 620 int s; 621 u_int count; 622 u_char lo, hi; 623 624 s = splhigh(); 625 626 switch (mach_type) { 627 case MACH_SGI_IP6 | MACH_SGI_IP10: 628 bus_space_write_1(iot, ioh, INT1_TIMER_CONTROL, 629 TIMER_SEL1 | TIMER_LATCH); 630 lo = bus_space_read_1(iot, ioh, INT1_TIMER_1); 631 hi = bus_space_read_1(iot, ioh, INT1_TIMER_1); 632 break; 633 634 case MACH_SGI_IP12: 635 bus_space_write_1(iot, ioh, INT2_TIMER_CONTROL, 636 TIMER_SEL1 | TIMER_LATCH); 637 lo = bus_space_read_1(iot, ioh, INT2_TIMER_1); 638 hi = bus_space_read_1(iot, ioh, INT2_TIMER_1); 639 break; 640 641 default: 642 panic("int_8254_get_timecount"); 643 } 644 645 count = 0xffff - ((hi << 8) | lo); 646 splx(s); 647 648 return (int_8254_tc_count + count); 649 } 650 651 static void 652 int_8254_intr0(vaddr_t pc, uint32_t status, uint32_t ipending) 653 { 654 struct clockframe cf; 655 656 cf.pc = pc; 657 cf.sr = status; 658 cf.intr = (curcpu()->ci_idepth > 1); 659 660 hardclock(&cf); 661 662 switch (mach_type) { 663 case MACH_SGI_IP6 | MACH_SGI_IP10: 664 bus_space_read_1(iot, ioh, INT1_TIMER_0_ACK); 665 break; 666 667 case MACH_SGI_IP12: 668 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR, 0x01); 669 break; 670 671 default: 672 panic("int_8254_intr0"); 673 } 674 } 675 676 static void 677 int_8254_intr1(vaddr_t pc, uint32_t status, uint32_t ipending) 678 { 679 int s; 680 681 s = splhigh(); 682 683 int_8254_tc_count += 0xffff; 684 switch (mach_type) { 685 case MACH_SGI_IP6 | MACH_SGI_IP10: 686 bus_space_read_1(iot, ioh, INT1_TIMER_1_ACK); 687 break; 688 689 case MACH_SGI_IP12: 690 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR, 0x02); 691 break; 692 693 default: 694 panic("int_8254_intr1"); 695 } 696 697 splx(s); 698 } 699 700 void 701 int2_wait_fifo(uint32_t flag) 702 { 703 704 if (ioh == 0) 705 delay(5000); 706 else 707 while (bus_space_read_1(iot, ioh, INT2_LOCAL0_STATUS) & flag) 708 ; 709 } 710
Indexes created Thu Oct 02 14:10:14 GMT 2025