int.c revision 1.4
1 /* $NetBSD: int.c,v 1.4 2004/03/25 15:06:37 pooka Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Christopher SEKIYA 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * INT/INT2/INT3 interrupt controller (used in ip1x and ip2x-class machines) 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: int.c,v 1.4 2004/03/25 15:06:37 pooka Exp $"); 36 37 #include "opt_cputype.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 45 #include <dev/ic/i8253reg.h> 46 #include <machine/sysconf.h> 47 #include <machine/machtype.h> 48 #include <machine/bus.h> 49 #include <mips/locore.h> 50 51 #include <mips/cache.h> 52 53 #include <sgimips/dev/int2reg.h> 54 #include <sgimips/dev/int2var.h> 55 56 static bus_space_handle_t ioh; 57 static bus_space_tag_t iot; 58 59 struct int_softc { 60 struct device sc_dev; 61 }; 62 63 64 static int int_match(struct device *, struct cfdata *, void *); 65 static void int_attach(struct device *, struct device *, void *); 66 void int_local0_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 67 void int_local1_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 68 int int_mappable_intr(void *); 69 void int_intr(u_int, u_int, u_int, u_int); 70 void *int_intr_establish(int, int, int (*)(void *), void *); 71 unsigned long int_cal_timer(void); 72 void int_8254_cal(void); 73 74 CFATTACH_DECL(int, sizeof(struct int_softc), 75 int_match, int_attach, NULL, NULL); 76 77 static int 78 int_match(struct device *parent, struct cfdata *match, void *aux) 79 { 80 if ( (mach_type == MACH_SGI_IP12) || (mach_type == MACH_SGI_IP20) || 81 (mach_type == MACH_SGI_IP22) ) 82 return 1; 83 84 return 0; 85 } 86 87 static void 88 int_attach(struct device *parent, struct device *self, void *aux) 89 { 90 u_int32_t address; 91 92 if (mach_type == MACH_SGI_IP12) 93 address = INT_IP12; 94 else if (mach_type == MACH_SGI_IP20) 95 address = INT_IP20; 96 else if (mach_type == MACH_SGI_IP22) { 97 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 98 address = INT_IP22; 99 else 100 address = INT_IP24; 101 } 102 else 103 panic("\nint0: passed match, but failed attach?"); 104 105 printf(" addr 0x%x", address); 106 107 bus_space_map(iot, address, 0, 0, &ioh); 108 iot = SGIMIPS_BUS_SPACE_NORMAL; 109 110 /* Clean out interrupt masks */ 111 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, 0); 112 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, 0); 113 bus_space_write_4(iot, ioh, INT2_MAP_MASK0, 0); 114 bus_space_write_4(iot, ioh, INT2_MAP_MASK1, 0); 115 116 /* Reset timer interrupts */ 117 bus_space_write_4(iot, ioh, INT2_TIMER_CLEAR, 0x03); 118 119 switch (mach_type) { 120 case MACH_SGI_IP12: 121 platform.intr1 = int_local0_intr; 122 platform.intr2 = int_local1_intr; 123 int_8254_cal(); 124 break; 125 #ifdef MIPS3 126 case MACH_SGI_IP20: 127 case MACH_SGI_IP22: 128 { 129 int i; 130 unsigned long cps; 131 unsigned long ctrdiff[3]; 132 133 platform.intr0 = int_local0_intr; 134 platform.intr1 = int_local1_intr; 135 136 /* calibrate timer */ 137 int_cal_timer(); 138 139 cps = 0; 140 for (i = 0; i < sizeof(ctrdiff) / sizeof(ctrdiff[0]); i++) { 141 do { 142 ctrdiff[i] = int_cal_timer(); 143 } while (ctrdiff[i] == 0); 144 145 cps += ctrdiff[i]; 146 } 147 148 cps = cps / (sizeof(ctrdiff) / sizeof(ctrdiff[0])); 149 150 printf(": bus %luMHz, CPU %luMHz", cps / 10000, cps / 5000); 151 152 /* R4k/R4400/R4600/R5k count at half CPU frequency */ 153 curcpu()->ci_cpu_freq = 2 * cps * hz; 154 } 155 #endif /* MIPS3 */ 156 157 break; 158 default: 159 panic("int0: unsupported machine type %i\n", mach_type); 160 break; 161 } 162 163 printf("\n"); 164 165 curcpu()->ci_cycles_per_hz = curcpu()->ci_cpu_freq / (2 * hz); 166 curcpu()->ci_divisor_delay = curcpu()->ci_cpu_freq / (2 * 1000000); 167 MIPS_SET_CI_RECIPRICAL(curcpu()); 168 169 if (mach_type == MACH_SGI_IP22) { 170 /* Wire interrupts 7, 11 to mappable interrupt 0,1 handlers */ 171 intrtab[7].ih_fun = int_mappable_intr; 172 intrtab[7].ih_arg = (void*) 0; 173 174 intrtab[11].ih_fun = int_mappable_intr; 175 intrtab[11].ih_arg = (void*) 1; 176 } 177 178 platform.intr_establish = int_intr_establish; 179 } 180 181 int 182 int_mappable_intr(void *arg) 183 { 184 int i; 185 int ret; 186 int intnum; 187 u_int32_t mstat; 188 u_int32_t mmask; 189 int which = (int)arg; 190 191 ret = 0; 192 mstat = bus_space_read_4(iot, ioh, INT2_MAP_STATUS); 193 mmask = bus_space_read_4(iot, ioh, INT2_MAP_MASK0 + (which << 2)); 194 195 mstat &= mmask; 196 197 for (i = 0; i < 8; i++) { 198 intnum = i + 16 + (which << 3); 199 if (mstat & (1 << i)) { 200 if (intrtab[intnum].ih_fun != NULL) 201 ret |= (intrtab[intnum].ih_fun) 202 (intrtab[intnum].ih_arg); 203 else 204 printf("int0: unexpected mapped interrupt %d\n", 205 intnum); 206 } 207 } 208 209 return ret; 210 } 211 212 void 213 int_local0_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending) 214 { 215 int i; 216 int ret; 217 u_int32_t l0stat; 218 u_int32_t l0mask; 219 220 ret = 0; 221 l0stat = bus_space_read_4(iot, ioh, INT2_LOCAL0_STATUS); 222 l0mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 223 224 l0stat &= l0mask; 225 226 for (i = 0; i < 8; i++) { 227 if (l0stat & (1 << i)) { 228 if (intrtab[i].ih_fun != NULL) 229 ret |= (intrtab[i].ih_fun)(intrtab[i].ih_arg); 230 else 231 printf("int0: unexpected local0 interrupt %d\n", i); 232 } 233 } 234 } 235 236 void 237 int_local1_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending) 238 { 239 int i; 240 int ret; 241 u_int32_t l1stat; 242 u_int32_t l1mask; 243 244 l1stat = bus_space_read_4(iot, ioh, INT2_LOCAL1_STATUS); 245 l1mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 246 247 l1stat &= l1mask; 248 249 ret = 0; 250 for (i = 0; i < 8; i++) { 251 if (l1stat & (1 << i)) { 252 if (intrtab[8 + i].ih_fun != NULL) 253 ret |= (intrtab[8 + i].ih_fun) 254 (intrtab[8 + i].ih_arg); 255 else 256 printf("int0: unexpected local1 interrupt %x\n", 257 8 + i ); 258 } 259 } 260 } 261 262 void * 263 int_intr_establish(int level, int ipl, int (*handler) (void *), void *arg) 264 { 265 u_int32_t mask; 266 267 if (level < 0 || level >= NINTR) 268 panic("invalid interrupt level"); 269 270 if (intrtab[level].ih_fun != NULL) 271 { 272 printf("int0: cannot share interrupts yet.\n"); 273 return (void *)NULL; 274 } 275 276 intrtab[level].ih_fun = handler; 277 intrtab[level].ih_arg = arg; 278 279 if (level < 8) { 280 mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 281 mask |= (1 << level); 282 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, mask); 283 } else if (level < 16) { 284 mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 285 mask |= (1 << (level - 8)); 286 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, mask); 287 } else if (level < 24) { 288 /* Map0 interrupt maps to l0 bit 7, so turn that on too */ 289 mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 290 mask |= (1 << 7); 291 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, mask); 292 293 mask = bus_space_read_4(iot, ioh, INT2_MAP_MASK0); 294 mask |= (1 << (level - 16)); 295 bus_space_write_4(iot, ioh, INT2_MAP_MASK0, mask); 296 } else { 297 /* Map1 interrupt maps to l1 bit 3, so turn that on too */ 298 mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 299 mask |= (1 << 3); 300 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, mask); 301 302 mask = bus_space_read_4(iot, ioh, INT2_MAP_MASK1); 303 mask |= (1 << (level - 24)); 304 bus_space_write_4(iot, ioh, INT2_MAP_MASK1, mask); 305 } 306 307 return (void *)NULL; 308 } 309 310 #ifdef MIPS3 311 unsigned long 312 int_cal_timer(void) 313 { 314 int s; 315 int roundtime; 316 int sampletime; 317 int startmsb, lsb, msb; 318 unsigned long startctr, endctr; 319 320 /* 321 * NOTE: HZ must be greater than 15 for this to work, as otherwise 322 * we'll overflow the counter. We round the answer to hearest 1 323 * MHz of the master (2x) clock. 324 */ 325 roundtime = (1000000 / hz) / 2; 326 sampletime = (1000000 / hz) + 0xff; 327 startmsb = (sampletime >> 8); 328 329 s = splhigh(); 330 331 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, 332 ( TIMER_SEL2 | TIMER_16BIT | TIMER_RATEGEN) ); 333 bus_space_write_4(iot, ioh, INT2_TIMER_2, (sampletime & 0xff)); 334 bus_space_write_4(iot, ioh, INT2_TIMER_2, (sampletime >> 8)); 335 336 startctr = mips3_cp0_count_read(); 337 338 /* Wait for the MSB to count down to zero */ 339 do { 340 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, TIMER_SEL2 ); 341 lsb = bus_space_read_4(iot, ioh, INT2_TIMER_2) & 0xff; 342 msb = bus_space_read_4(iot, ioh, INT2_TIMER_2) & 0xff; 343 344 endctr = mips3_cp0_count_read(); 345 } while (msb); 346 347 /* Turn off timer */ 348 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, 349 ( TIMER_SEL2 | TIMER_16BIT | TIMER_SWSTROBE) ); 350 351 splx(s); 352 353 return (endctr - startctr) / roundtime * roundtime; 354 } 355 #endif /* MIPS3 */ 356 357 void 358 int_8254_cal(void) 359 { 360 int s; 361 362 s = splhigh(); 363 364 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 15, 365 TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT); 366 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 3, (20000 / hz) % 256); 367 wbflush(); 368 delay(4); 369 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 3, (20000 / hz) / 256); 370 371 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 15, 372 TIMER_SEL2|TIMER_RATEGEN|TIMER_16BIT); 373 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 11, 50); 374 wbflush(); 375 delay(4); 376 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 11, 0); 377 splx(s); 378 } 379 380 void 381 int2_wait_fifo(u_int32_t flag) 382 { 383 while (bus_space_read_4(iot, ioh, INT2_LOCAL0_STATUS) & flag) 384 ; 385 } 386
Indexes created Tue Sep 23 23:09:58 GMT 2025