int.c revision 1.6
1 /* $NetBSD: int.c,v 1.6 2004/03/25 15:16:11 pooka Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Christopher SEKIYA 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * INT/INT2/INT3 interrupt controller (used in Indy's, Indigo's, etc..) 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: int.c,v 1.6 2004/03/25 15:16:11 pooka Exp $"); 36 37 #include "opt_cputype.h" 38 39 #include <sys/param.h> 40 #include <sys/proc.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 45 #include <dev/ic/i8253reg.h> 46 #include <machine/sysconf.h> 47 #include <machine/machtype.h> 48 #include <machine/bus.h> 49 #include <mips/locore.h> 50 51 #include <mips/cache.h> 52 53 #include <sgimips/dev/int2reg.h> 54 #include <sgimips/dev/int2var.h> 55 56 static bus_space_handle_t ioh; 57 static bus_space_tag_t iot; 58 59 struct int_softc { 60 struct device sc_dev; 61 }; 62 63 64 static int int_match(struct device *, struct cfdata *, void *); 65 static void int_attach(struct device *, struct device *, void *); 66 void int_local0_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 67 void int_local1_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 68 int int_mappable_intr(void *); 69 void int_intr(u_int, u_int, u_int, u_int); 70 void *int_intr_establish(int, int, int (*)(void *), void *); 71 unsigned long int_cal_timer(void); 72 void int_8254_cal(void); 73 74 CFATTACH_DECL(int, sizeof(struct int_softc), 75 int_match, int_attach, NULL, NULL); 76 77 static int 78 int_match(struct device *parent, struct cfdata *match, void *aux) 79 { 80 81 if ((mach_type == MACH_SGI_IP12) || (mach_type == MACH_SGI_IP20) || 82 (mach_type == MACH_SGI_IP22) ) 83 return 1; 84 85 return 0; 86 } 87 88 static void 89 int_attach(struct device *parent, struct device *self, void *aux) 90 { 91 u_int32_t address; 92 93 if (mach_type == MACH_SGI_IP12) 94 address = INT_IP12; 95 else if (mach_type == MACH_SGI_IP20) 96 address = INT_IP20; 97 else if (mach_type == MACH_SGI_IP22) { 98 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 99 address = INT_IP22; 100 else 101 address = INT_IP24; 102 } 103 else 104 panic("\nint0: passed match, but failed attach?"); 105 106 printf(" addr 0x%x", address); 107 108 bus_space_map(iot, address, 0, 0, &ioh); 109 iot = SGIMIPS_BUS_SPACE_NORMAL; 110 111 /* Clean out interrupt masks */ 112 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, 0); 113 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, 0); 114 bus_space_write_4(iot, ioh, INT2_MAP_MASK0, 0); 115 bus_space_write_4(iot, ioh, INT2_MAP_MASK1, 0); 116 117 /* Reset timer interrupts */ 118 bus_space_write_4(iot, ioh, INT2_TIMER_CLEAR, 0x03); 119 120 switch (mach_type) { 121 case MACH_SGI_IP12: 122 platform.intr1 = int_local0_intr; 123 platform.intr2 = int_local1_intr; 124 int_8254_cal(); 125 break; 126 #ifdef MIPS3 127 case MACH_SGI_IP20: 128 case MACH_SGI_IP22: 129 { 130 int i; 131 unsigned long cps; 132 unsigned long ctrdiff[3]; 133 134 platform.intr0 = int_local0_intr; 135 platform.intr1 = int_local1_intr; 136 137 /* calibrate timer */ 138 int_cal_timer(); 139 140 cps = 0; 141 for (i = 0; 142 i < sizeof(ctrdiff) / sizeof(ctrdiff[0]); i++) { 143 do { 144 ctrdiff[i] = int_cal_timer(); 145 } while (ctrdiff[i] == 0); 146 147 cps += ctrdiff[i]; 148 } 149 150 cps = cps / (sizeof(ctrdiff) / sizeof(ctrdiff[0])); 151 152 printf(": bus %luMHz, CPU %luMHz", 153 cps / 10000, cps / 5000); 154 155 /* R4k/R4400/R4600/R5k count at half CPU frequency */ 156 curcpu()->ci_cpu_freq = 2 * cps * hz; 157 } 158 #endif /* MIPS3 */ 159 160 break; 161 default: 162 panic("int0: unsupported machine type %i\n", mach_type); 163 break; 164 } 165 166 printf("\n"); 167 168 curcpu()->ci_cycles_per_hz = curcpu()->ci_cpu_freq / (2 * hz); 169 curcpu()->ci_divisor_delay = curcpu()->ci_cpu_freq / (2 * 1000000); 170 MIPS_SET_CI_RECIPRICAL(curcpu()); 171 172 if (mach_type == MACH_SGI_IP22) { 173 /* Wire interrupts 7, 11 to mappable interrupt 0,1 handlers */ 174 intrtab[7].ih_fun = int_mappable_intr; 175 intrtab[7].ih_arg = (void*) 0; 176 177 intrtab[11].ih_fun = int_mappable_intr; 178 intrtab[11].ih_arg = (void*) 1; 179 } 180 181 platform.intr_establish = int_intr_establish; 182 } 183 184 int 185 int_mappable_intr(void *arg) 186 { 187 int i; 188 int ret; 189 int intnum; 190 u_int32_t mstat; 191 u_int32_t mmask; 192 int which = (int)arg; 193 194 ret = 0; 195 mstat = bus_space_read_4(iot, ioh, INT2_MAP_STATUS); 196 mmask = bus_space_read_4(iot, ioh, INT2_MAP_MASK0 + (which << 2)); 197 198 mstat &= mmask; 199 200 for (i = 0; i < 8; i++) { 201 intnum = i + 16 + (which << 3); 202 if (mstat & (1 << i)) { 203 if (intrtab[intnum].ih_fun != NULL) 204 ret |= (intrtab[intnum].ih_fun) 205 (intrtab[intnum].ih_arg); 206 else 207 printf("int0: unexpected mapped interrupt %d\n", 208 intnum); 209 } 210 } 211 212 return ret; 213 } 214 215 void 216 int_local0_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, 217 u_int32_t ipending) 218 { 219 int i; 220 int ret; 221 u_int32_t l0stat; 222 u_int32_t l0mask; 223 224 ret = 0; 225 l0stat = bus_space_read_4(iot, ioh, INT2_LOCAL0_STATUS); 226 l0mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 227 228 l0stat &= l0mask; 229 230 for (i = 0; i < 8; i++) { 231 if (l0stat & (1 << i)) { 232 if (intrtab[i].ih_fun != NULL) 233 ret |= (intrtab[i].ih_fun)(intrtab[i].ih_arg); 234 else 235 printf("int0: unexpected local0 interrupt %d\n", 236 i); 237 } 238 } 239 } 240 241 void 242 int_local1_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, 243 u_int32_t ipending) 244 { 245 int i; 246 int ret; 247 u_int32_t l1stat; 248 u_int32_t l1mask; 249 250 l1stat = bus_space_read_4(iot, ioh, INT2_LOCAL1_STATUS); 251 l1mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 252 253 l1stat &= l1mask; 254 255 ret = 0; 256 for (i = 0; i < 8; i++) { 257 if (l1stat & (1 << i)) { 258 if (intrtab[8 + i].ih_fun != NULL) 259 ret |= (intrtab[8 + i].ih_fun) 260 (intrtab[8 + i].ih_arg); 261 else 262 printf("int0: unexpected local1 interrupt %x\n", 263 8 + i); 264 } 265 } 266 } 267 268 void * 269 int_intr_establish(int level, int ipl, int (*handler) (void *), void *arg) 270 { 271 u_int32_t mask; 272 273 if (level < 0 || level >= NINTR) 274 panic("invalid interrupt level"); 275 276 if (intrtab[level].ih_fun != NULL) 277 { 278 printf("int0: cannot share interrupts yet.\n"); 279 return (void *)NULL; 280 } 281 282 intrtab[level].ih_fun = handler; 283 intrtab[level].ih_arg = arg; 284 285 if (level < 8) { 286 mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 287 mask |= (1 << level); 288 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, mask); 289 } else if (level < 16) { 290 mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 291 mask |= (1 << (level - 8)); 292 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, mask); 293 } else if (level < 24) { 294 /* Map0 interrupt maps to l0 bit 7, so turn that on too */ 295 mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK); 296 mask |= (1 << 7); 297 bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, mask); 298 299 mask = bus_space_read_4(iot, ioh, INT2_MAP_MASK0); 300 mask |= (1 << (level - 16)); 301 bus_space_write_4(iot, ioh, INT2_MAP_MASK0, mask); 302 } else { 303 /* Map1 interrupt maps to l1 bit 3, so turn that on too */ 304 mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK); 305 mask |= (1 << 3); 306 bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, mask); 307 308 mask = bus_space_read_4(iot, ioh, INT2_MAP_MASK1); 309 mask |= (1 << (level - 24)); 310 bus_space_write_4(iot, ioh, INT2_MAP_MASK1, mask); 311 } 312 313 return (void *)NULL; 314 } 315 316 #ifdef MIPS3 317 unsigned long 318 int_cal_timer(void) 319 { 320 int s; 321 int roundtime; 322 int sampletime; 323 int startmsb, lsb, msb; 324 unsigned long startctr, endctr; 325 326 /* 327 * NOTE: HZ must be greater than 15 for this to work, as otherwise 328 * we'll overflow the counter. We round the answer to hearest 1 329 * MHz of the master (2x) clock. 330 */ 331 roundtime = (1000000 / hz) / 2; 332 sampletime = (1000000 / hz) + 0xff; 333 startmsb = (sampletime >> 8); 334 335 s = splhigh(); 336 337 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, 338 ( TIMER_SEL2 | TIMER_16BIT | TIMER_RATEGEN) ); 339 bus_space_write_4(iot, ioh, INT2_TIMER_2, (sampletime & 0xff)); 340 bus_space_write_4(iot, ioh, INT2_TIMER_2, (sampletime >> 8)); 341 342 startctr = mips3_cp0_count_read(); 343 344 /* Wait for the MSB to count down to zero */ 345 do { 346 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, TIMER_SEL2 ); 347 lsb = bus_space_read_4(iot, ioh, INT2_TIMER_2) & 0xff; 348 msb = bus_space_read_4(iot, ioh, INT2_TIMER_2) & 0xff; 349 350 endctr = mips3_cp0_count_read(); 351 } while (msb); 352 353 /* Turn off timer */ 354 bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, 355 ( TIMER_SEL2 | TIMER_16BIT | TIMER_SWSTROBE) ); 356 357 splx(s); 358 359 return (endctr - startctr) / roundtime * roundtime; 360 } 361 #endif /* MIPS3 */ 362 363 void 364 int_8254_cal(void) 365 { 366 int s; 367 368 s = splhigh(); 369 370 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 15, 371 TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT); 372 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 3, (20000 / hz) % 256); 373 wbflush(); 374 delay(4); 375 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 3, (20000 / hz) / 256); 376 377 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 15, 378 TIMER_SEL2|TIMER_RATEGEN|TIMER_16BIT); 379 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 11, 50); 380 wbflush(); 381 delay(4); 382 bus_space_write_1(iot, ioh, INT2_TIMER_CLEAR + 11, 0); 383 splx(s); 384 } 385 386 void 387 int2_wait_fifo(u_int32_t flag) 388 { 389 while (bus_space_read_4(iot, ioh, INT2_LOCAL0_STATUS) & flag) 390 ; 391 } 392
Indexes created Tue Sep 23 07:09:52 GMT 2025