pic.c revision 1.11
1 /* $NetBSD: pic.c,v 1.11 2006/08/30 23:44:52 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Steve Rumble 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: pic.c,v 1.11 2006/08/30 23:44:52 rumble Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/device.h> 35 #include <sys/systm.h> 36 37 #include <machine/cpu.h> 38 #include <machine/locore.h> 39 #include <machine/autoconf.h> 40 #include <machine/bus.h> 41 #include <machine/machtype.h> 42 #include <machine/sysconf.h> 43 44 #include <sgimips/dev/picreg.h> 45 46 #include <sgimips/gio/giovar.h> 47 48 #include "locators.h" 49 50 struct pic_softc { 51 struct device sc_dev; 52 53 bus_space_tag_t iot; 54 bus_space_handle_t ioh; 55 56 }; 57 58 static int pic_match(struct device *, struct cfdata *, void *); 59 static void pic_attach(struct device *, struct device *, void *); 60 static int pic_print(void *, const char *); 61 static void pic_bus_reset(void); 62 static void pic_watchdog_enable(void); 63 static void pic_watchdog_disable(void); 64 static void pic_watchdog_tickle(void); 65 66 CFATTACH_DECL(pic, sizeof(struct pic_softc), 67 pic_match, pic_attach, NULL, NULL); 68 69 struct pic_attach_args { 70 const char *iaa_name; 71 72 bus_space_tag_t iaa_st; 73 bus_space_handle_t iaa_sh; 74 }; 75 76 int pic_gio32_arb_config(int, uint32_t); 77 78 static struct pic_softc psc; 79 80 static int 81 pic_match(struct device * parent, struct cfdata * match, void *aux) 82 { 83 /* 84 * PIC exists on IP12 systems. It appears to be the immediate 85 * ancestor of the mc, for mips1 processors. 86 */ 87 if (mach_type == MACH_SGI_IP12) 88 return (1); 89 else 90 return (0); 91 } 92 93 static void 94 pic_attach(struct device * parent, struct device * self, void *aux) 95 { 96 u_int32_t reg; 97 struct pic_attach_args iaa; 98 struct mainbus_attach_args *ma = aux; 99 100 psc.iot = SGIMIPS_BUS_SPACE_HPC; 101 if (bus_space_map(psc.iot, ma->ma_addr, 0, 102 BUS_SPACE_MAP_LINEAR, &psc.ioh)) 103 panic("pic_attach: could not allocate memory\n"); 104 105 platform.bus_reset = pic_bus_reset; 106 platform.watchdog_enable = pic_watchdog_enable; 107 platform.watchdog_disable = pic_watchdog_disable; 108 platform.watchdog_reset = pic_watchdog_tickle; 109 110 reg = bus_space_read_4(psc.iot, psc.ioh, PIC_SYSID); 111 reg = (reg >> PIC_SYSID_REVSHIFT) & PIC_SYSID_REVMASK; 112 printf("\npic0: Revision %c", reg + 64); 113 114 /* enable refresh, set big-endian, memory parity, allow slave access */ 115 reg = bus_space_read_4(psc.iot, psc.ioh, PIC_CPUCTRL); 116 reg |= (PIC_CPUCTRL_REFRESH | PIC_CPUCTRL_BIGENDIAN | PIC_CPUCTRL_MPR | 117 PIC_CPUCTRL_SLAVE); 118 bus_space_write_4(psc.iot, psc.ioh, PIC_CPUCTRL, reg); 119 120 /* query the mode register to see what's going on */ 121 reg = bus_space_read_4(psc.iot, psc.ioh, PIC_MODE); 122 printf(": dblk (0x%x), iblk (0x%x)\n", reg & PIC_MODE_DBSIZ, 123 reg & PIC_MODE_IBSIZ); 124 125 /* display the machine type, board revision */ 126 printf("pic0: "); 127 128 switch (mach_subtype) { 129 case MACH_SGI_IP12_4D_3X: 130 printf("Personal Iris 4D/3x"); 131 break; 132 case MACH_SGI_IP12_VIP12: 133 printf("VME IP12"); 134 break; 135 case MACH_SGI_IP12_HP1: 136 printf("Indigo R3000"); 137 break; 138 case MACH_SGI_IP12_HPLC: 139 printf("Hollywood Light"); 140 break; 141 default: 142 printf("unknown machine"); 143 break; 144 } 145 printf(", board revision %x\n", mach_boardrev); 146 147 printf("pic0: "); 148 149 if (reg & PIC_MODE_NOCACHE) 150 printf("cache disabled"); 151 else 152 printf("cache enabled"); 153 154 if (reg & PIC_MODE_ISTREAM) 155 printf(", instr streaming"); 156 157 if (reg & PIC_MODE_STOREPARTIAL) 158 printf(", store partial"); 159 160 if (reg & PIC_MODE_BUSDRIVE) 161 printf(", bus drive"); 162 163 /* gio32 allow master, real time devices */ 164 reg = bus_space_read_4(psc.iot, psc.ioh, PIC_GIO32ARB_SLOT0); 165 reg &= ~(PIC_GIO32ARB_SLOT_SLAVE | PIC_GIO32ARB_SLOT_LONG); 166 bus_space_write_4(psc.iot, psc.ioh, PIC_GIO32ARB_SLOT0, reg); 167 168 reg = bus_space_read_4(psc.iot, psc.ioh, PIC_GIO32ARB_SLOT1); 169 reg &= ~(PIC_GIO32ARB_SLOT_SLAVE | PIC_GIO32ARB_SLOT_LONG); 170 bus_space_write_4(psc.iot, psc.ioh, PIC_GIO32ARB_SLOT1, reg); 171 172 /* default gio32 burst time */ 173 bus_space_write_4(psc.iot, psc.ioh, PIC_GIO32ARB_BURST, 174 PIC_GIO32ARB_DEFBURST); 175 176 /* default gio32 delay time */ 177 bus_space_write_4(psc.iot, psc.ioh, PIC_GIO32ARB_DELAY, 178 PIC_GIO32ARB_DEFDELAY); 179 180 printf("\n"); 181 182 /* 183 * A GIO bus exists on all IP12's. However, Personal Iris 184 * machines use VME for their expansion bus. 185 */ 186 iaa.iaa_name = "gio"; 187 (void) config_found(self, (void *) &iaa, pic_print); 188 189 pic_watchdog_enable(); 190 } 191 192 193 static int 194 pic_print(void *aux, const char *name) 195 { 196 struct pic_attach_args *iaa = aux; 197 198 if (name) 199 aprint_normal("%s at %s", iaa->iaa_name, name); 200 201 return (UNCONF); 202 } 203 204 static void 205 pic_bus_reset(void) 206 { 207 bus_space_write_4(psc.iot, psc.ioh, PIC_PARITY_ERROR, 0); 208 } 209 210 static void 211 pic_watchdog_enable(void) 212 { 213 uint32_t reg; 214 215 reg = bus_space_read_4(psc.iot, psc.ioh, PIC_CPUCTRL); 216 reg |= PIC_CPUCTRL_WDOG; 217 bus_space_write_4(psc.iot, psc.ioh, PIC_CPUCTRL, reg); 218 } 219 220 static void 221 pic_watchdog_disable(void) 222 { 223 uint32_t reg; 224 225 reg = bus_space_read_4(psc.iot, psc.ioh, PIC_CPUCTRL); 226 reg &= ~(PIC_CPUCTRL_WDOG); 227 bus_space_write_4(psc.iot, psc.ioh, PIC_CPUCTRL, reg); 228 } 229 230 static void 231 pic_watchdog_tickle(void) 232 { 233 234 pic_watchdog_disable(); 235 pic_watchdog_enable(); 236 } 237 238 /* intended to be called from gio/gio.c only */ 239 int 240 pic_gio32_arb_config(int slot, uint32_t flags) 241 { 242 uint32_t reg; 243 244 /* only Indigo machines have GIO expansion slots (XXX HPLC?) */ 245 if (mach_subtype != MACH_SGI_IP12_HP1 && 246 mach_subtype != MACH_SGI_IP12_HPLC) 247 return (EINVAL); 248 249 /* graphics slot is not valid on IP12 */ 250 if (slot != GIO_SLOT_EXP0 && slot != GIO_SLOT_EXP1) 251 return (EINVAL); 252 253 reg = bus_space_read_4(psc.iot, psc.ioh, (slot == GIO_SLOT_EXP0) ? 254 PIC_GIO32ARB_SLOT0 : PIC_GIO32ARB_SLOT1); 255 256 if (flags & GIO_ARB_RT) 257 reg &= ~PIC_GIO32ARB_SLOT_LONG; 258 259 if (flags & GIO_ARB_LB) 260 reg |= PIC_GIO32ARB_SLOT_LONG; 261 262 if (flags & GIO_ARB_MST) 263 reg &= ~PIC_GIO32ARB_SLOT_SLAVE; 264 265 if (flags & GIO_ARB_SLV) 266 reg |= PIC_GIO32ARB_SLOT_SLAVE; 267 268 bus_space_write_4(psc.iot, psc.ioh, (slot == GIO_SLOT_EXP0) ? 269 PIC_GIO32ARB_SLOT0 : PIC_GIO32ARB_SLOT1, reg); 270 271 return (0); 272 } 273
Indexes created Tue Sep 30 06:09:59 GMT 2025