picreg.h revision 1.2.2.2
1 1.2.2.2 skrll /* $NetBSD: picreg.h,v 1.2.2.2 2004/08/03 10:40:00 skrll Exp $ */ 2 1.2.2.2 skrll 3 1.2.2.2 skrll /* 4 1.2.2.2 skrll * Copyright (c) 2002 Steve Rumble 5 1.2.2.2 skrll * All rights reserved. 6 1.2.2.2 skrll * 7 1.2.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.2.2.2 skrll * modification, are permitted provided that the following conditions 9 1.2.2.2 skrll * are met: 10 1.2.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.2.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.2.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.2.2.2 skrll * 3. The name of the author may not be used to endorse or promote products 16 1.2.2.2 skrll * derived from this software without specific prior written permission. 17 1.2.2.2 skrll * 18 1.2.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 1.2.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 1.2.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 1.2.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 1.2.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 1.2.2.2 skrll * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 1.2.2.2 skrll * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 1.2.2.2 skrll * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 1.2.2.2 skrll * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 1.2.2.2 skrll * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 1.2.2.2 skrll */ 29 1.2.2.2 skrll 30 1.2.2.2 skrll #ifndef _ARCH_SGIMIPS_DEV_PICREG_H_ 31 1.2.2.2 skrll #define _ARCH_SGIMIPS_DEV_PICREG_H_ 32 1.2.2.2 skrll 33 1.2.2.2 skrll #define PIC_CPUCTRL 0x00 /* CPU control */ 34 1.2.2.2 skrll 35 1.2.2.2 skrll #define PIC_CPUCTRL_REFRESH 0x0001 /* refresh enable */ 36 1.2.2.2 skrll #define PIC_CPUCTRL_BIGENDIAN 0x0002 /* big endian mode */ 37 1.2.2.2 skrll #define PIC_CPUCTRL_DBREFILL 0x0004 /* data block refill */ 38 1.2.2.2 skrll #define PIC_CPUCTRL_IBREFILL 0x0008 /* instruction block refill */ 39 1.2.2.2 skrll #define PIC_CPUCTRL_GDMAINTR 0x0010 /* gfx intr on completion */ 40 1.2.2.2 skrll #define PIC_CPUCTRL_GDMASYNC 0x0020 /* gfx dma sync */ 41 1.2.2.2 skrll #define PIC_CPUCTRL_FREFRESH 0x0040 /* fast refresh on 33mhz+ gio */ 42 1.2.2.2 skrll #define PIC_CPUCTRL_NOVMEERR 0x0080 /* disables vme bus errors */ 43 1.2.2.2 skrll #define PIC_CPUCTRL_FREFRESHB 0x0080 /* fast refresh on revs. a+b */ 44 1.2.2.2 skrll #define PIC_CPUCTRL_GR2 0x0100 /* gio gr2 mode (?) */ 45 1.2.2.2 skrll #define PIC_CPUCTRL_SYSRESET 0x0200 /* vme sysreset line */ 46 1.2.2.2 skrll #define PIC_CPUCTRL_MPR 0x0400 /* memory read parity enable */ 47 1.2.2.2 skrll #define PIC_CPUCTRL_SLAVE 0x0800 /* slave accesses permitted */ 48 1.2.2.2 skrll #define PIC_CPUCTRL_VMEARB 0x1000 /* vme arbiter enable */ 49 1.2.2.2 skrll #define PIC_CPUCTRL_WPR 0x2000 /* write bad parity */ 50 1.2.2.2 skrll #define PIC_CPUCTRL_WDOG 0x4000 /* watchdog enable */ 51 1.2.2.2 skrll #define PIC_CPUCTRL_GFXRESET 0x8000 /* reset graphics */ 52 1.2.2.2 skrll 53 1.2.2.2 skrll #define PIC_MODE 0x04 /* system mode */ 54 1.2.2.2 skrll 55 1.2.2.2 skrll #define PIC_MODE_DBSIZ 0x0003 /* data block size */ 56 1.2.2.2 skrll #define PIC_MODE_IBSIZ 0x000c /* instruction block size */ 57 1.2.2.2 skrll #define PIC_MODE_ISTREAM 0x0010 /* instruction streaming */ 58 1.2.2.2 skrll #define PIC_MODE_NOCACHE 0x0020 /* cache disabled */ 59 1.2.2.2 skrll #define PIC_MODE_STOREPARTIAL 0x0040 /* store partial */ 60 1.2.2.2 skrll #define PIC_MODE_BUSDRIVE 0x0080 /* bus drive */ 61 1.2.2.2 skrll 62 1.2.2.2 skrll #define PIC_SYSID 0x08 /* system id */ 63 1.2.2.2 skrll 64 1.2.2.2 skrll #define PIC_SYSID_FPU 0x0001 /* fpu exists */ 65 1.2.2.2 skrll #define PIC_SYSID_GDMAERR 0x0004 /* graphics dma error */ 66 1.2.2.2 skrll #define PIC_SYSID_GDMADONE 0x0008 /* graphics dma complete */ 67 1.2.2.2 skrll #define PIC_SYSID_VMERMW 0x0010 /* vme read-mod-write */ 68 1.2.2.2 skrll #define PIC_SYSID_REVSHIFT 0x0006 /* Rev bits shifted */ 69 1.2.2.2 skrll #define PIC_SYSID_REVMASK 0x0007 /* PIC revision */ 70 1.2.2.2 skrll 71 1.2.2.2 skrll #define PIC_MEMCFG0 0x10000 /* memory config register 0 */ 72 1.2.2.2 skrll #define PIC_MEMCFG1 0x10004 /* memory config register 1 */ 73 1.2.2.2 skrll #define PIC_MEMCFG0_PHYSADDR (0x1fa00000 + PIC_MEMCFG0) 74 1.2.2.2 skrll #define PIC_MEMCFG1_PHYSADDR (0x1fa00000 + PIC_MEMCFG1) 75 1.2.2.2 skrll 76 1.2.2.2 skrll #define PIC_MEMCFG_4MB 0x0000 /* 4 megabytes (never occurs) */ 77 1.2.2.2 skrll #define PIC_MEMCFG_8MB 0x0001 /* 8 megabytes */ 78 1.2.2.2 skrll #define PIC_MEMCFG_16MB 0x0003 /* 16 megabytes */ 79 1.2.2.2 skrll #define PIC_MEMCFG_32MB 0x0007 /* 32 megabytes */ 80 1.2.2.2 skrll #define PIC_MEMCFG_64MB 0x000f /* 64 megabytes */ 81 1.2.2.2 skrll 82 1.2.2.2 skrll #define PIC_MEMCFG_BADSIZ 0x0000 /* bad memory size */ 83 1.2.2.2 skrll #define PIC_MEMCFG_ADDRMASK 0x003f /* memory address mask */ 84 1.2.2.2 skrll #define PIC_MEMCFG_BADADDR 0x003f /* no memory in bank */ 85 1.2.2.2 skrll #define PIC_MEMCFG_SIZMASK 0x0f00 /* bank size mask */ 86 1.2.2.2 skrll 87 1.2.2.2 skrll /* 88 1.2.2.2 skrll * The bank memory address is computed the same way mc's is. 89 1.2.2.2 skrll * Size is similar, only having one less bit (max. 64MB per bank). 90 1.2.2.2 skrll */ 91 1.2.2.2 skrll #define PIC_MEMCFG_ADDR(x) \ 92 1.2.2.2 skrll ((x & PIC_MEMCFG_ADDRMASK) << 22) 93 1.2.2.2 skrll #define PIC_MEMCFG_SIZ(x) \ 94 1.2.2.2 skrll (((x & PIC_MEMCFG_SIZMASK) + 0x100) << 14) 95 1.2.2.2 skrll 96 1.2.2.2 skrll #define PIC_WRONLY_REFRESH 0x10100 /* write only refresh timer */ 97 1.2.2.2 skrll 98 1.2.2.2 skrll #define PIC_PARITY_ERROR 0x10200 /* parity errors */ 99 1.2.2.2 skrll 100 1.2.2.2 skrll #define PIC_PARITY_ERROR_GDMA 0x0001 /* graphics dma */ 101 1.2.2.2 skrll #define PIC_PARITY_ERROR_DMA 0x0002 102 1.2.2.2 skrll #define PIC_PARITY_ERROR_CPU 0x0004 103 1.2.2.2 skrll #define PIC_PARITY_ERROR_VME 0x0008 104 1.2.2.2 skrll #define PIC_PARITY_ERROR_BYTE3 0x0010 /* error in fourth byte */ 105 1.2.2.2 skrll #define PIC_PARITY_ERROR_BYTE2 0x0020 /* error in third byte */ 106 1.2.2.2 skrll #define PIC_PARITY_ERROR_BYTE1 0x0040 /* error in second byte */ 107 1.2.2.2 skrll #define PIC_PARITY_ERROR_BYTE0 0x0080 /* error in first byte */ 108 1.2.2.2 skrll 109 1.2.2.2 skrll #define PIC_PARITY_ADDR_CPU 0x10204 /* cpu error address */ 110 1.2.2.2 skrll #define PIC_PARITY_ADDR_DMA 0x10208 /* dma error address */ 111 1.2.2.2 skrll #define PIC_PARITY_ERROR_CLEAR 0x10210 /* clear parity errors */ 112 1.2.2.2 skrll 113 1.2.2.2 skrll /* 114 1.2.2.2 skrll * GIO slot configuration registers described by the 'GIO BUS Specification' 115 1.2.2.2 skrll * apparently no IP20 counterpart on mc. 116 1.2.2.2 skrll */ 117 1.2.2.2 skrll #define PIC_GIO32ARB_SLOT0 0x20000 /* set slot 0 config */ 118 1.2.2.2 skrll #define PIC_GIO32ARB_SLOT1 0x20004 /* set slot 1 config */ 119 1.2.2.2 skrll 120 1.2.2.2 skrll #define PIC_GIO32ARB_SLOT_SLAVE 0x0001 /* slave only */ 121 1.2.2.2 skrll #define PIC_GIO32ARB_SLOT_LONG 0x0002 /* long burst */ 122 1.2.2.2 skrll 123 1.2.2.2 skrll #define PIC_GIO32ARB_BURST 0x20008 /* set gio burst */ 124 1.2.2.2 skrll 125 1.2.2.2 skrll #define PIC_GIO32ARB_DEFBURST 0x0001 /* default burst value */ 126 1.2.2.2 skrll 127 1.2.2.2 skrll #define PIC_GIO32ARB_DELAY 0x2000c /* set gio delay */ 128 1.2.2.2 skrll 129 1.2.2.2 skrll #define PIC_GIO32ARB_DEFDELAY 0x00f2 /* default delay value */ 130 1.2.2.2 skrll 131 1.2.2.2 skrll #endif /* _ARCH_SGIMIPS_DEV_PICREG_H_ */ 132
Indexes created Wed Oct 22 06:10:02 GMT 2025