gio.c revision 1.25
1 /* $NetBSD: gio.c,v 1.25 2006/12/29 00:42:01 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the 18 * NetBSD Project. See http://www.NetBSD.org/ for 19 * information about NetBSD. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: gio.c,v 1.25 2006/12/29 00:42:01 rumble Exp $"); 37 38 #include "opt_ddb.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 44 #define _SGIMIPS_BUS_DMA_PRIVATE 45 #include <machine/bus.h> 46 #include <machine/machtype.h> 47 48 #include <sgimips/gio/gioreg.h> 49 #include <sgimips/gio/giovar.h> 50 #include <sgimips/gio/giodevs_data.h> 51 52 #include "locators.h" 53 #include "newport.h" 54 #include "grtwo.h" 55 #include "light.h" 56 #include "imc.h" 57 #include "pic.h" 58 59 #if (NNEWPORT > 0) 60 #include <sgimips/gio/newportvar.h> 61 #endif 62 63 #if (NGRTWO > 0) 64 #include <sgimips/gio/grtwovar.h> 65 #endif 66 67 #if (NLIGHT > 0) 68 #include <sgimips/gio/lightvar.h> 69 #endif 70 71 #if (NIMC > 0) 72 extern int imc_gio64_arb_config(int, uint32_t); 73 #endif 74 75 #if (NPIC > 0) 76 extern int pic_gio32_arb_config(int, uint32_t); 77 #endif 78 79 80 struct gio_softc { 81 struct device sc_dev; 82 }; 83 84 static int gio_match(struct device *, struct cfdata *, void *); 85 static void gio_attach(struct device *, struct device *, void *); 86 static int gio_print(void *, const char *); 87 static int gio_search(struct device *, struct cfdata *, 88 const int *, void *); 89 static int gio_submatch(struct device *, struct cfdata *, 90 const int *, void *); 91 92 CFATTACH_DECL(gio, sizeof(struct gio_softc), 93 gio_match, gio_attach, NULL, NULL); 94 95 struct gio_probe { 96 uint32_t slot; 97 uint32_t base; 98 uint32_t mach_type; 99 uint32_t mach_subtype; 100 }; 101 102 /* 103 * Expansion Slot Base Addresses 104 * 105 * IP12, IP20 and IP24 have two GIO connectors: GIO_SLOT_EXP0 and 106 * GIO_SLOT_EXP1. 107 * 108 * On IP24 these slots exist on the graphics board or the IOPLUS 109 * "mezzanine" on Indy and Challenge S, respectively. The IOPLUS or 110 * graphics board connects to the mainboard via a single GIO64 connector. 111 * 112 * IP22 has either three or four physical connectors, but only two 113 * electrically distinct slots: GIO_SLOT_GFX and GIO_SLOT_EXP0. 114 * 115 * It should also be noted that DMA is (mostly) not supported in Challenge 116 * S's GIO_SLOT_EXP1. See gio(4) for the story. 117 */ 118 static const struct gio_probe slot_bases[] = { 119 { GIO_SLOT_GFX, 0x1f000000, MACH_SGI_IP22, MACH_SGI_IP22_FULLHOUSE }, 120 121 { GIO_SLOT_EXP0, 0x1f400000, MACH_SGI_IP12, -1 }, 122 { GIO_SLOT_EXP0, 0x1f400000, MACH_SGI_IP20, -1 }, 123 { GIO_SLOT_EXP0, 0x1f400000, MACH_SGI_IP22, -1 }, 124 125 { GIO_SLOT_EXP1, 0x1f600000, MACH_SGI_IP12, -1 }, 126 { GIO_SLOT_EXP1, 0x1f600000, MACH_SGI_IP20, -1 }, 127 { GIO_SLOT_EXP1, 0x1f600000, MACH_SGI_IP22, MACH_SGI_IP22_GUINNESS }, 128 129 { 0, 0, 0, 0 } 130 }; 131 132 /* 133 * Graphic Board Base Addresses 134 * 135 * Graphics boards are not treated like expansion slot cards. Their base 136 * addresses do not necessarily correspond to GIO slot addresses and they 137 * do not contain product identification words. 138 */ 139 static const struct gio_probe gfx_bases[] = { 140 /* grtwo, and newport on IP22 */ 141 { -1, 0x1f000000, MACH_SGI_IP12, -1 }, 142 { -1, 0x1f000000, MACH_SGI_IP20, -1 }, 143 { -1, 0x1f000000, MACH_SGI_IP22, -1 }, 144 145 /* light */ 146 { -1, 0x1f3f0000, MACH_SGI_IP12, -1 }, 147 { -1, 0x1f3f0000, MACH_SGI_IP20, -1 }, 148 149 /* light (dual headed) */ 150 { -1, 0x1f3f8000, MACH_SGI_IP12, -1 }, 151 { -1, 0x1f3f8000, MACH_SGI_IP20, -1 }, 152 153 /* grtwo, and newport on IP22 */ 154 { -1, 0x1f400000, MACH_SGI_IP12, -1 }, 155 { -1, 0x1f400000, MACH_SGI_IP20, -1 }, 156 { -1, 0x1f400000, MACH_SGI_IP22, -1 }, 157 158 /* grtwo */ 159 { -1, 0x1f600000, MACH_SGI_IP12, -1 }, 160 { -1, 0x1f600000, MACH_SGI_IP20, -1 }, 161 { -1, 0x1f600000, MACH_SGI_IP22, -1 }, 162 163 /* newport */ 164 { -1, 0x1f800000, MACH_SGI_IP22, MACH_SGI_IP22_FULLHOUSE }, 165 166 /* newport */ 167 { -1, 0x1fc00000, MACH_SGI_IP22, MACH_SGI_IP22_FULLHOUSE }, 168 169 { 0, 0, 0, 0 } 170 }; 171 172 /* maximum number of graphics boards possible (arbitrarily large estimate) */ 173 #define MAXGFX 8 174 175 static int 176 gio_match(struct device *parent, struct cfdata *match, void *aux) 177 { 178 179 return 1; 180 } 181 182 static void 183 gio_attach(struct device *parent, struct device *self, void *aux) 184 { 185 struct gio_attach_args ga; 186 uint32_t gfx[MAXGFX]; 187 int i, j, ngfx; 188 189 printf("\n"); 190 191 ngfx = 0; 192 memset(gfx, 0, sizeof(gfx)); 193 194 /* 195 * Attach graphics devices first. They do not contain a Product 196 * Identification Word and have no slot number. 197 * 198 * Record addresses to which graphics devices attach so that 199 * we do not confuse them with expansion slots, should the 200 * addresses coincide. 201 */ 202 for (i = 0; gfx_bases[i].base != 0; i++) { 203 /* skip slots that don't apply to us */ 204 if (gfx_bases[i].mach_type != mach_type) 205 continue; 206 207 if (gfx_bases[i].mach_subtype != -1 && 208 gfx_bases[i].mach_subtype != mach_subtype) 209 continue; 210 211 ga.ga_slot = -1; 212 ga.ga_addr = gfx_bases[i].base; 213 ga.ga_iot = SGIMIPS_BUS_SPACE_NORMAL; 214 ga.ga_ioh = MIPS_PHYS_TO_KSEG1(ga.ga_addr); 215 ga.ga_dmat = &sgimips_default_bus_dma_tag; 216 ga.ga_product = -1; 217 218 if (badaddr((void *)ga.ga_ioh, sizeof(uint32_t))) 219 continue; 220 221 if (config_found_sm_loc(self, "gio", NULL, &ga, gio_print, 222 gio_submatch)) { 223 if (ngfx == MAXGFX) 224 panic("gio_attach: MAXGFX"); 225 gfx[ngfx++] = gfx_bases[i].base; 226 } 227 } 228 229 /* 230 * Now attach any GIO expansion cards. 231 * 232 * Be sure to skip any addresses to which a graphics device has 233 * already been attached. 234 */ 235 for (i = 0; slot_bases[i].base != 0; i++) { 236 boolean_t skip = FALSE; 237 238 /* skip slots that don't apply to us */ 239 if (slot_bases[i].mach_type != mach_type) 240 continue; 241 242 if (slot_bases[i].mach_subtype != -1 && 243 slot_bases[i].mach_subtype != mach_subtype) 244 continue; 245 246 for (j = 0; j < ngfx; j++) { 247 if (slot_bases[i].base == gfx[j]) { 248 skip = TRUE; 249 break; 250 } 251 } 252 if (skip) 253 continue; 254 255 ga.ga_slot = slot_bases[i].slot; 256 ga.ga_addr = slot_bases[i].base; 257 ga.ga_iot = SGIMIPS_BUS_SPACE_NORMAL; 258 ga.ga_ioh = MIPS_PHYS_TO_KSEG1(ga.ga_addr); 259 ga.ga_dmat = &sgimips_default_bus_dma_tag; 260 261 if (badaddr((void *)ga.ga_ioh, sizeof(uint32_t))) 262 continue; 263 264 ga.ga_product = bus_space_read_4(ga.ga_iot, ga.ga_ioh, 0); 265 266 config_found_sm_loc(self, "gio", NULL, &ga, gio_print, 267 gio_submatch); 268 } 269 270 config_search_ia(gio_search, self, "gio", &ga); 271 } 272 273 static int 274 gio_print(void *aux, const char *pnp) 275 { 276 struct gio_attach_args *ga = aux; 277 int i = 0; 278 279 /* gfx probe */ 280 if (ga->ga_product == -1) 281 return (QUIET); 282 283 if (pnp != NULL) { 284 int product, revision; 285 286 product = GIO_PRODUCT_PRODUCTID(ga->ga_product); 287 288 if (GIO_PRODUCT_32BIT_ID(ga->ga_product)) 289 revision = GIO_PRODUCT_REVISION(ga->ga_product); 290 else 291 revision = 0; 292 293 while (gio_knowndevs[i].productid != 0) { 294 if (gio_knowndevs[i].productid == product) { 295 aprint_normal("%s", gio_knowndevs[i].product); 296 break; 297 } 298 i++; 299 } 300 301 if (gio_knowndevs[i].productid == 0) 302 aprint_normal("unknown GIO card"); 303 304 aprint_normal(" (product 0x%02x revision 0x%02x) at %s", 305 product, revision, pnp); 306 } 307 308 if (ga->ga_slot != GIOCF_SLOT_DEFAULT) 309 aprint_normal(" slot %d", ga->ga_slot); 310 if (ga->ga_addr != (uint32_t) GIOCF_ADDR_DEFAULT) 311 aprint_normal(" addr 0x%x", ga->ga_addr); 312 313 return UNCONF; 314 } 315 316 static int 317 gio_search(struct device *parent, struct cfdata *cf, 318 const int *ldesc, void *aux) 319 { 320 struct gio_attach_args *ga = aux; 321 322 do { 323 /* Handled by direct configuration, so skip here */ 324 if (cf->cf_loc[GIOCF_ADDR] == GIOCF_ADDR_DEFAULT) 325 return 0; 326 327 ga->ga_slot = cf->cf_loc[GIOCF_SLOT]; 328 ga->ga_addr = cf->cf_loc[GIOCF_ADDR]; 329 ga->ga_iot = 0; 330 ga->ga_ioh = MIPS_PHYS_TO_KSEG1(ga->ga_addr); 331 332 if (config_match(parent, cf, ga) > 0) 333 config_attach(parent, cf, ga, gio_print); 334 } while (cf->cf_fstate == FSTATE_STAR); 335 336 return 0; 337 } 338 339 static int 340 gio_submatch(struct device *parent, struct cfdata *cf, 341 const int *ldesc, void *aux) 342 { 343 struct gio_attach_args *ga = aux; 344 345 if (cf->cf_loc[GIOCF_SLOT] != GIOCF_SLOT_DEFAULT && 346 cf->cf_loc[GIOCF_SLOT] != ga->ga_slot) 347 return 0; 348 349 if (cf->cf_loc[GIOCF_ADDR] != GIOCF_ADDR_DEFAULT && 350 cf->cf_loc[GIOCF_ADDR] != ga->ga_addr) 351 return 0; 352 353 return config_match(parent, cf, aux); 354 } 355 356 int 357 gio_cnattach() 358 { 359 struct gio_attach_args ga; 360 int i; 361 362 for (i = 0; gfx_bases[i].base != 0; i++) { 363 /* skip bases that don't apply to us */ 364 if (gfx_bases[i].mach_type != mach_type) 365 continue; 366 367 if (gfx_bases[i].mach_subtype != -1 && 368 gfx_bases[i].mach_subtype != mach_subtype) 369 continue; 370 371 ga.ga_slot = -1; 372 ga.ga_addr = gfx_bases[i].base; 373 ga.ga_iot = SGIMIPS_BUS_SPACE_NORMAL; 374 ga.ga_ioh = MIPS_PHYS_TO_KSEG1(ga.ga_addr); 375 ga.ga_dmat = &sgimips_default_bus_dma_tag; 376 ga.ga_product = -1; 377 378 if (badaddr((void *)ga.ga_ioh,sizeof(uint32_t))) 379 continue; 380 381 #if (NGRTWO > 0) 382 if (grtwo_cnattach(&ga) == 0) 383 return 0; 384 #endif 385 386 #if (NLIGHT > 0) 387 if (light_cnattach(&ga) == 0) 388 return 0; 389 #endif 390 391 #if (NNEWPORT > 0) 392 if (newport_cnattach(&ga) == 0) 393 return 0; 394 #endif 395 396 } 397 398 return ENXIO; 399 } 400 401 /* 402 * Devices living in the expansion slots must enable or disable some 403 * GIO arbiter settings. This is accomplished via imc(4) or pic(4) 404 * registers, depending on the machine in question. 405 */ 406 int 407 gio_arb_config(int slot, uint32_t flags) 408 { 409 410 if (flags == 0) 411 return (EINVAL); 412 413 if (flags & ~(GIO_ARB_RT | GIO_ARB_LB | GIO_ARB_MST | GIO_ARB_SLV | 414 GIO_ARB_PIPE | GIO_ARB_NOPIPE)) 415 return (EINVAL); 416 417 if (((flags & GIO_ARB_RT) && (flags & GIO_ARB_LB)) || 418 ((flags & GIO_ARB_MST) && (flags & GIO_ARB_SLV)) || 419 ((flags & GIO_ARB_PIPE) && (flags & GIO_ARB_NOPIPE))) 420 return (EINVAL); 421 422 #if (NPIC > 0) 423 if (mach_type == MACH_SGI_IP12) 424 return (pic_gio32_arb_config(slot, flags)); 425 #endif 426 427 #if (NIMC > 0) 428 if (mach_type == MACH_SGI_IP20 || mach_type == MACH_SGI_IP22) 429 return (imc_gio64_arb_config(slot, flags)); 430 #endif 431 432 return (EINVAL); 433 } 434 435 /* 436 * Establish an interrupt handler for the specified slot. 437 * 438 * Indy and Challenge S have an interrupt per GIO slot. Indigo and Indigo2 439 * share a single interrupt, however. 440 */ 441 void * 442 gio_intr_establish(int slot, int level, int (*func)(void *), void *arg) 443 { 444 int intr; 445 446 switch (mach_type) { 447 case MACH_SGI_IP12: 448 case MACH_SGI_IP20: 449 if (slot == GIO_SLOT_GFX) 450 panic("gio_intr_establish: slot %d", slot); 451 intr = 6; 452 break; 453 454 case MACH_SGI_IP22: 455 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) { 456 if (slot == GIO_SLOT_EXP1) 457 panic("gio_intr_establish: slot %d", slot); 458 intr = 6; 459 } else { 460 if (slot == GIO_SLOT_GFX) 461 panic("gio_intr_establish: slot %d", slot); 462 intr = (slot == GIO_SLOT_EXP0) ? 22 : 23; 463 } 464 break; 465 466 default: 467 panic("gio_intr_establish: mach_type"); 468 } 469 470 return (cpu_intr_establish(intr, level, func, arg)); 471 } 472 473 const char * 474 gio_product_string(int prid) 475 { 476 int i; 477 478 for (i = 0; gio_knowndevs[i].product != NULL; i++) 479 if (gio_knowndevs[i].productid == prid) 480 return (gio_knowndevs[i].product); 481 482 return (NULL); 483 } 484
Indexes created Fri Sep 26 20:09:58 GMT 2025