gio.c revision 1.36.10.3
1 /* $NetBSD: gio.c,v 1.36.10.3 2021/03/22 02:00:58 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the 18 * NetBSD Project. See http://www.NetBSD.org/ for 19 * information about NetBSD. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: gio.c,v 1.36.10.3 2021/03/22 02:00:58 thorpej Exp $"); 37 38 #include "opt_ddb.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 44 #include <sys/bus.h> 45 #include <machine/machtype.h> 46 #include <machine/sysconf.h> 47 48 #include <sgimips/gio/gioreg.h> 49 #include <sgimips/gio/giovar.h> 50 #include <sgimips/gio/giodevs_data.h> 51 52 #include "locators.h" 53 #include "newport.h" 54 #include "grtwo.h" 55 #include "light.h" 56 #include "imc.h" 57 #include "pic.h" 58 59 #if (NNEWPORT > 0) 60 #include <sgimips/gio/newportvar.h> 61 #endif 62 63 #if (NGRTWO > 0) 64 #include <sgimips/gio/grtwovar.h> 65 #endif 66 67 #if (NLIGHT > 0) 68 #include <sgimips/gio/lightvar.h> 69 #endif 70 71 #if (NIMC > 0) 72 extern int imc_gio64_arb_config(int, uint32_t); 73 #endif 74 75 #if (NPIC > 0) 76 extern int pic_gio32_arb_config(int, uint32_t); 77 #endif 78 79 80 static int gio_match(device_t, cfdata_t, void *); 81 static void gio_attach(device_t, device_t, void *); 82 static int gio_print(void *, const char *); 83 static int gio_search(device_t, cfdata_t, const int *, void *); 84 static int gio_submatch(device_t, cfdata_t, const int *, void *); 85 86 CFATTACH_DECL_NEW(gio, 0, 87 gio_match, gio_attach, NULL, NULL); 88 89 struct gio_probe { 90 uint32_t slot; 91 uint32_t base; 92 uint32_t mach_type; 93 uint32_t mach_subtype; 94 }; 95 96 /* 97 * Expansion Slot Base Addresses 98 * 99 * IP12, IP20 and IP24 have two GIO connectors: GIO_SLOT_EXP0 and 100 * GIO_SLOT_EXP1. 101 * 102 * On IP24 these slots exist on the graphics board or the IOPLUS 103 * "mezzanine" on Indy and Challenge S, respectively. The IOPLUS or 104 * graphics board connects to the mainboard via a single GIO64 connector. 105 * 106 * IP22 has either three or four physical connectors, but only two 107 * electrically distinct slots: GIO_SLOT_GFX and GIO_SLOT_EXP0. 108 * 109 * It should also be noted that DMA is (mostly) not supported in Challenge 110 * S's GIO_SLOT_EXP1. See gio(4) for the story. 111 */ 112 static const struct gio_probe slot_bases[] = { 113 { GIO_SLOT_GFX, 0x1f000000, MACH_SGI_IP22, MACH_SGI_IP22_FULLHOUSE }, 114 115 { GIO_SLOT_EXP0, 0x1f400000, MACH_SGI_IP12, -1 }, 116 { GIO_SLOT_EXP0, 0x1f400000, MACH_SGI_IP20, -1 }, 117 { GIO_SLOT_EXP0, 0x1f400000, MACH_SGI_IP22, -1 }, 118 119 { GIO_SLOT_EXP1, 0x1f600000, MACH_SGI_IP12, -1 }, 120 { GIO_SLOT_EXP1, 0x1f600000, MACH_SGI_IP20, -1 }, 121 { GIO_SLOT_EXP1, 0x1f600000, MACH_SGI_IP22, MACH_SGI_IP22_GUINNESS }, 122 123 { 0, 0, 0, 0 } 124 }; 125 126 /* 127 * Graphic Board Base Addresses 128 * 129 * Graphics boards are not treated like expansion slot cards. Their base 130 * addresses do not necessarily correspond to GIO slot addresses and they 131 * do not contain product identification words. 132 */ 133 static const struct gio_probe gfx_bases[] = { 134 /* grtwo, and newport on IP22 */ 135 { -1, 0x1f000000, MACH_SGI_IP12, -1 }, 136 { -1, 0x1f000000, MACH_SGI_IP20, -1 }, 137 { -1, 0x1f000000, MACH_SGI_IP22, -1 }, 138 139 /* light */ 140 { -1, 0x1f3f0000, MACH_SGI_IP12, -1 }, 141 { -1, 0x1f3f0000, MACH_SGI_IP20, -1 }, 142 143 /* light (dual headed) */ 144 { -1, 0x1f3f8000, MACH_SGI_IP12, -1 }, 145 { -1, 0x1f3f8000, MACH_SGI_IP20, -1 }, 146 147 /* grtwo, and newport on IP22 */ 148 { -1, 0x1f400000, MACH_SGI_IP12, -1 }, 149 { -1, 0x1f400000, MACH_SGI_IP20, -1 }, 150 { -1, 0x1f400000, MACH_SGI_IP22, -1 }, 151 152 /* grtwo */ 153 { -1, 0x1f600000, MACH_SGI_IP12, -1 }, 154 { -1, 0x1f600000, MACH_SGI_IP20, -1 }, 155 { -1, 0x1f600000, MACH_SGI_IP22, -1 }, 156 157 /* newport */ 158 { -1, 0x1f800000, MACH_SGI_IP22, MACH_SGI_IP22_FULLHOUSE }, 159 160 /* newport */ 161 { -1, 0x1fc00000, MACH_SGI_IP22, MACH_SGI_IP22_FULLHOUSE }, 162 163 { 0, 0, 0, 0 } 164 }; 165 166 /* maximum number of graphics boards possible (arbitrarily large estimate) */ 167 #define MAXGFX 8 168 169 static int 170 gio_match(device_t parent, cfdata_t match, void *aux) 171 { 172 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20 || 173 mach_type == MACH_SGI_IP22) 174 return 1; 175 176 return 0; 177 } 178 179 static void 180 gio_attach(device_t parent, device_t self, void *aux) 181 { 182 struct gio_attach_args ga; 183 uint32_t gfx[MAXGFX]; 184 int i, j, ngfx; 185 186 printf("\n"); 187 188 ngfx = 0; 189 memset(gfx, 0, sizeof(gfx)); 190 191 /* 192 * Attach graphics devices first. They do not contain a Product 193 * Identification Word and have no slot number. 194 * 195 * Record addresses to which graphics devices attach so that 196 * we do not confuse them with expansion slots, should the 197 * addresses coincide. 198 */ 199 for (i = 0; gfx_bases[i].base != 0; i++) { 200 /* skip slots that don't apply to us */ 201 if (gfx_bases[i].mach_type != mach_type) 202 continue; 203 204 if (gfx_bases[i].mach_subtype != -1 && 205 gfx_bases[i].mach_subtype != mach_subtype) 206 continue; 207 208 ga.ga_slot = -1; 209 ga.ga_addr = gfx_bases[i].base; 210 /* XXX */ 211 if (platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga.ga_addr), 212 sizeof(uint32_t))) 213 continue; 214 ga.ga_iot = normal_memt; 215 if (bus_space_map(normal_memt, ga.ga_addr, 0, 216 BUS_SPACE_MAP_LINEAR, &ga.ga_ioh) != 0) 217 continue; 218 ga.ga_dmat = &sgimips_default_bus_dma_tag; 219 ga.ga_product = -1; 220 221 222 if (config_found(self, &ga, gio_print, 223 CFARG_SUBMATCH, gio_submatch, 224 CFARG_IATTR, "gio", 225 CFARG_EOL) != NULL) { 226 if (ngfx == MAXGFX) 227 panic("gio_attach: MAXGFX"); 228 gfx[ngfx++] = gfx_bases[i].base; 229 } 230 } 231 232 /* 233 * Now attach any GIO expansion cards. 234 * 235 * Be sure to skip any addresses to which a graphics device has 236 * already been attached. 237 */ 238 for (i = 0; slot_bases[i].base != 0; i++) { 239 bool skip = false; 240 241 /* skip slots that don't apply to us */ 242 if (slot_bases[i].mach_type != mach_type) 243 continue; 244 245 if (slot_bases[i].mach_subtype != -1 && 246 slot_bases[i].mach_subtype != mach_subtype) 247 continue; 248 249 for (j = 0; j < ngfx; j++) { 250 if (slot_bases[i].base == gfx[j]) { 251 skip = true; 252 break; 253 } 254 } 255 if (skip) 256 continue; 257 258 ga.ga_slot = slot_bases[i].slot; 259 ga.ga_addr = slot_bases[i].base; 260 /* XXX */ 261 if (platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga.ga_addr), 262 sizeof(uint32_t))) 263 continue; 264 ga.ga_iot = normal_memt; 265 if (bus_space_map(normal_memt, ga.ga_addr, 0, 266 BUS_SPACE_MAP_LINEAR, &ga.ga_ioh) != 0) 267 continue; 268 ga.ga_dmat = &sgimips_default_bus_dma_tag; 269 270 ga.ga_product = bus_space_read_4(ga.ga_iot, ga.ga_ioh, 0); 271 272 config_found(self, &ga, gio_print, 273 CFARG_SUBMATCH, gio_submatch, 274 CFARG_IATTR, "gio", 275 CFARG_EOL); 276 } 277 278 config_search(self, &ga, 279 CFARG_SUBMATCH, gio_search, 280 CFARG_EOL); 281 } 282 283 static int 284 gio_print(void *aux, const char *pnp) 285 { 286 struct gio_attach_args *ga = aux; 287 int i = 0; 288 289 /* gfx probe */ 290 if (ga->ga_product == -1) 291 return (QUIET); 292 293 if (pnp != NULL) { 294 int product, revision; 295 296 product = GIO_PRODUCT_PRODUCTID(ga->ga_product); 297 298 if (GIO_PRODUCT_32BIT_ID(ga->ga_product)) 299 revision = GIO_PRODUCT_REVISION(ga->ga_product); 300 else 301 revision = 0; 302 303 while (gio_knowndevs[i].productid != 0) { 304 if (gio_knowndevs[i].productid == product) { 305 aprint_normal("%s", gio_knowndevs[i].product); 306 break; 307 } 308 i++; 309 } 310 311 if (gio_knowndevs[i].productid == 0) 312 aprint_normal("unknown GIO card"); 313 314 aprint_normal(" (product 0x%02x revision 0x%02x) at %s", 315 product, revision, pnp); 316 } 317 318 if (ga->ga_slot != GIOCF_SLOT_DEFAULT) 319 aprint_normal(" slot %d", ga->ga_slot); 320 if (ga->ga_addr != (uint32_t) GIOCF_ADDR_DEFAULT) 321 aprint_normal(" addr 0x%x", ga->ga_addr); 322 323 return UNCONF; 324 } 325 326 static int 327 gio_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 328 { 329 struct gio_attach_args *ga = aux; 330 331 do { 332 /* Handled by direct configuration, so skip here */ 333 if (cf->cf_loc[GIOCF_ADDR] == GIOCF_ADDR_DEFAULT) 334 return 0; 335 336 ga->ga_slot = cf->cf_loc[GIOCF_SLOT]; 337 ga->ga_addr = cf->cf_loc[GIOCF_ADDR]; 338 ga->ga_iot = normal_memt; 339 ga->ga_ioh = MIPS_PHYS_TO_KSEG1(ga->ga_addr); 340 341 if (config_match(parent, cf, ga) > 0) 342 config_attach(parent, cf, ga, gio_print); 343 } while (cf->cf_fstate == FSTATE_STAR); 344 345 return 0; 346 } 347 348 static int 349 gio_submatch(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 350 { 351 struct gio_attach_args *ga = aux; 352 353 if (cf->cf_loc[GIOCF_SLOT] != GIOCF_SLOT_DEFAULT && 354 cf->cf_loc[GIOCF_SLOT] != ga->ga_slot) 355 return 0; 356 357 if (cf->cf_loc[GIOCF_ADDR] != GIOCF_ADDR_DEFAULT && 358 cf->cf_loc[GIOCF_ADDR] != ga->ga_addr) 359 return 0; 360 361 return config_match(parent, cf, aux); 362 } 363 364 int 365 gio_cnattach(void) 366 { 367 struct gio_attach_args ga; 368 int i; 369 370 for (i = 0; gfx_bases[i].base != 0; i++) { 371 /* skip bases that don't apply to us */ 372 if (gfx_bases[i].mach_type != mach_type) 373 continue; 374 375 if (gfx_bases[i].mach_subtype != -1 && 376 gfx_bases[i].mach_subtype != mach_subtype) 377 continue; 378 379 ga.ga_slot = -1; 380 ga.ga_addr = gfx_bases[i].base; 381 /* XXX */ 382 if (platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga.ga_addr), 383 sizeof(uint32_t))) 384 continue; 385 ga.ga_iot = normal_memt; 386 if (bus_space_map(normal_memt, ga.ga_addr, 0, 387 BUS_SPACE_MAP_LINEAR, &ga.ga_ioh) != 0) 388 continue; 389 ga.ga_dmat = &sgimips_default_bus_dma_tag; 390 ga.ga_product = -1; 391 392 #if (NGRTWO > 0) 393 if (grtwo_cnattach(&ga) == 0) 394 return 0; 395 #endif 396 397 #if (NLIGHT > 0) 398 if (light_cnattach(&ga) == 0) 399 return 0; 400 #endif 401 402 #if (NNEWPORT > 0) 403 if (newport_cnattach(&ga) == 0) 404 return 0; 405 #endif 406 407 } 408 409 return ENXIO; 410 } 411 412 /* 413 * Devices living in the expansion slots must enable or disable some 414 * GIO arbiter settings. This is accomplished via imc(4) or pic(4) 415 * registers, depending on the machine in question. 416 */ 417 int 418 gio_arb_config(int slot, uint32_t flags) 419 { 420 421 if (flags == 0) 422 return (EINVAL); 423 424 if (flags & ~(GIO_ARB_RT | GIO_ARB_LB | GIO_ARB_MST | GIO_ARB_SLV | 425 GIO_ARB_PIPE | GIO_ARB_NOPIPE | GIO_ARB_32BIT | GIO_ARB_64BIT | 426 GIO_ARB_HPC2_32BIT | GIO_ARB_HPC2_64BIT)) 427 return (EINVAL); 428 429 if (((flags & GIO_ARB_RT) && (flags & GIO_ARB_LB)) || 430 ((flags & GIO_ARB_MST) && (flags & GIO_ARB_SLV)) || 431 ((flags & GIO_ARB_PIPE) && (flags & GIO_ARB_NOPIPE)) || 432 ((flags & GIO_ARB_32BIT) && (flags & GIO_ARB_64BIT)) || 433 ((flags & GIO_ARB_HPC2_32BIT) && (flags & GIO_ARB_HPC2_64BIT))) 434 return (EINVAL); 435 436 #if (NPIC > 0) 437 if (mach_type == MACH_SGI_IP12) 438 return (pic_gio32_arb_config(slot, flags)); 439 #endif 440 441 #if (NIMC > 0) 442 if (mach_type == MACH_SGI_IP20 || mach_type == MACH_SGI_IP22) 443 return (imc_gio64_arb_config(slot, flags)); 444 #endif 445 446 return (EINVAL); 447 } 448 449 /* 450 * Establish an interrupt handler for the specified slot. 451 * 452 * Indy and Challenge S have an interrupt per GIO slot. Indigo and Indigo2 453 * share a single interrupt, however. 454 */ 455 void * 456 gio_intr_establish(int slot, int level, int (*func)(void *), void *arg) 457 { 458 int intr; 459 460 switch (mach_type) { 461 case MACH_SGI_IP12: 462 case MACH_SGI_IP20: 463 if (slot == GIO_SLOT_GFX) 464 panic("gio_intr_establish: slot %d", slot); 465 intr = 6; 466 break; 467 468 case MACH_SGI_IP22: 469 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) { 470 if (slot == GIO_SLOT_EXP1) 471 panic("gio_intr_establish: slot %d", slot); 472 intr = 6; 473 } else { 474 if (slot == GIO_SLOT_GFX) 475 panic("gio_intr_establish: slot %d", slot); 476 intr = (slot == GIO_SLOT_EXP0) ? 22 : 23; 477 } 478 break; 479 480 default: 481 panic("gio_intr_establish: mach_type"); 482 } 483 484 return (cpu_intr_establish(intr, level, func, arg)); 485 } 486 487 const char * 488 gio_product_string(int prid) 489 { 490 int i; 491 492 for (i = 0; gio_knowndevs[i].product != NULL; i++) 493 if (gio_knowndevs[i].productid == prid) 494 return (gio_knowndevs[i].product); 495 496 return (NULL); 497 } 498
Indexes created Mon Oct 13 08:09:50 GMT 2025