pci_gio.c revision 1.14
1 /* $NetBSD: pci_gio.c,v 1.14 2015/02/18 16:47:58 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Stephen M. Rumble 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: pci_gio.c,v 1.14 2015/02/18 16:47:58 macallan Exp $"); 29 30 /* 31 * Glue for PCI devices that are connected to the GIO bus by various little 32 * GIO<->PCI ASICs. 33 * 34 * We presently support the following boards: 35 * o Phobos G100/G130/G160 (if_tlp, lxtphy) 36 * o Set Engineering GFE (if_tl, nsphy) 37 */ 38 39 #include "opt_pci.h" 40 #include "pci.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 #include <sys/extent.h> 47 48 #include <sys/bus.h> 49 #include <machine/machtype.h> 50 51 #include <sgimips/gio/giovar.h> 52 #include <sgimips/gio/gioreg.h> 53 #include <sgimips/gio/giodevs.h> 54 55 #include <sgimips/dev/imcvar.h> 56 57 #include <mips/cache.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 #include <dev/pci/pciconf.h> 63 64 int giopci_debug = 0; 65 #define DPRINTF(_x) if (giopci_debug) printf _x 66 67 struct giopci_softc { 68 struct sgimips_pci_chipset sc_pc; 69 int sc_slot; 70 int sc_gprid; 71 uint32_t sc_pci_len; 72 bus_space_tag_t sc_iot; 73 bus_space_handle_t sc_ioh; 74 }; 75 76 static int giopci_match(device_t, cfdata_t, void *); 77 static void giopci_attach(device_t, device_t, void *); 78 static int giopci_bus_maxdevs(pci_chipset_tag_t, int); 79 static pcireg_t giopci_conf_read(pci_chipset_tag_t, pcitag_t, int); 80 static void giopci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 81 static int giopci_conf_hook(pci_chipset_tag_t, int, int, int, pcireg_t); 82 static int giopci_intr_map(const struct pci_attach_args *, 83 pci_intr_handle_t *); 84 static const char * 85 giopci_intr_string(pci_chipset_tag_t, pci_intr_handle_t, 86 char *, size_t); 87 static void *giopci_intr_establish(int, int, int (*)(void *), void *); 88 static void giopci_intr_disestablish(void *); 89 90 #define PHOBOS_PCI_OFFSET 0x00100000 91 #define PHOBOS_PCI_LENGTH 128 /* ~arbitrary */ 92 #define PHOBOS_TULIP_START 0x00101000 93 #define PHOBOS_TULIP_END 0x001fffff 94 95 #define SETENG_MAGIC_OFFSET 0x00020000 96 #define SETENG_MAGIC_VALUE 0x00001000 97 #define SETENG_PCI_OFFSET 0x00080000 98 #define SETENG_PCI_LENGTH 128 /* ~arbitrary */ 99 #define SETENG_TLAN_START 0x00100000 100 #define SETENG_TLAN_END 0x001fffff 101 102 CFATTACH_DECL_NEW(giopci, sizeof(struct giopci_softc), 103 giopci_match, giopci_attach, NULL, NULL); 104 105 static void pcimem_bus_mem_init(bus_space_tag_t, void *); 106 static struct mips_bus_space pcimem_mbst; 107 bus_space_tag_t gio_pci_memt = NULL; 108 109 static int 110 giopci_match(device_t parent, cfdata_t match, void *aux) 111 { 112 struct gio_attach_args *ga = aux; 113 int gprid; 114 115 /* 116 * I think that these cards are all GIO32-bis or GIO64. Thus 117 * they work in either Indigo2/Challenge M or 118 * Indy/Challenge S/Indigo R4k, according to form factor. However, 119 * there are some exceptions (e.g. my Indigo R4k won't power 120 * on with the Set Engineering card installed). 121 */ 122 if (mach_type != MACH_SGI_IP20 && mach_type != MACH_SGI_IP22) 123 return (0); 124 125 gprid = GIO_PRODUCT_PRODUCTID(ga->ga_product); 126 if (gprid == PHOBOS_G100 || gprid == PHOBOS_G130 || 127 gprid == PHOBOS_G160 || gprid == SETENG_GFE) 128 return (1); 129 130 return (0); 131 } 132 133 static void 134 giopci_attach(device_t parent, device_t self, void *aux) 135 { 136 struct giopci_softc *sc = device_private(self); 137 pci_chipset_tag_t pc = &sc->sc_pc; 138 struct gio_attach_args *ga = aux; 139 uint32_t pci_off, pci_len, arb; 140 struct pcibus_attach_args pba; 141 u_long m_start, m_end; 142 #ifdef PCI_NETBSD_CONFIGURE 143 extern int pci_conf_debug; 144 145 pci_conf_debug = giopci_debug; 146 #endif 147 148 sc->sc_iot = ga->ga_iot; 149 sc->sc_slot = ga->ga_slot; 150 sc->sc_gprid = GIO_PRODUCT_PRODUCTID(ga->ga_product); 151 152 pcimem_bus_mem_init(&pcimem_mbst, NULL); 153 gio_pci_memt = &pcimem_mbst; 154 155 if (mach_type == MACH_SGI_IP22 && 156 mach_subtype == MACH_SGI_IP22_FULLHOUSE) 157 arb = GIO_ARB_RT | GIO_ARB_MST | GIO_ARB_PIPE; 158 else 159 arb = GIO_ARB_RT | GIO_ARB_MST; 160 161 if (gio_arb_config(ga->ga_slot, arb)) { 162 printf(": failed to configure GIO bus arbiter\n"); 163 return; 164 } 165 166 #if (NIMC > 0) 167 imc_disable_sysad_parity(); 168 #endif 169 170 switch (sc->sc_gprid) { 171 case PHOBOS_G100: 172 case PHOBOS_G130: 173 case PHOBOS_G160: 174 pci_off = PHOBOS_PCI_OFFSET; 175 pci_len = PHOBOS_PCI_LENGTH; 176 m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_START); 177 m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_END); 178 break; 179 180 case SETENG_GFE: 181 /* 182 * NB: The SetEng board does not allow the ThunderLAN's DMA 183 * engine to properly transfer segments that span page 184 * boundaries. See sgimips/autoconf.c where we catch a 185 * tl(4) device attachment and create an appropriate 186 * proplib entry to enable the workaround. 187 */ 188 pci_off = SETENG_PCI_OFFSET; 189 pci_len = SETENG_PCI_LENGTH; 190 m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_START); 191 m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_END); 192 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 193 SETENG_MAGIC_OFFSET, SETENG_MAGIC_VALUE); 194 break; 195 196 default: 197 panic("giopci_attach: unsupported GIO product id 0x%02x", 198 sc->sc_gprid); 199 } 200 201 if (bus_space_subregion(ga->ga_iot, ga->ga_ioh, pci_off, pci_len, 202 &sc->sc_ioh)) { 203 printf("%s: unable to map PCI registers\n", device_xname(self)); 204 return; 205 } 206 sc->sc_pci_len = pci_len; 207 208 pc->pc_bus_maxdevs = giopci_bus_maxdevs; 209 pc->pc_conf_read = giopci_conf_read; 210 pc->pc_conf_write = giopci_conf_write; 211 pc->pc_conf_hook = giopci_conf_hook; 212 pc->pc_intr_map = giopci_intr_map; 213 pc->pc_intr_string = giopci_intr_string; 214 pc->intr_establish = giopci_intr_establish; 215 pc->intr_disestablish = giopci_intr_disestablish; 216 pc->iot = ga->ga_iot; 217 pc->ioh = ga->ga_ioh; 218 pc->cookie = sc; 219 220 printf(": %s\n", gio_product_string(sc->sc_gprid)); 221 222 #ifdef PCI_NETBSD_CONFIGURE 223 pc->pc_memext = extent_create("giopcimem", m_start, m_end, 224 NULL, 0, EX_NOWAIT); 225 pci_configure_bus(pc, NULL, pc->pc_memext, NULL, 0, 226 mips_cache_info.mci_dcache_align); 227 #endif 228 229 memset(&pba, 0, sizeof(pba)); 230 pba.pba_memt = gio_pci_memt; 231 pba.pba_dmat = ga->ga_dmat; 232 pba.pba_pc = pc; 233 pba.pba_flags = PCI_FLAGS_MEM_OKAY; 234 /* NB: do not set PCI_FLAGS_{MRL,MRM,MWI}_OKAY -- true ?! */ 235 236 config_found_ia(self, "pcibus", &pba, pcibusprint); 237 } 238 239 static int 240 giopci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 241 { 242 243 return (busno == 0); 244 } 245 246 static pcireg_t 247 giopci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 248 { 249 struct giopci_softc *sc = pc->cookie; 250 int bus, dev, func; 251 pcireg_t data; 252 253 pci_decompose_tag(pc, tag, &bus, &dev, &func); 254 if (bus != 0 || dev != 0 || func != 0) 255 return (0); 256 257 /* XXX - should just use bus_space_peek */ 258 if (reg >= sc->sc_pci_len) { 259 DPRINTF(("giopci_conf_read: reg 0x%x out of bounds\n", reg)); 260 return (0); 261 } 262 263 DPRINTF(("giopci_conf_read: reg 0x%x = 0x", reg)); 264 data = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg); 265 DPRINTF(("%08x\n", data)); 266 267 return (data); 268 } 269 270 static void 271 giopci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 272 { 273 struct giopci_softc *sc = pc->cookie; 274 int bus, dev, func; 275 276 pci_decompose_tag(pc, tag, &bus, &dev, &func); 277 if (bus != 0 || dev != 0 || func != 0) 278 return; 279 280 /* XXX - should just use bus_space_poke */ 281 if (reg >= sc->sc_pci_len) { 282 DPRINTF(("giopci_conf_write: reg 0x%x out of bounds " 283 "(val = 0x%08x)\n", reg, data)); 284 return; 285 } 286 287 DPRINTF(("giopci_conf_write: reg 0x%x = 0x%08x\n", reg, data)); 288 bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, data); 289 } 290 291 static int 292 giopci_conf_hook(pci_chipset_tag_t pc, int bus, int device, int function, 293 pcireg_t id) 294 { 295 296 /* All devices use memory accesses only. */ 297 return (PCI_CONF_MAP_MEM | PCI_CONF_ENABLE_MEM | PCI_CONF_ENABLE_BM); 298 } 299 300 static int 301 giopci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 302 { 303 struct giopci_softc *sc = pa->pa_pc->cookie; 304 305 *ihp = sc->sc_slot; 306 307 return (0); 308 } 309 310 static const char * 311 giopci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char * buf, 312 size_t len) 313 { 314 snprintf(buf, len, "slot %s", (ih == GIO_SLOT_EXP0) ? "EXP0" : 315 (ih == GIO_SLOT_EXP1) ? "EXP1" : "GFX"); 316 return buf; 317 } 318 319 static void * 320 giopci_intr_establish(int slot, int level, int (*func)(void *), void *arg) 321 { 322 323 return (gio_intr_establish(slot, level, func, arg)); 324 } 325 326 static void 327 giopci_intr_disestablish(void *cookie) 328 { 329 330 panic("giopci_intr_disestablish: impossible."); 331 } 332 333 #define CHIP pcimem 334 #define CHIP_MEM /* defined */ 335 #define CHIP_WRONG_ENDIAN 336 337 #define CHIP_W1_BUS_START(v) 0x00000000UL 338 #define CHIP_W1_BUS_END(v) 0xffffffffUL 339 #define CHIP_W1_SYS_START(v) 0x00000000UL 340 #define CHIP_W1_SYS_END(v) 0xffffffffUL 341 342 #include <mips/mips/bus_space_alignstride_chipdep.c> 343
Indexes created Tue Sep 30 20:09:53 GMT 2025