pci_gio.c revision 1.2
1 /* $NetBSD: pci_gio.c,v 1.2 2006/09/07 18:24:05 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Stephen M. Rumble 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: pci_gio.c,v 1.2 2006/09/07 18:24:05 rumble Exp $"); 29 30 /* 31 * Glue for PCI devices that are connected to the GIO bus by various little 32 * GIO<->PCI ASICs. 33 * 34 * We presently support the following boards: 35 * o Phobos G100/G130/G160 (if_tlp, lxtphy) 36 * o Set Engineering GFE (if_tl, nsphy) 37 * 38 * XXX - G100 and G160 are untested. The former may use an older chipset, 39 * (21140, I think) though the latter should be essentially identical to 40 * the G130. 41 */ 42 43 #include "opt_pci.h" 44 #include "pci.h" 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/malloc.h> 50 #include <sys/extent.h> 51 52 #include <machine/bus.h> 53 #include <machine/machtype.h> 54 55 #include <sgimips/gio/giovar.h> 56 #include <sgimips/gio/gioreg.h> 57 #include <sgimips/gio/giodevs.h> 58 59 #include <sgimips/dev/imcvar.h> 60 61 #include <mips/cache.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 #include <dev/pci/pciconf.h> 67 68 int giopci_debug = 0; 69 #define DPRINTF(_x) if (giopci_debug) printf _x 70 71 struct giopci_softc { 72 struct device sc_dev; 73 struct sgimips_pci_chipset sc_pc; 74 int sc_slot; 75 int sc_gprid; 76 uint32_t sc_pci_len; 77 bus_space_tag_t sc_iot; 78 bus_space_handle_t sc_ioh; 79 }; 80 81 static int giopci_match(struct device *, struct cfdata *, void *); 82 static void giopci_attach(struct device *, struct device *, void *); 83 static int giopci_bus_maxdevs(pci_chipset_tag_t, int); 84 static pcireg_t giopci_conf_read(pci_chipset_tag_t, pcitag_t, int); 85 static void giopci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 86 static int giopci_conf_hook(pci_chipset_tag_t, int, int, int, pcireg_t); 87 static int giopci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 88 static const char * 89 giopci_intr_string(pci_chipset_tag_t, pci_intr_handle_t); 90 static void *giopci_intr_establish(int, int, int (*)(void *), void *); 91 static void giopci_intr_disestablish(void *); 92 93 #define PHOBOS_PCI_OFFSET 0x00100000 94 #define PHOBOS_PCI_LENGTH 128 /* ~arbitrary */ 95 #define PHOBOS_TULIP_START 0x00101000 96 #define PHOBOS_TULIP_END 0x001fffff 97 98 #define SETENG_MAGIC_OFFSET 0x00020000 99 #define SETENG_MAGIC_VALUE 0x00001000 100 #define SETENG_PCI_OFFSET 0x00080000 101 #define SETENG_PCI_LENGTH 128 /* ~arbitrary */ 102 #define SETENG_TLAN_START 0x00100000 103 #define SETENG_TLAN_END 0x001fffff 104 105 CFATTACH_DECL(giopci, sizeof(struct giopci_softc), 106 giopci_match, giopci_attach, NULL, NULL); 107 108 static int 109 giopci_match(struct device *parent, struct cfdata *match, void *aux) 110 { 111 struct gio_attach_args *ga = aux; 112 int gprid; 113 114 /* 115 * I think that these cards are all GIO32-bis. Thus they work 116 * in Indy/Challenge-S and perhaps Indigo R4k as well, though 117 * there are some exceptions (e.g. my Indigo R4k won't power 118 * on with the Set Engineering card installed). 119 */ 120 if (mach_type != MACH_SGI_IP20 && mach_type != MACH_SGI_IP22) 121 return (0); 122 123 gprid = GIO_PRODUCT_PRODUCTID(ga->ga_product); 124 if (gprid == PHOBOS_G100 || gprid == PHOBOS_G130 || 125 gprid == PHOBOS_G160 || gprid == SETENG_GFE) 126 return (1); 127 128 return (0); 129 } 130 131 static void 132 giopci_attach(struct device *parent, struct device *self, void *aux) 133 { 134 struct giopci_softc *sc = (void *)self; 135 pci_chipset_tag_t pc = &sc->sc_pc; 136 struct gio_attach_args *ga = aux; 137 uint32_t pci_off, pci_len, arb; 138 struct pcibus_attach_args pba; 139 u_long m_start, m_end; 140 #ifdef PCI_NETBSD_CONFIGURE 141 extern int pci_conf_debug; 142 143 pci_conf_debug = giopci_debug; 144 #endif 145 146 sc->sc_iot = ga->ga_iot; 147 sc->sc_slot = ga->ga_slot; 148 sc->sc_gprid = GIO_PRODUCT_PRODUCTID(ga->ga_product); 149 150 if (mach_type == MACH_SGI_IP22 && 151 mach_subtype == MACH_SGI_IP22_FULLHOUSE) 152 arb = GIO_ARB_RT | GIO_ARB_MST | GIO_ARB_PIPE; 153 else 154 arb = GIO_ARB_RT | GIO_ARB_MST; 155 156 if (gio_arb_config(ga->ga_slot, arb)) { 157 printf(": failed to configure GIO bus arbiter\n"); 158 return; 159 } 160 161 #if (NIMC > 0) 162 imc_disable_sysad_parity(); 163 #endif 164 165 switch (sc->sc_gprid) { 166 case PHOBOS_G100: 167 case PHOBOS_G130: 168 case PHOBOS_G160: 169 pci_off = PHOBOS_PCI_OFFSET; 170 pci_len = PHOBOS_PCI_LENGTH; 171 m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_START); 172 m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_END); 173 break; 174 175 case SETENG_GFE: 176 pci_off = SETENG_PCI_OFFSET; 177 pci_len = SETENG_PCI_LENGTH; 178 m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_START); 179 m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_END); 180 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 181 SETENG_MAGIC_OFFSET, SETENG_MAGIC_VALUE); 182 break; 183 184 default: 185 panic("giopci_attach: unsupported GIO product id 0x%02x", 186 sc->sc_gprid); 187 } 188 189 if (bus_space_subregion(ga->ga_iot, ga->ga_ioh, pci_off, pci_len, 190 &sc->sc_ioh)) { 191 printf("%s: unable to map PCI registers\n",sc->sc_dev.dv_xname); 192 return; 193 } 194 sc->sc_pci_len = pci_len; 195 196 pc->pc_bus_maxdevs = giopci_bus_maxdevs; 197 pc->pc_conf_read = giopci_conf_read; 198 pc->pc_conf_write = giopci_conf_write; 199 pc->pc_conf_hook = giopci_conf_hook; 200 pc->pc_intr_map = giopci_intr_map; 201 pc->pc_intr_string = giopci_intr_string; 202 pc->intr_establish = giopci_intr_establish; 203 pc->intr_disestablish = giopci_intr_disestablish; 204 pc->iot = ga->ga_iot; 205 pc->ioh = ga->ga_ioh; 206 pc->cookie = sc; 207 208 printf(": %s\n", gio_product_string(sc->sc_gprid)); 209 210 #ifdef PCI_NETBSD_CONFIGURE 211 pc->pc_memext = extent_create("giopcimem", m_start, m_end, 212 M_DEVBUF, NULL, 0, EX_NOWAIT); 213 pci_configure_bus(pc, NULL, pc->pc_memext, NULL, 0, mips_dcache_align); 214 #endif 215 216 memset(&pba, 0, sizeof(pba)); 217 pba.pba_memt = SGIMIPS_BUS_SPACE_MEM; 218 pba.pba_dmat = ga->ga_dmat; 219 pba.pba_pc = pc; 220 pba.pba_flags = PCI_FLAGS_MEM_ENABLED; 221 /* NB: do not set PCI_FLAGS_{MRL,MRM,MWI}_OKAY -- true ?! */ 222 223 config_found_ia(self, "pcibus", &pba, pcibusprint); 224 } 225 226 static int 227 giopci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 228 { 229 230 return (busno == 0); 231 } 232 233 static pcireg_t 234 giopci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 235 { 236 struct giopci_softc *sc = pc->cookie; 237 int bus, dev, func; 238 pcireg_t data; 239 240 pci_decompose_tag(pc, tag, &bus, &dev, &func); 241 if (bus != 0 || dev != 0 || func != 0) 242 return (0); 243 244 /* XXX - should just use bus_space_peek */ 245 if (reg >= sc->sc_pci_len) { 246 DPRINTF(("giopci_conf_read: reg 0x%x out of bounds\n", reg)); 247 return (0); 248 } 249 250 DPRINTF(("giopci_conf_read: reg 0x%x = 0x", reg)); 251 data = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg); 252 DPRINTF(("%08x\n", data)); 253 254 return (data); 255 } 256 257 static void 258 giopci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 259 { 260 struct giopci_softc *sc = pc->cookie; 261 int bus, dev, func; 262 263 pci_decompose_tag(pc, tag, &bus, &dev, &func); 264 if (bus != 0 || dev != 0 || func != 0) 265 return; 266 267 /* XXX - should just use bus_space_poke */ 268 if (reg >= sc->sc_pci_len) { 269 DPRINTF(("giopci_conf_write: reg 0x%x out of bounds " 270 "(val = 0x%08x)\n", reg, data)); 271 return; 272 } 273 274 DPRINTF(("giopci_conf_write: reg 0x%x = 0x%08x\n", reg, data)); 275 bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, data); 276 } 277 278 static int 279 giopci_conf_hook(pci_chipset_tag_t pc, int bus, int device, int function, 280 pcireg_t id) 281 { 282 283 /* All devices use memory accesses only. */ 284 return (PCI_CONF_MAP_MEM | PCI_CONF_ENABLE_MEM | PCI_CONF_ENABLE_BM); 285 } 286 287 static int 288 giopci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 289 { 290 struct giopci_softc *sc = pa->pa_pc->cookie; 291 292 *ihp = sc->sc_slot; 293 294 return (0); 295 } 296 297 static const char * 298 giopci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 299 { 300 static char str[10]; 301 302 snprintf(str, sizeof(str), "slot %s", 303 (ih == GIO_SLOT_EXP0) ? "EXP0" : 304 (ih == GIO_SLOT_EXP1) ? "EXP1" : "GFX"); 305 return (str); 306 } 307 308 static void * 309 giopci_intr_establish(int slot, int level, int (*func)(void *), void *arg) 310 { 311 312 return (gio_intr_establish(slot, level, func, arg)); 313 } 314 315 static void 316 giopci_intr_disestablish(void *cookie) 317 { 318 319 panic("giopci_intr_disestablish: impossible."); 320 } 321
Indexes created Tue Sep 30 20:09:53 GMT 2025