pci_gio.c revision 1.3
1 /* $NetBSD: pci_gio.c,v 1.3 2006/12/22 22:42:47 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Stephen M. Rumble 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: pci_gio.c,v 1.3 2006/12/22 22:42:47 rumble Exp $"); 29 30 /* 31 * Glue for PCI devices that are connected to the GIO bus by various little 32 * GIO<->PCI ASICs. 33 * 34 * We presently support the following boards: 35 * o Phobos G100/G130/G160 (if_tlp, lxtphy) 36 * o Set Engineering GFE (if_tl, nsphy) 37 * 38 * XXX - G100 and G160 are untested. The former may use an older chipset, 39 * (21140, I think) though the latter should be essentially identical to 40 * the G130. 41 */ 42 43 #include "opt_pci.h" 44 #include "pci.h" 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/device.h> 49 #include <sys/malloc.h> 50 #include <sys/extent.h> 51 52 #include <machine/bus.h> 53 #include <machine/machtype.h> 54 55 #include <sgimips/gio/giovar.h> 56 #include <sgimips/gio/gioreg.h> 57 #include <sgimips/gio/giodevs.h> 58 59 #include <sgimips/dev/imcvar.h> 60 61 #include <mips/cache.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcidevs.h> 66 #include <dev/pci/pciconf.h> 67 68 int giopci_debug = 0; 69 #define DPRINTF(_x) if (giopci_debug) printf _x 70 71 struct giopci_softc { 72 struct device sc_dev; 73 struct sgimips_pci_chipset sc_pc; 74 int sc_slot; 75 int sc_gprid; 76 uint32_t sc_pci_len; 77 bus_space_tag_t sc_iot; 78 bus_space_handle_t sc_ioh; 79 }; 80 81 static int giopci_match(struct device *, struct cfdata *, void *); 82 static void giopci_attach(struct device *, struct device *, void *); 83 static int giopci_bus_maxdevs(pci_chipset_tag_t, int); 84 static pcireg_t giopci_conf_read(pci_chipset_tag_t, pcitag_t, int); 85 static void giopci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 86 static int giopci_conf_hook(pci_chipset_tag_t, int, int, int, pcireg_t); 87 static int giopci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 88 static const char * 89 giopci_intr_string(pci_chipset_tag_t, pci_intr_handle_t); 90 static void *giopci_intr_establish(int, int, int (*)(void *), void *); 91 static void giopci_intr_disestablish(void *); 92 93 #define PHOBOS_PCI_OFFSET 0x00100000 94 #define PHOBOS_PCI_LENGTH 128 /* ~arbitrary */ 95 #define PHOBOS_TULIP_START 0x00101000 96 #define PHOBOS_TULIP_END 0x001fffff 97 98 #define SETENG_MAGIC_OFFSET 0x00020000 99 #define SETENG_MAGIC_VALUE 0x00001000 100 #define SETENG_PCI_OFFSET 0x00080000 101 #define SETENG_PCI_LENGTH 128 /* ~arbitrary */ 102 #define SETENG_TLAN_START 0x00100000 103 #define SETENG_TLAN_END 0x001fffff 104 105 CFATTACH_DECL(giopci, sizeof(struct giopci_softc), 106 giopci_match, giopci_attach, NULL, NULL); 107 108 static int 109 giopci_match(struct device *parent, struct cfdata *match, void *aux) 110 { 111 struct gio_attach_args *ga = aux; 112 int gprid; 113 114 /* 115 * I think that these cards are all GIO32-bis or GIO64. Thus 116 * they work in either Indigo2/Challenge M or 117 * Indy/Challenge S/Indigo R4k, according to form factor. However, 118 * there are some exceptions (e.g. my Indigo R4k won't power 119 * on with the Set Engineering card installed). 120 */ 121 if (mach_type != MACH_SGI_IP20 && mach_type != MACH_SGI_IP22) 122 return (0); 123 124 gprid = GIO_PRODUCT_PRODUCTID(ga->ga_product); 125 if (gprid == PHOBOS_G100 || gprid == PHOBOS_G130 || 126 gprid == PHOBOS_G160 || gprid == SETENG_GFE) 127 return (1); 128 129 return (0); 130 } 131 132 static void 133 giopci_attach(struct device *parent, struct device *self, void *aux) 134 { 135 struct giopci_softc *sc = (void *)self; 136 pci_chipset_tag_t pc = &sc->sc_pc; 137 struct gio_attach_args *ga = aux; 138 uint32_t pci_off, pci_len, arb; 139 struct pcibus_attach_args pba; 140 u_long m_start, m_end; 141 #ifdef PCI_NETBSD_CONFIGURE 142 extern int pci_conf_debug; 143 144 pci_conf_debug = giopci_debug; 145 #endif 146 147 sc->sc_iot = ga->ga_iot; 148 sc->sc_slot = ga->ga_slot; 149 sc->sc_gprid = GIO_PRODUCT_PRODUCTID(ga->ga_product); 150 151 if (mach_type == MACH_SGI_IP22 && 152 mach_subtype == MACH_SGI_IP22_FULLHOUSE) 153 arb = GIO_ARB_RT | GIO_ARB_MST | GIO_ARB_PIPE; 154 else 155 arb = GIO_ARB_RT | GIO_ARB_MST; 156 157 if (gio_arb_config(ga->ga_slot, arb)) { 158 printf(": failed to configure GIO bus arbiter\n"); 159 return; 160 } 161 162 #if (NIMC > 0) 163 imc_disable_sysad_parity(); 164 #endif 165 166 switch (sc->sc_gprid) { 167 case PHOBOS_G100: 168 case PHOBOS_G130: 169 case PHOBOS_G160: 170 pci_off = PHOBOS_PCI_OFFSET; 171 pci_len = PHOBOS_PCI_LENGTH; 172 m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_START); 173 m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_END); 174 break; 175 176 case SETENG_GFE: 177 pci_off = SETENG_PCI_OFFSET; 178 pci_len = SETENG_PCI_LENGTH; 179 m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_START); 180 m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_END); 181 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 182 SETENG_MAGIC_OFFSET, SETENG_MAGIC_VALUE); 183 break; 184 185 default: 186 panic("giopci_attach: unsupported GIO product id 0x%02x", 187 sc->sc_gprid); 188 } 189 190 if (bus_space_subregion(ga->ga_iot, ga->ga_ioh, pci_off, pci_len, 191 &sc->sc_ioh)) { 192 printf("%s: unable to map PCI registers\n",sc->sc_dev.dv_xname); 193 return; 194 } 195 sc->sc_pci_len = pci_len; 196 197 pc->pc_bus_maxdevs = giopci_bus_maxdevs; 198 pc->pc_conf_read = giopci_conf_read; 199 pc->pc_conf_write = giopci_conf_write; 200 pc->pc_conf_hook = giopci_conf_hook; 201 pc->pc_intr_map = giopci_intr_map; 202 pc->pc_intr_string = giopci_intr_string; 203 pc->intr_establish = giopci_intr_establish; 204 pc->intr_disestablish = giopci_intr_disestablish; 205 pc->iot = ga->ga_iot; 206 pc->ioh = ga->ga_ioh; 207 pc->cookie = sc; 208 209 printf(": %s\n", gio_product_string(sc->sc_gprid)); 210 211 #ifdef PCI_NETBSD_CONFIGURE 212 pc->pc_memext = extent_create("giopcimem", m_start, m_end, 213 M_DEVBUF, NULL, 0, EX_NOWAIT); 214 pci_configure_bus(pc, NULL, pc->pc_memext, NULL, 0, mips_dcache_align); 215 #endif 216 217 memset(&pba, 0, sizeof(pba)); 218 pba.pba_memt = SGIMIPS_BUS_SPACE_MEM; 219 pba.pba_dmat = ga->ga_dmat; 220 pba.pba_pc = pc; 221 pba.pba_flags = PCI_FLAGS_MEM_ENABLED; 222 /* NB: do not set PCI_FLAGS_{MRL,MRM,MWI}_OKAY -- true ?! */ 223 224 config_found_ia(self, "pcibus", &pba, pcibusprint); 225 } 226 227 static int 228 giopci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 229 { 230 231 return (busno == 0); 232 } 233 234 static pcireg_t 235 giopci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 236 { 237 struct giopci_softc *sc = pc->cookie; 238 int bus, dev, func; 239 pcireg_t data; 240 241 pci_decompose_tag(pc, tag, &bus, &dev, &func); 242 if (bus != 0 || dev != 0 || func != 0) 243 return (0); 244 245 /* XXX - should just use bus_space_peek */ 246 if (reg >= sc->sc_pci_len) { 247 DPRINTF(("giopci_conf_read: reg 0x%x out of bounds\n", reg)); 248 return (0); 249 } 250 251 DPRINTF(("giopci_conf_read: reg 0x%x = 0x", reg)); 252 data = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg); 253 DPRINTF(("%08x\n", data)); 254 255 return (data); 256 } 257 258 static void 259 giopci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 260 { 261 struct giopci_softc *sc = pc->cookie; 262 int bus, dev, func; 263 264 pci_decompose_tag(pc, tag, &bus, &dev, &func); 265 if (bus != 0 || dev != 0 || func != 0) 266 return; 267 268 /* XXX - should just use bus_space_poke */ 269 if (reg >= sc->sc_pci_len) { 270 DPRINTF(("giopci_conf_write: reg 0x%x out of bounds " 271 "(val = 0x%08x)\n", reg, data)); 272 return; 273 } 274 275 DPRINTF(("giopci_conf_write: reg 0x%x = 0x%08x\n", reg, data)); 276 bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, data); 277 } 278 279 static int 280 giopci_conf_hook(pci_chipset_tag_t pc, int bus, int device, int function, 281 pcireg_t id) 282 { 283 284 /* All devices use memory accesses only. */ 285 return (PCI_CONF_MAP_MEM | PCI_CONF_ENABLE_MEM | PCI_CONF_ENABLE_BM); 286 } 287 288 static int 289 giopci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 290 { 291 struct giopci_softc *sc = pa->pa_pc->cookie; 292 293 *ihp = sc->sc_slot; 294 295 return (0); 296 } 297 298 static const char * 299 giopci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih) 300 { 301 static char str[10]; 302 303 snprintf(str, sizeof(str), "slot %s", 304 (ih == GIO_SLOT_EXP0) ? "EXP0" : 305 (ih == GIO_SLOT_EXP1) ? "EXP1" : "GFX"); 306 return (str); 307 } 308 309 static void * 310 giopci_intr_establish(int slot, int level, int (*func)(void *), void *arg) 311 { 312 313 return (gio_intr_establish(slot, level, func, arg)); 314 } 315 316 static void 317 giopci_intr_disestablish(void *cookie) 318 { 319 320 panic("giopci_intr_disestablish: impossible."); 321 } 322
Indexes created Tue Sep 30 20:09:53 GMT 2025