hpc.c revision 1.22
1 /* $NetBSD: hpc.c,v 1.22 2003/12/16 11:59:04 sekiya Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang 5 * Copyright (c) 2001 Rafal K. Boni 6 * Copyright (c) 2001 Jason R. Thorpe 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.22 2003/12/16 11:59:04 sekiya Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/reboot.h> 44 45 #include <machine/machtype.h> 46 47 #include <sgimips/gio/gioreg.h> 48 #include <sgimips/gio/giovar.h> 49 50 #include <sgimips/hpc/hpcvar.h> 51 #include <sgimips/hpc/hpcreg.h> 52 #include <sgimips/ioc/iocreg.h> 53 54 #include "locators.h" 55 56 const struct hpc_device { 57 const char *hd_name; 58 bus_addr_t hd_devoff; 59 bus_addr_t hd_dmaoff; 60 int hd_irq; 61 int hd_sysmask; 62 } hpc_devices[] = { 63 { "zsc", 64 /* XXX Magic numbers */ 65 HPC_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0, 66 29, 67 HPCDEV_IP22 | HPCDEV_IP24 }, 68 69 { "pckbc", 70 HPC_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0, 71 28, 72 HPCDEV_IP22 | HPCDEV_IP24 }, 73 74 { "sq", 75 HPC_ENET_DEVREGS, HPC_ENET_REGS, 76 3, 77 HPCDEV_IP22 | HPCDEV_IP24 }, 78 79 { "sq", 80 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 81 3, 82 HPCDEV_IP20 }, 83 84 { "wdsc", 85 HPC_SCSI0_DEVREGS, HPC_SCSI0_REGS, 86 1, /* XXX 1 = IRQ_LOCAL0 + 1 */ 87 HPCDEV_IP22 | HPCDEV_IP24 }, 88 89 { "wdsc", 90 HPC_SCSI1_DEVREGS, HPC_SCSI1_REGS, 91 2, /* XXX 2 = IRQ_LOCAL0 + 2 */ 92 HPCDEV_IP22 }, 93 94 { "wdsc", 95 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 96 2, /* XXX 1 = IRQ_LOCAL0 + 2 */ 97 HPCDEV_IP20 }, 98 99 { "dpclock", 100 HPC1_PBUS_BBRAM, 0, 101 -1, 102 HPCDEV_IP20 }, 103 104 { "dsclock", 105 HPC_PBUS_BBRAM, 0, 106 -1, 107 HPCDEV_IP22 | HPCDEV_IP24 }, 108 109 { "haltwo", 110 HPC_PBUS_CH0_DEVREGS, HPC_PBUS_DMAREGS, 111 8 + 4, /* XXX IRQ_LOCAL1 + 4 */ 112 HPCDEV_IP22 | HPCDEV_IP24 }, 113 114 { NULL, 115 0, 0, 116 0, 117 0 118 } 119 }; 120 121 struct hpc_softc { 122 struct device sc_dev; 123 124 bus_addr_t sc_base; 125 126 bus_space_tag_t sc_ct; 127 bus_space_handle_t sc_ch; 128 }; 129 130 static struct hpc_values hpc1_values = { 131 15, 132 HPC1_SCSI0_REGS, 133 HPC1_SCSI0_REGS_SIZE, 134 HPC1_SCSI0_CBP, 135 HPC1_SCSI0_NDBP, 136 HPC1_SCSI0_BC, 137 HPC1_SCSI0_CTL, 138 HPC1_SCSI0_GIO, 139 HPC1_SCSI0_DEV, 140 HPC1_SCSI0_DMACFG, 141 HPC1_SCSI0_PIOCFG, 142 HPC1_SCSI1_REGS, 143 HPC1_SCSI1_REGS_SIZE, 144 HPC1_SCSI1_CBP, 145 HPC1_SCSI1_NDBP, 146 HPC1_SCSI1_BC, 147 HPC1_SCSI1_CTL, 148 HPC1_SCSI1_GIO, 149 HPC1_SCSI1_DEV, 150 HPC1_SCSI1_DMACFG, 151 HPC1_SCSI1_PIOCFG, 152 HPC1_DMACTL_DIR, 153 HPC1_DMACTL_FLUSH, 154 HPC1_DMACTL_ACTIVE, 155 HPC1_DMACTL_RESET, 156 HPC1_ENET_REGS, 157 HPC1_ENET_REGS_SIZE, 158 HPC1_ENET_INTDELAY, 159 HPC1_ENET_INTDELAYVAL, 160 HPC1_ENETR_CBP, 161 HPC1_ENETR_NDBP, 162 HPC1_ENETR_BC, 163 HPC1_ENETR_CTL, 164 HPC1_ENETR_CTL_ACTIVE, 165 HPC1_ENETR_RESET, 166 0, 167 HPC1_ENETR_PIOCFG, 168 HPC1_ENETX_CBP, 169 HPC1_ENETX_NDBP, 170 HPC1_ENETX_BC, 171 HPC1_ENETX_CTL, 172 HPC1_ENETX_CTL_ACTIVE, 173 HPC1_ENETX_DEV, 174 HPC1_ENETR_FIFO, 175 HPC1_ENETR_FIFO_SIZE, 176 HPC1_ENETX_FIFO, 177 HPC1_ENETX_FIFO_SIZE, 178 HPC1_SCSI0_DEVREGS_SIZE, 179 HPC1_SCSI0_DEVREGS_SIZE, 180 HPC1_ENET_DEVREGS, 181 HPC1_ENET_DEVREGS_SIZE, 182 HPC1_PBUS_FIFO, 183 HPC1_PBUS_FIFO_SIZE, 184 HPC1_PBUS_BBRAM, 185 #define MAX_SCSI_XFER (512*1024) 186 (MAX_SCSI_XFER / 4096), 187 4096, 188 100, 189 (HPC1_DMACTL_ACTIVE | HPC1_DMACTL_DIR), 190 HPC1_DMACTL_ACTIVE, 191 HPC1_DMACTL_FLUSH, 192 HPC1_DMACTL_ACTIVE, 193 HPC1_DMACTL_RESET 194 }; 195 196 static struct hpc_values hpc3_values = { 197 3, 198 HPC_SCSI0_REGS, 199 HPC_SCSI0_REGS_SIZE, 200 HPC_SCSI0_CBP, 201 HPC_SCSI0_NDBP, 202 HPC_SCSI0_BC, 203 HPC_SCSI0_CTL, 204 HPC_SCSI0_GIO, 205 HPC_SCSI0_DEV, 206 HPC_SCSI0_DMACFG, 207 HPC_SCSI0_PIOCFG, 208 HPC_SCSI1_REGS, 209 HPC_SCSI1_REGS_SIZE, 210 HPC_SCSI1_CBP, 211 HPC_SCSI1_NDBP, 212 HPC_SCSI1_BC, 213 HPC_SCSI1_CTL, 214 HPC_SCSI1_GIO, 215 HPC_SCSI1_DEV, 216 HPC_SCSI1_DMACFG, 217 HPC_SCSI1_PIOCFG, 218 HPC_DMACTL_DIR, 219 HPC_DMACTL_FLUSH, 220 HPC_DMACTL_ACTIVE, 221 HPC_DMACTL_RESET, 222 HPC_ENET_REGS, 223 HPC_ENET_REGS_SIZE, 224 0, 225 0, 226 HPC_ENETR_CBP, 227 HPC_ENETR_NDBP, 228 HPC_ENETR_BC, 229 HPC_ENETR_CTL, 230 ENETR_CTL_ACTIVE, 231 HPC_ENETR_RESET, 232 HPC_ENETR_DMACFG, 233 HPC_ENETR_PIOCFG, 234 HPC_ENETX_CBP, 235 HPC_ENETX_NDBP, 236 HPC_ENETX_BC, 237 HPC_ENETX_CTL, 238 ENETX_CTL_ACTIVE, 239 HPC_ENETX_DEV, 240 HPC_ENETR_FIFO, 241 HPC_ENETR_FIFO_SIZE, 242 HPC_ENETX_FIFO, 243 HPC_ENETX_FIFO_SIZE, 244 HPC_SCSI0_DEVREGS_SIZE, 245 HPC_SCSI1_DEVREGS_SIZE, 246 HPC_ENET_DEVREGS, 247 HPC_ENET_DEVREGS_SIZE, 248 HPC_PBUS_FIFO, 249 HPC_PBUS_FIFO_SIZE, 250 HPC_PBUS_BBRAM, 251 (MAX_SCSI_XFER / 8192), 252 8192, 253 100, 254 HPC_DMACTL_ACTIVE, 255 (HPC_DMACTL_ACTIVE | HPC_DMACTL_DIR), 256 HPC_DMACTL_FLUSH, 257 HPC_DMACTL_ACTIVE, 258 HPC_DMACTL_RESET 259 }; 260 261 262 extern int mach_type; /* IPxx type */ 263 extern int mach_subtype; /* subtype: eg., Guiness/Fullhouse for IP22 */ 264 extern int mach_boardrev; /* machine board revision, in case it matters */ 265 266 extern struct sgimips_bus_dma_tag sgimips_default_bus_dma_tag; 267 268 static int powerintr_established; 269 270 int hpc_match(struct device *, struct cfdata *, void *); 271 void hpc_attach(struct device *, struct device *, void *); 272 int hpc_print(void *, const char *); 273 274 int hpc_submatch(struct device *, struct cfdata *, void *); 275 276 int hpc_power_intr(void *); 277 278 CFATTACH_DECL(hpc, sizeof(struct hpc_softc), 279 hpc_match, hpc_attach, NULL, NULL); 280 281 int 282 hpc_match(struct device *parent, struct cfdata *cf, void *aux) 283 { 284 struct gio_attach_args* ga = aux; 285 286 /* Make sure it's actually there and readable */ 287 if (badaddr((void*)MIPS_PHYS_TO_KSEG1(ga->ga_addr), sizeof(u_int32_t))) 288 return 0; 289 290 return 1; 291 } 292 293 void 294 hpc_attach(struct device *parent, struct device *self, void *aux) 295 { 296 struct hpc_softc *sc = (struct hpc_softc *)self; 297 struct gio_attach_args* ga = aux; 298 struct hpc_attach_args ha; 299 const struct hpc_device *hd; 300 int sysmask, hpctype; 301 302 switch (mach_type) { 303 case MACH_SGI_IP20: 304 hpctype = 15; 305 sysmask = HPCDEV_IP20; 306 break; 307 case MACH_SGI_IP22: 308 hpctype = 3; 309 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 310 sysmask = HPCDEV_IP22; 311 else 312 sysmask = HPCDEV_IP24; 313 break; 314 315 default: 316 panic("hpc_attach: can't handle HPC on an IP%d", 317 mach_type); 318 }; 319 320 printf(": SGI HPC%d\n", hpctype); 321 322 sc->sc_ct = 1; 323 sc->sc_ch = ga->ga_ioh; 324 325 sc->sc_base = ga->ga_addr; 326 327 for (hd = hpc_devices; hd->hd_name != NULL; hd++) { 328 if (!(hd->hd_sysmask & sysmask)) 329 continue; 330 331 ha.ha_name = hd->hd_name; 332 ha.ha_devoff = hd->hd_devoff; 333 ha.ha_dmaoff = hd->hd_dmaoff; 334 ha.ha_irq = hd->hd_irq; 335 336 /* XXX This is disgusting. */ 337 ha.ha_st = 1; 338 ha.ha_sh = MIPS_PHYS_TO_KSEG1(sc->sc_base); 339 ha.ha_dmat = &sgimips_default_bus_dma_tag; 340 if (hpctype == 3) 341 ha.hpc_regs = &hpc3_values; 342 else 343 ha.hpc_regs = &hpc1_values; 344 345 (void) config_found_sm(self, &ha, hpc_print, hpc_submatch); 346 } 347 348 /* 349 * XXX: Only attach the powerfail interrupt once, since the 350 * interrupt code doesn't let you share interrupt just yet. 351 * 352 * Since the powerfail interrupt is hardcoded to read from 353 * a specific register anyway (XXX#2!), we don't care when 354 * it gets attached, as long as it only happens once. 355 */ 356 if (!powerintr_established) { 357 cpu_intr_establish(9, IPL_NONE, hpc_power_intr, sc); 358 powerintr_established++; 359 } 360 } 361 362 int 363 hpc_submatch(struct device *parent, struct cfdata *cf, void *aux) 364 { 365 struct hpc_attach_args *ha = aux; 366 367 if (cf->cf_loc[HPCCF_OFFSET] != HPCCF_OFFSET_DEFAULT && 368 (bus_addr_t) cf->cf_loc[HPCCF_OFFSET] != ha->ha_devoff) 369 return (0); 370 371 return (config_match(parent, cf, aux)); 372 } 373 374 int 375 hpc_print(void *aux, const char *pnp) 376 { 377 struct hpc_attach_args *ha = aux; 378 379 if (pnp) 380 printf("%s at %s", ha->ha_name, pnp); 381 382 printf(" offset 0x%lx", ha->ha_devoff); 383 384 return (UNCONF); 385 } 386 387 int 388 hpc_power_intr(void *arg) 389 { 390 u_int32_t pwr_reg; 391 392 pwr_reg = *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)); 393 *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)) = pwr_reg; 394 395 printf("hpc_power_intr: panel reg = %08x\n", pwr_reg); 396 397 if (pwr_reg & 2) 398 cpu_reboot(RB_HALT, NULL); 399 400 return 1; 401 } 402
Indexes created Mon Sep 22 13:09:51 GMT 2025