hpc.c revision 1.23
1 /* $NetBSD: hpc.c,v 1.23 2003/12/29 06:33:57 sekiya Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang 5 * Copyright (c) 2001 Rafal K. Boni 6 * Copyright (c) 2001 Jason R. Thorpe 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.23 2003/12/29 06:33:57 sekiya Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/reboot.h> 44 45 #include <machine/machtype.h> 46 47 #include <sgimips/gio/gioreg.h> 48 #include <sgimips/gio/giovar.h> 49 50 #include <sgimips/hpc/hpcvar.h> 51 #include <sgimips/hpc/hpcreg.h> 52 #include <sgimips/ioc/iocreg.h> 53 54 #include "locators.h" 55 56 const struct hpc_device { 57 const char *hd_name; 58 bus_addr_t hd_devoff; 59 bus_addr_t hd_dmaoff; 60 int hd_irq; 61 int hd_sysmask; 62 } hpc_devices[] = { 63 { "zsc", 64 /* XXX Magic numbers */ 65 HPC_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0, 66 29, 67 HPCDEV_IP22 | HPCDEV_IP24 }, 68 69 { "pckbc", 70 HPC_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0, 71 28, 72 HPCDEV_IP22 | HPCDEV_IP24 }, 73 74 { "sq", 75 HPC_ENET_DEVREGS, HPC_ENET_REGS, 76 3, 77 HPCDEV_IP22 | HPCDEV_IP24 }, 78 79 { "sq", 80 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 81 3, 82 HPCDEV_IP20 }, 83 84 { "wdsc", 85 HPC_SCSI0_DEVREGS, HPC_SCSI0_REGS, 86 1, /* XXX 1 = IRQ_LOCAL0 + 1 */ 87 HPCDEV_IP22 | HPCDEV_IP24 }, 88 89 { "wdsc", 90 HPC_SCSI1_DEVREGS, HPC_SCSI1_REGS, 91 2, /* XXX 2 = IRQ_LOCAL0 + 2 */ 92 HPCDEV_IP22 }, 93 94 { "wdsc", 95 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 96 2, /* XXX 1 = IRQ_LOCAL0 + 2 */ 97 HPCDEV_IP20 }, 98 99 { "dpclock", 100 HPC1_PBUS_BBRAM, 0, 101 -1, 102 HPCDEV_IP20 }, 103 104 { "dsclock", 105 HPC_PBUS_BBRAM, 0, 106 -1, 107 HPCDEV_IP22 | HPCDEV_IP24 }, 108 109 { "haltwo", 110 HPC_PBUS_CH0_DEVREGS, HPC_PBUS_DMAREGS, 111 8 + 4, /* XXX IRQ_LOCAL1 + 4 */ 112 HPCDEV_IP22 | HPCDEV_IP24 }, 113 114 { NULL, 115 0, 0, 116 0, 117 0 118 } 119 }; 120 121 struct hpc_softc { 122 struct device sc_dev; 123 124 bus_addr_t sc_base; 125 126 bus_space_tag_t sc_ct; 127 bus_space_handle_t sc_ch; 128 }; 129 130 static struct hpc_values hpc1_values = { 131 .revision = 1, 132 .scsi0_regs = HPC1_SCSI0_REGS, 133 .scsi0_regs_size = HPC1_SCSI0_REGS_SIZE, 134 .scsi0_cbp = HPC1_SCSI0_CBP, 135 .scsi0_ndbp = HPC1_SCSI0_NDBP, 136 .scsi0_bc = HPC1_SCSI0_BC, 137 .scsi0_ctl = HPC1_SCSI0_CTL, 138 .scsi0_gio = HPC1_SCSI0_GIO, 139 .scsi0_dev = HPC1_SCSI0_DEV, 140 .scsi0_dmacfg = HPC1_SCSI0_DMACFG, 141 .scsi0_piocfg = HPC1_SCSI0_PIOCFG, 142 .scsi1_regs = HPC1_SCSI1_REGS, 143 .scsi1_regs_size = HPC1_SCSI1_REGS_SIZE, 144 .scsi1_cbp = HPC1_SCSI1_CBP, 145 .scsi1_ndbp = HPC1_SCSI1_NDBP, 146 .scsi1_bc = HPC1_SCSI1_BC, 147 .scsi1_ctl = HPC1_SCSI1_CTL, 148 .scsi1_gio = HPC1_SCSI1_GIO, 149 .scsi1_dev = HPC1_SCSI1_DEV, 150 .scsi1_dmacfg = HPC1_SCSI1_DMACFG, 151 .scsi1_piocfg = HPC1_SCSI1_PIOCFG, 152 .dmactl_dir = HPC1_DMACTL_DIR, 153 .dmactl_flush = HPC1_DMACTL_FLUSH, 154 .dmactl_active = HPC1_DMACTL_ACTIVE, 155 .dmactl_reset = HPC1_DMACTL_RESET, 156 .enet_regs = HPC1_ENET_REGS, 157 .enet_regs_size = HPC1_ENET_REGS_SIZE, 158 .enet_intdelay = HPC1_ENET_INTDELAY, 159 .enet_intdelayval = HPC1_ENET_INTDELAYVAL, 160 .enetr_cbp = HPC1_ENETR_CBP, 161 .enetr_ndbp = HPC1_ENETR_NDBP, 162 .enetr_bc = HPC1_ENETR_BC, 163 .enetr_ctl = HPC1_ENETR_CTL, 164 .enetr_ctl_active = HPC1_ENETR_CTL_ACTIVE, 165 .enetr_reset = HPC1_ENETR_RESET, 166 .enetr_dmacfg = 0, 167 .enetr_piocfg = HPC1_ENETR_PIOCFG, 168 .enetx_cbp = HPC1_ENETX_CBP, 169 .enetx_ndbp = HPC1_ENETX_NDBP, 170 .enetx_bc = HPC1_ENETX_BC, 171 .enetx_ctl = HPC1_ENETX_CTL, 172 .enetx_ctl_active = HPC1_ENETX_CTL_ACTIVE, 173 .enetx_dev = HPC1_ENETX_DEV, 174 .enetr_fifo = HPC1_ENETR_FIFO, 175 .enetr_fifo_size = HPC1_ENETR_FIFO_SIZE, 176 .enetx_fifo = HPC1_ENETX_FIFO, 177 .enetx_fifo_size = HPC1_ENETX_FIFO_SIZE, 178 .scsi0_devregs_size = HPC1_SCSI0_DEVREGS_SIZE, 179 .scsi1_devregs_size = HPC1_SCSI0_DEVREGS_SIZE, 180 .enet_devregs = HPC1_ENET_DEVREGS, 181 .enet_devregs_size = HPC1_ENET_DEVREGS_SIZE, 182 .pbus_fifo = HPC1_PBUS_FIFO, 183 .pbus_fifo_size = HPC1_PBUS_FIFO_SIZE, 184 .pbus_bbram = HPC1_PBUS_BBRAM, 185 #define MAX_SCSI_XFER (512*1024) 186 .scsi_max_xfer = MAX_SCSI_XFER, 187 .scsi_dma_segs = (MAX_SCSI_XFER / 4096), 188 .scsi_dma_segs_size = 4096, 189 .clk_freq = 100, 190 .dma_datain_cmd = (HPC1_DMACTL_ACTIVE | HPC1_DMACTL_DIR), 191 .dma_dataout_cmd = HPC1_DMACTL_ACTIVE, 192 .scsi_dmactl_flush = HPC1_DMACTL_FLUSH, 193 .scsi_dmactl_active = HPC1_DMACTL_ACTIVE, 194 .scsi_dmactl_reset = HPC1_DMACTL_RESET 195 }; 196 197 static struct hpc_values hpc3_values = { 198 .revision 3, 199 .scsi0_regs = HPC_SCSI0_REGS, 200 .scsi0_regs_size = HPC_SCSI0_REGS_SIZE, 201 .scsi0_cbp = HPC_SCSI0_CBP, 202 .scsi0_ndbp = HPC_SCSI0_NDBP, 203 .scsi0_bc = HPC_SCSI0_BC, 204 .scsi0_ctl = HPC_SCSI0_CTL, 205 .scsi0_gio = HPC_SCSI0_GIO, 206 .scsi0_dev = HPC_SCSI0_DEV, 207 .scsi0_dmacfg = HPC_SCSI0_DMACFG, 208 .scsi0_piocfg = HPC_SCSI0_PIOCFG, 209 .scsi1_regs = HPC_SCSI1_REGS, 210 .scsi1_regs_size = HPC_SCSI1_REGS_SIZE, 211 .scsi1_cbp = HPC_SCSI1_CBP, 212 .scsi1_ndbp = HPC_SCSI1_NDBP, 213 .scsi1_bc = HPC_SCSI1_BC, 214 .scsi1_ctl = HPC_SCSI1_CTL, 215 .scsi1_gio = HPC_SCSI1_GIO, 216 .scsi1_dev = HPC_SCSI1_DEV, 217 .scsi1_dmacfg = HPC_SCSI1_DMACFG, 218 .scsi1_piocfg = HPC_SCSI1_PIOCFG, 219 .dmactl_dir = HPC_DMACTL_DIR, 220 .dmactl_flush = HPC_DMACTL_FLUSH, 221 .dmactl_active = HPC_DMACTL_ACTIVE, 222 .dmactl_reset = HPC_DMACTL_RESET, 223 .enet_regs = HPC_ENET_REGS, 224 .enet_regs_size = HPC_ENET_REGS_SIZE, 225 .enet_intdelay = 0, 226 .enet_intdelayval = 0, 227 .enetr_cbp = HPC_ENETR_CBP, 228 .enetr_ndbp = HPC_ENETR_NDBP, 229 .enetr_bc = HPC_ENETR_BC, 230 .enetr_ctl = HPC_ENETR_CTL, 231 .enetr_ctl_active = ENETR_CTL_ACTIVE, 232 .enetr_reset = HPC_ENETR_RESET, 233 .enetr_dmacfg = HPC_ENETR_DMACFG, 234 .enetr_piocfg = HPC_ENETR_PIOCFG, 235 .enetx_cbp = HPC_ENETX_CBP, 236 .enetx_ndbp = HPC_ENETX_NDBP, 237 .enetx_bc = HPC_ENETX_BC, 238 .enetx_ctl = HPC_ENETX_CTL, 239 .enetx_ctl_active = ENETX_CTL_ACTIVE, 240 .enetx_dev = HPC_ENETX_DEV, 241 .enetr_fifo = HPC_ENETR_FIFO, 242 .enetr_fifo_size = HPC_ENETR_FIFO_SIZE, 243 .enetx_fifo = HPC_ENETX_FIFO, 244 .enetx_fifo_size = HPC_ENETX_FIFO_SIZE, 245 .scsi0_devregs_size = HPC_SCSI0_DEVREGS_SIZE, 246 .scsi1_devregs_size = HPC_SCSI1_DEVREGS_SIZE, 247 .enet_devregs = HPC_ENET_DEVREGS, 248 .enet_devregs_size = HPC_ENET_DEVREGS_SIZE, 249 .pbus_fifo = HPC_PBUS_FIFO, 250 .pbus_fifo_size = HPC_PBUS_FIFO_SIZE, 251 .pbus_bbram = HPC_PBUS_BBRAM, 252 .scsi_max_xfer = MAX_SCSI_XFER, 253 .scsi_dma_segs = (MAX_SCSI_XFER / 8192), 254 .scsi_dma_segs_size = 8192, 255 .clk_freq = 100, 256 .dma_datain_cmd = HPC_DMACTL_ACTIVE, 257 .dma_dataout_cmd = (HPC_DMACTL_ACTIVE | HPC_DMACTL_DIR), 258 .scsi_dmactl_flush = HPC_DMACTL_FLUSH, 259 .scsi_dmactl_active = HPC_DMACTL_ACTIVE, 260 .scsi_dmactl_reset = HPC_DMACTL_RESET 261 }; 262 263 264 extern int mach_type; /* IPxx type */ 265 extern int mach_subtype; /* subtype: eg., Guiness/Fullhouse for IP22 */ 266 extern int mach_boardrev; /* machine board revision, in case it matters */ 267 268 extern struct sgimips_bus_dma_tag sgimips_default_bus_dma_tag; 269 270 static int powerintr_established; 271 272 int hpc_match(struct device *, struct cfdata *, void *); 273 void hpc_attach(struct device *, struct device *, void *); 274 int hpc_print(void *, const char *); 275 276 int hpc_submatch(struct device *, struct cfdata *, void *); 277 278 int hpc_power_intr(void *); 279 280 CFATTACH_DECL(hpc, sizeof(struct hpc_softc), 281 hpc_match, hpc_attach, NULL, NULL); 282 283 int 284 hpc_match(struct device *parent, struct cfdata *cf, void *aux) 285 { 286 struct gio_attach_args* ga = aux; 287 288 /* Make sure it's actually there and readable */ 289 if (badaddr((void*)MIPS_PHYS_TO_KSEG1(ga->ga_addr), sizeof(u_int32_t))) 290 return 0; 291 292 return 1; 293 } 294 295 void 296 hpc_attach(struct device *parent, struct device *self, void *aux) 297 { 298 struct hpc_softc *sc = (struct hpc_softc *)self; 299 struct gio_attach_args* ga = aux; 300 struct hpc_attach_args ha; 301 const struct hpc_device *hd; 302 int sysmask, hpctype; 303 304 switch (mach_type) { 305 case MACH_SGI_IP20: 306 hpctype = 15; 307 sysmask = HPCDEV_IP20; 308 break; 309 310 case MACH_SGI_IP22: 311 hpctype = 3; 312 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 313 sysmask = HPCDEV_IP22; 314 else 315 sysmask = HPCDEV_IP24; 316 break; 317 318 default: 319 panic("hpc_attach: can't handle HPC on an IP%d", mach_type); 320 }; 321 322 /* Verify HPC1 or HPC1.5 */ 323 if (hpctype != 3) { 324 hpctype = *(u_int32_t *) 325 MIPS_PHYS_TO_KSEG1(ga->ga_addr + HPC1_BIGENDIAN); 326 327 if (((hpctype >> HPC1_REVSHIFT) & HPC1_REVMASK) == HPC1_REV15) 328 hpctype = 15; 329 else 330 hpctype = 1; 331 } 332 333 printf(": SGI HPC%d%s\n", (hpctype == 3) ? 3 : 1, 334 (hpctype == 15) ? ".5" : ""); 335 336 sc->sc_ct = 1; 337 sc->sc_ch = ga->ga_ioh; 338 339 sc->sc_base = ga->ga_addr; 340 341 for (hd = hpc_devices; hd->hd_name != NULL; hd++) { 342 if (!(hd->hd_sysmask & sysmask)) 343 continue; 344 345 ha.ha_name = hd->hd_name; 346 ha.ha_devoff = hd->hd_devoff; 347 ha.ha_dmaoff = hd->hd_dmaoff; 348 ha.ha_irq = hd->hd_irq; 349 350 /* XXX This is disgusting. */ 351 ha.ha_st = 1; 352 ha.ha_sh = MIPS_PHYS_TO_KSEG1(sc->sc_base); 353 ha.ha_dmat = &sgimips_default_bus_dma_tag; 354 if (hpctype == 3) 355 ha.hpc_regs = &hpc3_values; 356 else 357 ha.hpc_regs = &hpc1_values; 358 ha.hpc_regs->revision = hpctype; 359 360 (void) config_found_sm(self, &ha, hpc_print, hpc_submatch); 361 } 362 363 /* 364 * XXX: Only attach the powerfail interrupt once, since the 365 * interrupt code doesn't let you share interrupt just yet. 366 * 367 * Since the powerfail interrupt is hardcoded to read from 368 * a specific register anyway (XXX#2!), we don't care when 369 * it gets attached, as long as it only happens once. 370 */ 371 if (mach_type == MACH_SGI_IP22 && !powerintr_established) { 372 cpu_intr_establish(9, IPL_NONE, hpc_power_intr, sc); 373 powerintr_established++; 374 } 375 } 376 377 int 378 hpc_submatch(struct device *parent, struct cfdata *cf, void *aux) 379 { 380 struct hpc_attach_args *ha = aux; 381 382 if (cf->cf_loc[HPCCF_OFFSET] != HPCCF_OFFSET_DEFAULT && 383 (bus_addr_t) cf->cf_loc[HPCCF_OFFSET] != ha->ha_devoff) 384 return (0); 385 386 return (config_match(parent, cf, aux)); 387 } 388 389 int 390 hpc_print(void *aux, const char *pnp) 391 { 392 struct hpc_attach_args *ha = aux; 393 394 if (pnp) 395 printf("%s at %s", ha->ha_name, pnp); 396 397 printf(" offset 0x%lx", ha->ha_devoff); 398 399 return (UNCONF); 400 } 401 402 int 403 hpc_power_intr(void *arg) 404 { 405 u_int32_t pwr_reg; 406 407 pwr_reg = *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)); 408 *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)) = pwr_reg; 409 410 printf("hpc_power_intr: panel reg = %08x\n", pwr_reg); 411 412 if (pwr_reg & 2) 413 cpu_reboot(RB_HALT, NULL); 414 415 return 1; 416 } 417
Indexes created Mon Sep 22 05:09:51 GMT 2025