hpc.c revision 1.28
1 /* $NetBSD: hpc.c,v 1.28 2004/04/11 10:29:20 pooka Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang 5 * Copyright (c) 2001 Rafal K. Boni 6 * Copyright (c) 2001 Jason R. Thorpe 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.28 2004/04/11 10:29:20 pooka Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/reboot.h> 45 #include <sys/callout.h> 46 47 #include <machine/machtype.h> 48 49 #include <sgimips/gio/gioreg.h> 50 #include <sgimips/gio/giovar.h> 51 52 #include <sgimips/hpc/hpcvar.h> 53 #include <sgimips/hpc/hpcreg.h> 54 #include <sgimips/ioc/iocreg.h> 55 56 #include "locators.h" 57 58 const struct hpc_device { 59 const char *hd_name; 60 bus_addr_t hd_devoff; 61 bus_addr_t hd_dmaoff; 62 int hd_irq; 63 int hd_sysmask; 64 } hpc_devices[] = { 65 { "zsc", 66 /* XXX Magic numbers */ 67 HPC_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0, 68 29, 69 HPCDEV_IP22 | HPCDEV_IP24 }, 70 71 /* probe order is important for IP20 zsc */ 72 73 { "zsc", /* serial 0/1 duart 1 */ 74 0x0d10, 0, 75 5, 76 HPCDEV_IP12 | HPCDEV_IP20 }, 77 78 { "zsc", /* serial 0/1 duart 0 */ 79 0x0d00, 0, 80 5, 81 HPCDEV_IP12 | HPCDEV_IP20 }, 82 83 { "pckbc", 84 HPC_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0, 85 28, 86 HPCDEV_IP22 | HPCDEV_IP24 }, 87 88 { "sq", 89 HPC_ENET_DEVREGS, HPC_ENET_REGS, 90 3, 91 HPCDEV_IP22 | HPCDEV_IP24 }, 92 93 { "sq", 94 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 95 3, 96 HPCDEV_IP12 | HPCDEV_IP20 }, 97 98 { "wdsc", 99 HPC_SCSI0_DEVREGS, HPC_SCSI0_REGS, 100 1, /* XXX 1 = IRQ_LOCAL0 + 1 */ 101 HPCDEV_IP22 | HPCDEV_IP24 }, 102 103 { "wdsc", 104 HPC_SCSI1_DEVREGS, HPC_SCSI1_REGS, 105 2, /* XXX 2 = IRQ_LOCAL0 + 2 */ 106 HPCDEV_IP22 }, 107 108 { "wdsc", 109 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 110 2, /* XXX 1 = IRQ_LOCAL0 + 2 */ 111 HPCDEV_IP12 | HPCDEV_IP20 }, 112 113 { "dpclock", 114 HPC1_PBUS_BBRAM, 0, 115 -1, 116 HPCDEV_IP12 | HPCDEV_IP20 }, 117 118 { "dsclock", 119 HPC_PBUS_BBRAM, 0, 120 -1, 121 HPCDEV_IP22 | HPCDEV_IP24 }, 122 123 { "haltwo", 124 HPC_PBUS_CH0_DEVREGS, HPC_PBUS_DMAREGS, 125 8 + 4, /* XXX IRQ_LOCAL1 + 4 */ 126 HPCDEV_IP22 | HPCDEV_IP24 }, 127 128 { NULL, 129 0, 0, 130 0, 131 0 132 } 133 }; 134 135 struct hpc_softc { 136 struct device sc_dev; 137 138 bus_addr_t sc_base; 139 140 bus_space_tag_t sc_ct; 141 bus_space_handle_t sc_ch; 142 }; 143 144 static struct hpc_values hpc1_values = { 145 .revision = 1, 146 .scsi0_regs = HPC1_SCSI0_REGS, 147 .scsi0_regs_size = HPC1_SCSI0_REGS_SIZE, 148 .scsi0_cbp = HPC1_SCSI0_CBP, 149 .scsi0_ndbp = HPC1_SCSI0_NDBP, 150 .scsi0_bc = HPC1_SCSI0_BC, 151 .scsi0_ctl = HPC1_SCSI0_CTL, 152 .scsi0_gio = HPC1_SCSI0_GIO, 153 .scsi0_dev = HPC1_SCSI0_DEV, 154 .scsi0_dmacfg = HPC1_SCSI0_DMACFG, 155 .scsi0_piocfg = HPC1_SCSI0_PIOCFG, 156 .scsi1_regs = HPC1_SCSI1_REGS, 157 .scsi1_regs_size = HPC1_SCSI1_REGS_SIZE, 158 .scsi1_cbp = HPC1_SCSI1_CBP, 159 .scsi1_ndbp = HPC1_SCSI1_NDBP, 160 .scsi1_bc = HPC1_SCSI1_BC, 161 .scsi1_ctl = HPC1_SCSI1_CTL, 162 .scsi1_gio = HPC1_SCSI1_GIO, 163 .scsi1_dev = HPC1_SCSI1_DEV, 164 .scsi1_dmacfg = HPC1_SCSI1_DMACFG, 165 .scsi1_piocfg = HPC1_SCSI1_PIOCFG, 166 .dmactl_dir = HPC1_DMACTL_DIR, 167 .dmactl_flush = HPC1_DMACTL_FLUSH, 168 .dmactl_active = HPC1_DMACTL_ACTIVE, 169 .dmactl_reset = HPC1_DMACTL_RESET, 170 .enet_regs = HPC1_ENET_REGS, 171 .enet_regs_size = HPC1_ENET_REGS_SIZE, 172 .enet_intdelay = HPC1_ENET_INTDELAY, 173 .enet_intdelayval = HPC1_ENET_INTDELAYVAL, 174 .enetr_cbp = HPC1_ENETR_CBP, 175 .enetr_ndbp = HPC1_ENETR_NDBP, 176 .enetr_bc = HPC1_ENETR_BC, 177 .enetr_ctl = HPC1_ENETR_CTL, 178 .enetr_ctl_active = HPC1_ENETR_CTL_ACTIVE, 179 .enetr_reset = HPC1_ENETR_RESET, 180 .enetr_dmacfg = 0, 181 .enetr_piocfg = HPC1_ENETR_PIOCFG, 182 .enetx_cbp = HPC1_ENETX_CBP, 183 .enetx_ndbp = HPC1_ENETX_NDBP, 184 .enetx_bc = HPC1_ENETX_BC, 185 .enetx_ctl = HPC1_ENETX_CTL, 186 .enetx_ctl_active = HPC1_ENETX_CTL_ACTIVE, 187 .enetx_dev = HPC1_ENETX_DEV, 188 .enetr_fifo = HPC1_ENETR_FIFO, 189 .enetr_fifo_size = HPC1_ENETR_FIFO_SIZE, 190 .enetx_fifo = HPC1_ENETX_FIFO, 191 .enetx_fifo_size = HPC1_ENETX_FIFO_SIZE, 192 .scsi0_devregs_size = HPC1_SCSI0_DEVREGS_SIZE, 193 .scsi1_devregs_size = HPC1_SCSI0_DEVREGS_SIZE, 194 .enet_devregs = HPC1_ENET_DEVREGS, 195 .enet_devregs_size = HPC1_ENET_DEVREGS_SIZE, 196 .pbus_fifo = HPC1_PBUS_FIFO, 197 .pbus_fifo_size = HPC1_PBUS_FIFO_SIZE, 198 .pbus_bbram = HPC1_PBUS_BBRAM, 199 #define MAX_SCSI_XFER (512*1024) 200 .scsi_max_xfer = MAX_SCSI_XFER, 201 .scsi_dma_segs = (MAX_SCSI_XFER / 4096), 202 .scsi_dma_segs_size = 4096, 203 .clk_freq = 100, 204 .dma_datain_cmd = (HPC1_DMACTL_ACTIVE | HPC1_DMACTL_DIR), 205 .dma_dataout_cmd = HPC1_DMACTL_ACTIVE, 206 .scsi_dmactl_flush = HPC1_DMACTL_FLUSH, 207 .scsi_dmactl_active = HPC1_DMACTL_ACTIVE, 208 .scsi_dmactl_reset = HPC1_DMACTL_RESET 209 }; 210 211 static struct hpc_values hpc3_values = { 212 .revision 3, 213 .scsi0_regs = HPC_SCSI0_REGS, 214 .scsi0_regs_size = HPC_SCSI0_REGS_SIZE, 215 .scsi0_cbp = HPC_SCSI0_CBP, 216 .scsi0_ndbp = HPC_SCSI0_NDBP, 217 .scsi0_bc = HPC_SCSI0_BC, 218 .scsi0_ctl = HPC_SCSI0_CTL, 219 .scsi0_gio = HPC_SCSI0_GIO, 220 .scsi0_dev = HPC_SCSI0_DEV, 221 .scsi0_dmacfg = HPC_SCSI0_DMACFG, 222 .scsi0_piocfg = HPC_SCSI0_PIOCFG, 223 .scsi1_regs = HPC_SCSI1_REGS, 224 .scsi1_regs_size = HPC_SCSI1_REGS_SIZE, 225 .scsi1_cbp = HPC_SCSI1_CBP, 226 .scsi1_ndbp = HPC_SCSI1_NDBP, 227 .scsi1_bc = HPC_SCSI1_BC, 228 .scsi1_ctl = HPC_SCSI1_CTL, 229 .scsi1_gio = HPC_SCSI1_GIO, 230 .scsi1_dev = HPC_SCSI1_DEV, 231 .scsi1_dmacfg = HPC_SCSI1_DMACFG, 232 .scsi1_piocfg = HPC_SCSI1_PIOCFG, 233 .dmactl_dir = HPC_DMACTL_DIR, 234 .dmactl_flush = HPC_DMACTL_FLUSH, 235 .dmactl_active = HPC_DMACTL_ACTIVE, 236 .dmactl_reset = HPC_DMACTL_RESET, 237 .enet_regs = HPC_ENET_REGS, 238 .enet_regs_size = HPC_ENET_REGS_SIZE, 239 .enet_intdelay = 0, 240 .enet_intdelayval = 0, 241 .enetr_cbp = HPC_ENETR_CBP, 242 .enetr_ndbp = HPC_ENETR_NDBP, 243 .enetr_bc = HPC_ENETR_BC, 244 .enetr_ctl = HPC_ENETR_CTL, 245 .enetr_ctl_active = ENETR_CTL_ACTIVE, 246 .enetr_reset = HPC_ENETR_RESET, 247 .enetr_dmacfg = HPC_ENETR_DMACFG, 248 .enetr_piocfg = HPC_ENETR_PIOCFG, 249 .enetx_cbp = HPC_ENETX_CBP, 250 .enetx_ndbp = HPC_ENETX_NDBP, 251 .enetx_bc = HPC_ENETX_BC, 252 .enetx_ctl = HPC_ENETX_CTL, 253 .enetx_ctl_active = ENETX_CTL_ACTIVE, 254 .enetx_dev = HPC_ENETX_DEV, 255 .enetr_fifo = HPC_ENETR_FIFO, 256 .enetr_fifo_size = HPC_ENETR_FIFO_SIZE, 257 .enetx_fifo = HPC_ENETX_FIFO, 258 .enetx_fifo_size = HPC_ENETX_FIFO_SIZE, 259 .scsi0_devregs_size = HPC_SCSI0_DEVREGS_SIZE, 260 .scsi1_devregs_size = HPC_SCSI1_DEVREGS_SIZE, 261 .enet_devregs = HPC_ENET_DEVREGS, 262 .enet_devregs_size = HPC_ENET_DEVREGS_SIZE, 263 .pbus_fifo = HPC_PBUS_FIFO, 264 .pbus_fifo_size = HPC_PBUS_FIFO_SIZE, 265 .pbus_bbram = HPC_PBUS_BBRAM, 266 .scsi_max_xfer = MAX_SCSI_XFER, 267 .scsi_dma_segs = (MAX_SCSI_XFER / 8192), 268 .scsi_dma_segs_size = 8192, 269 .clk_freq = 100, 270 .dma_datain_cmd = HPC_DMACTL_ACTIVE, 271 .dma_dataout_cmd = (HPC_DMACTL_ACTIVE | HPC_DMACTL_DIR), 272 .scsi_dmactl_flush = HPC_DMACTL_FLUSH, 273 .scsi_dmactl_active = HPC_DMACTL_ACTIVE, 274 .scsi_dmactl_reset = HPC_DMACTL_RESET 275 }; 276 277 278 extern int mach_type; /* IPxx type */ 279 extern int mach_subtype; /* subtype: eg., Guiness/Fullhouse for IP22 */ 280 extern int mach_boardrev; /* machine board revision, in case it matters */ 281 282 extern struct sgimips_bus_dma_tag sgimips_default_bus_dma_tag; 283 284 static int powerintr_established; 285 286 int hpc_match(struct device *, struct cfdata *, void *); 287 void hpc_attach(struct device *, struct device *, void *); 288 int hpc_print(void *, const char *); 289 290 int hpc_submatch(struct device *, struct cfdata *, void *); 291 292 int hpc_power_intr(void *); 293 294 #if defined(BLINK) 295 static struct callout hpc_blink_ch = CALLOUT_INITIALIZER; 296 static void hpc_blink(void *); 297 #endif 298 299 CFATTACH_DECL(hpc, sizeof(struct hpc_softc), 300 hpc_match, hpc_attach, NULL, NULL); 301 302 int 303 hpc_match(struct device *parent, struct cfdata *cf, void *aux) 304 { 305 struct gio_attach_args* ga = aux; 306 307 /* Make sure it's actually there and readable */ 308 if (badaddr((void*)MIPS_PHYS_TO_KSEG1(ga->ga_addr), sizeof(u_int32_t))) 309 return 0; 310 311 return 1; 312 } 313 314 void 315 hpc_attach(struct device *parent, struct device *self, void *aux) 316 { 317 struct hpc_softc *sc = (struct hpc_softc *)self; 318 struct gio_attach_args* ga = aux; 319 struct hpc_attach_args ha; 320 const struct hpc_device *hd; 321 uint32_t hpctype; 322 int sysmask; 323 324 switch (mach_type) { 325 case MACH_SGI_IP12: 326 hpctype = 1; 327 sysmask = HPCDEV_IP12; 328 break; 329 330 case MACH_SGI_IP20: 331 hpctype = 15; 332 sysmask = HPCDEV_IP20; 333 break; 334 335 case MACH_SGI_IP22: 336 hpctype = 3; 337 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 338 sysmask = HPCDEV_IP22; 339 else 340 sysmask = HPCDEV_IP24; 341 break; 342 343 default: 344 panic("hpc_attach: can't handle HPC on an IP%d", mach_type); 345 }; 346 347 /* 348 * Verify HPC1 or HPC1.5 349 * 350 * For some reason the endian register isn't mapped on all 351 * machines (HPC1 machines?). 352 */ 353 if (hpctype != 3 && 354 !badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr+HPC1_BIGENDIAN),4)){ 355 hpctype = *(uint32_t *) 356 MIPS_PHYS_TO_KSEG1(ga->ga_addr + HPC1_BIGENDIAN); 357 358 if (((hpctype >> HPC1_REVSHIFT) & HPC1_REVMASK) == HPC1_REV15) 359 hpctype = 15; 360 else 361 hpctype = 1; 362 363 /* force big-endian mode */ 364 *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + HPC1_BIGENDIAN) 365 = hpctype & 0xe0; 366 } 367 368 printf(": SGI HPC%d%s\n", (hpctype == 3) ? 3 : 1, 369 (hpctype == 15) ? ".5" : ""); 370 371 sc->sc_ct = 1; 372 sc->sc_ch = ga->ga_ioh; 373 374 sc->sc_base = ga->ga_addr; 375 376 for (hd = hpc_devices; hd->hd_name != NULL; hd++) { 377 if (!(hd->hd_sysmask & sysmask)) 378 continue; 379 380 ha.ha_name = hd->hd_name; 381 ha.ha_devoff = hd->hd_devoff; 382 ha.ha_dmaoff = hd->hd_dmaoff; 383 ha.ha_irq = hd->hd_irq; 384 385 /* XXX This is disgusting. */ 386 ha.ha_st = 1; 387 ha.ha_sh = MIPS_PHYS_TO_KSEG1(sc->sc_base); 388 ha.ha_dmat = &sgimips_default_bus_dma_tag; 389 if (hpctype == 3) 390 ha.hpc_regs = &hpc3_values; 391 else 392 ha.hpc_regs = &hpc1_values; 393 ha.hpc_regs->revision = hpctype; 394 395 (void) config_found_sm(self, &ha, hpc_print, hpc_submatch); 396 } 397 398 /* 399 * XXX: Only attach the powerfail interrupt once, since the 400 * interrupt code doesn't let you share interrupt just yet. 401 * 402 * Since the powerfail interrupt is hardcoded to read from 403 * a specific register anyway (XXX#2!), we don't care when 404 * it gets attached, as long as it only happens once. 405 */ 406 if (mach_type == MACH_SGI_IP22 && !powerintr_established) { 407 cpu_intr_establish(9, IPL_NONE, hpc_power_intr, sc); 408 powerintr_established++; 409 } 410 411 #if defined(BLINK) 412 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) 413 hpc_blink(sc); 414 #endif 415 } 416 417 int 418 hpc_submatch(struct device *parent, struct cfdata *cf, void *aux) 419 { 420 struct hpc_attach_args *ha = aux; 421 422 if (cf->cf_loc[HPCCF_OFFSET] != HPCCF_OFFSET_DEFAULT && 423 (bus_addr_t) cf->cf_loc[HPCCF_OFFSET] != ha->ha_devoff) 424 return (0); 425 426 return (config_match(parent, cf, aux)); 427 } 428 429 int 430 hpc_print(void *aux, const char *pnp) 431 { 432 struct hpc_attach_args *ha = aux; 433 434 if (pnp) 435 printf("%s at %s", ha->ha_name, pnp); 436 437 printf(" offset 0x%lx", ha->ha_devoff); 438 439 return (UNCONF); 440 } 441 442 int 443 hpc_power_intr(void *arg) 444 { 445 u_int32_t pwr_reg; 446 447 pwr_reg = *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)); 448 *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)) = pwr_reg; 449 450 printf("hpc_power_intr: panel reg = %08x\n", pwr_reg); 451 452 if (pwr_reg & 2) 453 cpu_reboot(RB_HALT, NULL); 454 455 return 1; 456 } 457 458 #if defined(BLINK) 459 static void 460 hpc_blink(void *self) 461 { 462 struct hpc_softc *sc = (struct hpc_softc *) self; 463 register int s; 464 int value; 465 466 s = splhigh(); 467 468 value = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(HPC1_AUX_REGS); 469 value ^= HPC1_AUX_CONSLED; 470 *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(HPC1_AUX_REGS) = value; 471 splx(s); 472 473 /* 474 * Blink rate is: 475 * full cycle every second if completely idle (loadav = 0) 476 * full cycle every 2 seconds if loadav = 1 477 * full cycle every 3 seconds if loadav = 2 478 * etc. 479 */ 480 s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); 481 callout_reset(&hpc_blink_ch, s, hpc_blink, sc); 482 } 483 #endif 484 485
Indexes created Mon Sep 22 10:09:38 GMT 2025