hpc.c revision 1.31
1 /* $NetBSD: hpc.c,v 1.31 2004/12/30 23:18:09 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang 5 * Copyright (c) 2001 Rafal K. Boni 6 * Copyright (c) 2001 Jason R. Thorpe 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.31 2004/12/30 23:18:09 rumble Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/reboot.h> 45 #include <sys/callout.h> 46 47 #include <machine/machtype.h> 48 49 #include <sgimips/gio/gioreg.h> 50 #include <sgimips/gio/giovar.h> 51 52 #include <sgimips/hpc/hpcvar.h> 53 #include <sgimips/hpc/hpcreg.h> 54 #include <sgimips/ioc/iocreg.h> 55 56 #include "locators.h" 57 58 #define HPC_REVISION_MASK 0x3 59 #define HPC_REVISION_1 0x1 60 #define HPC_REVISION_15 0x2 61 #define HPC_REVISION_3 0x3 62 63 const struct hpc_device { 64 const char *hd_name; 65 bus_addr_t hd_base; 66 bus_addr_t hd_devoff; 67 bus_addr_t hd_dmaoff; 68 int hd_irq; 69 int hd_sysmask; 70 } hpc_devices[] = { 71 { "zsc", 72 HPC_BASE_ADDRESS_0, 73 /* XXX Magic numbers */ 74 HPC3_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0, 75 29, 76 HPCDEV_IP22 | HPCDEV_IP24 }, 77 78 /* probe order is important for IP20 zsc */ 79 80 { "zsc", /* serial 0/1 duart 1 */ 81 HPC_BASE_ADDRESS_0, 82 0x0d10, 0, 83 5, 84 HPCDEV_IP12 | HPCDEV_IP20 }, 85 86 { "zsc", /* kbd/ms duart 0 */ 87 HPC_BASE_ADDRESS_0, 88 0x0d00, 0, 89 5, 90 HPCDEV_IP12 | HPCDEV_IP20 }, 91 92 { "pckbc", 93 HPC_BASE_ADDRESS_0, 94 HPC3_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0, 95 28, 96 HPCDEV_IP22 | HPCDEV_IP24 }, 97 98 { "sq", 99 HPC_BASE_ADDRESS_0, 100 HPC3_ENET_DEVREGS, HPC3_ENET_REGS, 101 3, 102 HPCDEV_IP22 | HPCDEV_IP24 }, 103 104 { "sq", 105 HPC_BASE_ADDRESS_0, 106 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 107 3, 108 HPCDEV_IP12 | HPCDEV_IP20 }, 109 110 { "sq", 111 HPC_BASE_ADDRESS_1, 112 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 113 6, 114 HPCDEV_IP12 | HPCDEV_IP20 }, 115 116 { "sq", 117 HPC_BASE_ADDRESS_1, 118 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 119 22, 120 HPCDEV_IP24 }, 121 122 { "sq", 123 HPC_BASE_ADDRESS_2, 124 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 125 15, 126 HPCDEV_IP12 | HPCDEV_IP20 }, 127 128 { "sq", 129 HPC_BASE_ADDRESS_2, 130 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 131 23, 132 HPCDEV_IP24 }, 133 134 { "wdsc", 135 HPC_BASE_ADDRESS_0, 136 HPC3_SCSI0_DEVREGS, HPC3_SCSI0_REGS, 137 1, /* XXX 1 = IRQ_LOCAL0 + 1 */ 138 HPCDEV_IP22 | HPCDEV_IP24 }, 139 140 { "wdsc", 141 HPC_BASE_ADDRESS_0, 142 HPC3_SCSI1_DEVREGS, HPC3_SCSI1_REGS, 143 2, /* XXX 2 = IRQ_LOCAL0 + 2 */ 144 HPCDEV_IP22 }, 145 146 { "wdsc", 147 HPC_BASE_ADDRESS_0, 148 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 149 2, /* XXX 1 = IRQ_LOCAL0 + 2 */ 150 HPCDEV_IP12 | HPCDEV_IP20 }, 151 152 { "dpclock", 153 HPC_BASE_ADDRESS_0, 154 HPC1_PBUS_BBRAM, 0, 155 -1, 156 HPCDEV_IP12 | HPCDEV_IP20 }, 157 158 { "dsclock", 159 HPC_BASE_ADDRESS_0, 160 HPC3_PBUS_BBRAM, 0, 161 -1, 162 HPCDEV_IP22 | HPCDEV_IP24 }, 163 164 { "haltwo", 165 HPC_BASE_ADDRESS_0, 166 HPC3_PBUS_CH0_DEVREGS, HPC3_PBUS_DMAREGS, 167 8 + 4, /* XXX IRQ_LOCAL1 + 4 */ 168 HPCDEV_IP22 | HPCDEV_IP24 }, 169 170 { NULL, 171 0, 172 0, 0, 173 0, 174 0 175 } 176 }; 177 178 struct hpc_softc { 179 struct device sc_dev; 180 181 bus_addr_t sc_base; 182 183 bus_space_tag_t sc_ct; 184 bus_space_handle_t sc_ch; 185 }; 186 187 static struct hpc_values hpc1_values = { 188 .revision = 1, 189 .scsi0_regs = HPC1_SCSI0_REGS, 190 .scsi0_regs_size = HPC1_SCSI0_REGS_SIZE, 191 .scsi0_cbp = HPC1_SCSI0_CBP, 192 .scsi0_ndbp = HPC1_SCSI0_NDBP, 193 .scsi0_bc = HPC1_SCSI0_BC, 194 .scsi0_ctl = HPC1_SCSI0_CTL, 195 .scsi0_gio = HPC1_SCSI0_GIO, 196 .scsi0_dev = HPC1_SCSI0_DEV, 197 .scsi0_dmacfg = HPC1_SCSI0_DMACFG, 198 .scsi0_piocfg = HPC1_SCSI0_PIOCFG, 199 .scsi1_regs = HPC1_SCSI1_REGS, 200 .scsi1_regs_size = HPC1_SCSI1_REGS_SIZE, 201 .scsi1_cbp = HPC1_SCSI1_CBP, 202 .scsi1_ndbp = HPC1_SCSI1_NDBP, 203 .scsi1_bc = HPC1_SCSI1_BC, 204 .scsi1_ctl = HPC1_SCSI1_CTL, 205 .scsi1_gio = HPC1_SCSI1_GIO, 206 .scsi1_dev = HPC1_SCSI1_DEV, 207 .scsi1_dmacfg = HPC1_SCSI1_DMACFG, 208 .scsi1_piocfg = HPC1_SCSI1_PIOCFG, 209 .dmactl_dir = HPC1_DMACTL_DIR, 210 .dmactl_flush = HPC1_DMACTL_FLUSH, 211 .dmactl_active = HPC1_DMACTL_ACTIVE, 212 .dmactl_reset = HPC1_DMACTL_RESET, 213 .enet_regs = HPC1_ENET_REGS, 214 .enet_regs_size = HPC1_ENET_REGS_SIZE, 215 .enet_intdelay = HPC1_ENET_INTDELAY, 216 .enet_intdelayval = HPC1_ENET_INTDELAY_OFF, 217 .enetr_cbp = HPC1_ENETR_CBP, 218 .enetr_ndbp = HPC1_ENETR_NDBP, 219 .enetr_bc = HPC1_ENETR_BC, 220 .enetr_ctl = HPC1_ENETR_CTL, 221 .enetr_ctl_active = HPC1_ENETR_CTL_ACTIVE, 222 .enetr_reset = HPC1_ENETR_RESET, 223 .enetr_dmacfg = 0, 224 .enetr_piocfg = 0, 225 .enetx_cbp = HPC1_ENETX_CBP, 226 .enetx_ndbp = HPC1_ENETX_NDBP, 227 .enetx_bc = HPC1_ENETX_BC, 228 .enetx_ctl = HPC1_ENETX_CTL, 229 .enetx_ctl_active = HPC1_ENETX_CTL_ACTIVE, 230 .enetx_dev = 0, 231 .enetr_fifo = HPC1_ENETR_FIFO, 232 .enetr_fifo_size = HPC1_ENETR_FIFO_SIZE, 233 .enetx_fifo = HPC1_ENETX_FIFO, 234 .enetx_fifo_size = HPC1_ENETX_FIFO_SIZE, 235 .scsi0_devregs_size = HPC1_SCSI0_DEVREGS_SIZE, 236 .scsi1_devregs_size = HPC1_SCSI0_DEVREGS_SIZE, 237 .enet_devregs = HPC1_ENET_DEVREGS, 238 .enet_devregs_size = HPC1_ENET_DEVREGS_SIZE, 239 .pbus_fifo = 0, 240 .pbus_fifo_size = 0, 241 .pbus_bbram = 0, 242 #define MAX_SCSI_XFER (512*1024) 243 .scsi_max_xfer = MAX_SCSI_XFER, 244 .scsi_dma_segs = (MAX_SCSI_XFER / 4096), 245 .scsi_dma_segs_size = 4096, 246 .clk_freq = 100, 247 .dma_datain_cmd = (HPC1_DMACTL_ACTIVE | HPC1_DMACTL_DIR), 248 .dma_dataout_cmd = HPC1_DMACTL_ACTIVE, 249 .scsi_dmactl_flush = HPC1_DMACTL_FLUSH, 250 .scsi_dmactl_active = HPC1_DMACTL_ACTIVE, 251 .scsi_dmactl_reset = HPC1_DMACTL_RESET 252 }; 253 254 static struct hpc_values hpc3_values = { 255 .revision 3, 256 .scsi0_regs = HPC3_SCSI0_REGS, 257 .scsi0_regs_size = HPC3_SCSI0_REGS_SIZE, 258 .scsi0_cbp = HPC3_SCSI0_CBP, 259 .scsi0_ndbp = HPC3_SCSI0_NDBP, 260 .scsi0_bc = HPC3_SCSI0_BC, 261 .scsi0_ctl = HPC3_SCSI0_CTL, 262 .scsi0_gio = HPC3_SCSI0_GIO, 263 .scsi0_dev = HPC3_SCSI0_DEV, 264 .scsi0_dmacfg = HPC3_SCSI0_DMACFG, 265 .scsi0_piocfg = HPC3_SCSI0_PIOCFG, 266 .scsi1_regs = HPC3_SCSI1_REGS, 267 .scsi1_regs_size = HPC3_SCSI1_REGS_SIZE, 268 .scsi1_cbp = HPC3_SCSI1_CBP, 269 .scsi1_ndbp = HPC3_SCSI1_NDBP, 270 .scsi1_bc = HPC3_SCSI1_BC, 271 .scsi1_ctl = HPC3_SCSI1_CTL, 272 .scsi1_gio = HPC3_SCSI1_GIO, 273 .scsi1_dev = HPC3_SCSI1_DEV, 274 .scsi1_dmacfg = HPC3_SCSI1_DMACFG, 275 .scsi1_piocfg = HPC3_SCSI1_PIOCFG, 276 .dmactl_dir = HPC3_DMACTL_DIR, 277 .dmactl_flush = HPC3_DMACTL_FLUSH, 278 .dmactl_active = HPC3_DMACTL_ACTIVE, 279 .dmactl_reset = HPC3_DMACTL_RESET, 280 .enet_regs = HPC3_ENET_REGS, 281 .enet_regs_size = HPC3_ENET_REGS_SIZE, 282 .enet_intdelay = 0, 283 .enet_intdelayval = 0, 284 .enetr_cbp = HPC3_ENETR_CBP, 285 .enetr_ndbp = HPC3_ENETR_NDBP, 286 .enetr_bc = HPC3_ENETR_BC, 287 .enetr_ctl = HPC3_ENETR_CTL, 288 .enetr_ctl_active = HPC3_ENETR_CTL_ACTIVE, 289 .enetr_reset = HPC3_ENETR_RESET, 290 .enetr_dmacfg = HPC3_ENETR_DMACFG, 291 .enetr_piocfg = HPC3_ENETR_PIOCFG, 292 .enetx_cbp = HPC3_ENETX_CBP, 293 .enetx_ndbp = HPC3_ENETX_NDBP, 294 .enetx_bc = HPC3_ENETX_BC, 295 .enetx_ctl = HPC3_ENETX_CTL, 296 .enetx_ctl_active = HPC3_ENETX_CTL_ACTIVE, 297 .enetx_dev = HPC3_ENETX_DEV, 298 .enetr_fifo = HPC3_ENETR_FIFO, 299 .enetr_fifo_size = HPC3_ENETR_FIFO_SIZE, 300 .enetx_fifo = HPC3_ENETX_FIFO, 301 .enetx_fifo_size = HPC3_ENETX_FIFO_SIZE, 302 .scsi0_devregs_size = HPC3_SCSI0_DEVREGS_SIZE, 303 .scsi1_devregs_size = HPC3_SCSI1_DEVREGS_SIZE, 304 .enet_devregs = HPC3_ENET_DEVREGS, 305 .enet_devregs_size = HPC3_ENET_DEVREGS_SIZE, 306 .pbus_fifo = HPC3_PBUS_FIFO, 307 .pbus_fifo_size = HPC3_PBUS_FIFO_SIZE, 308 .pbus_bbram = HPC3_PBUS_BBRAM, 309 .scsi_max_xfer = MAX_SCSI_XFER, 310 .scsi_dma_segs = (MAX_SCSI_XFER / 8192), 311 .scsi_dma_segs_size = 8192, 312 .clk_freq = 100, 313 .dma_datain_cmd = HPC3_DMACTL_ACTIVE, 314 .dma_dataout_cmd = (HPC3_DMACTL_ACTIVE | HPC3_DMACTL_DIR), 315 .scsi_dmactl_flush = HPC3_DMACTL_FLUSH, 316 .scsi_dmactl_active = HPC3_DMACTL_ACTIVE, 317 .scsi_dmactl_reset = HPC3_DMACTL_RESET 318 }; 319 320 321 extern int mach_type; /* IPxx type */ 322 extern int mach_subtype; /* subtype: eg., Guiness/Fullhouse for IP22 */ 323 extern int mach_boardrev; /* machine board revision, in case it matters */ 324 325 extern struct sgimips_bus_dma_tag sgimips_default_bus_dma_tag; 326 327 static int powerintr_established; 328 329 int hpc_match(struct device *, struct cfdata *, void *); 330 void hpc_attach(struct device *, struct device *, void *); 331 int hpc_print(void *, const char *); 332 333 int hpc_revision(struct hpc_softc *, struct gio_attach_args *); 334 335 int hpc_submatch(struct device *, struct cfdata *, void *); 336 337 int hpc_power_intr(void *); 338 339 #if defined(BLINK) 340 static struct callout hpc_blink_ch = CALLOUT_INITIALIZER; 341 static void hpc_blink(void *); 342 #endif 343 344 CFATTACH_DECL(hpc, sizeof(struct hpc_softc), 345 hpc_match, hpc_attach, NULL, NULL); 346 347 int 348 hpc_match(struct device *parent, struct cfdata *cf, void *aux) 349 { 350 struct gio_attach_args* ga = aux; 351 352 /* Make sure it's actually there and readable */ 353 if (badaddr((void*)MIPS_PHYS_TO_KSEG1(ga->ga_addr), sizeof(u_int32_t))) 354 return 0; 355 356 return 1; 357 } 358 359 void 360 hpc_attach(struct device *parent, struct device *self, void *aux) 361 { 362 struct hpc_softc *sc = (struct hpc_softc *)self; 363 struct gio_attach_args* ga = aux; 364 struct hpc_attach_args ha; 365 const struct hpc_device *hd; 366 uint32_t hpctype; 367 int sysmask; 368 369 switch (mach_type) { 370 case MACH_SGI_IP12: 371 sysmask = HPCDEV_IP12; 372 break; 373 374 case MACH_SGI_IP20: 375 sysmask = HPCDEV_IP20; 376 break; 377 378 case MACH_SGI_IP22: 379 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 380 sysmask = HPCDEV_IP22; 381 else 382 sysmask = HPCDEV_IP24; 383 break; 384 385 default: 386 panic("hpc_attach: can't handle HPC on an IP%d", mach_type); 387 }; 388 389 if ((hpctype = hpc_revision(sc, ga)) == 0) 390 panic("hpc_attach: could not identify HPC revision\n"); 391 392 /* force big-endian mode */ 393 if (hpctype == 15) 394 *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr+HPC1_BIGENDIAN) = 0; 395 396 printf(": SGI HPC%d%s\n", (hpctype == 3) ? 3 : 1, 397 (hpctype == 15) ? ".5" : ""); 398 399 sc->sc_ct = 1; 400 sc->sc_ch = ga->ga_ioh; 401 402 sc->sc_base = ga->ga_addr; 403 404 for (hd = hpc_devices; hd->hd_name != NULL; hd++) { 405 if (!(hd->hd_sysmask & sysmask) || hd->hd_base != sc->sc_base) 406 continue; 407 408 ha.ha_name = hd->hd_name; 409 ha.ha_devoff = hd->hd_devoff; 410 ha.ha_dmaoff = hd->hd_dmaoff; 411 ha.ha_irq = hd->hd_irq; 412 413 /* XXX This is disgusting. */ 414 ha.ha_st = 1; 415 ha.ha_sh = MIPS_PHYS_TO_KSEG1(sc->sc_base); 416 ha.ha_dmat = &sgimips_default_bus_dma_tag; 417 if (hpctype == 3) 418 ha.hpc_regs = &hpc3_values; 419 else 420 ha.hpc_regs = &hpc1_values; 421 ha.hpc_regs->revision = hpctype; 422 423 (void) config_found_sm(self, &ha, hpc_print, hpc_submatch); 424 } 425 426 /* 427 * XXX: Only attach the powerfail interrupt once, since the 428 * interrupt code doesn't let you share interrupt just yet. 429 * 430 * Since the powerfail interrupt is hardcoded to read from 431 * a specific register anyway (XXX#2!), we don't care when 432 * it gets attached, as long as it only happens once. 433 */ 434 if (mach_type == MACH_SGI_IP22 && !powerintr_established) { 435 cpu_intr_establish(9, IPL_NONE, hpc_power_intr, sc); 436 powerintr_established++; 437 } 438 439 #if defined(BLINK) 440 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) 441 hpc_blink(sc); 442 #endif 443 } 444 445 int 446 hpc_revision(struct hpc_softc *sc, struct gio_attach_args *ga) 447 { 448 int hpctype; 449 450 /* Allow forcing of our hpc revision. */ 451 switch (sc->sc_dev.dv_cfdata->cf_flags & HPC_REVISION_MASK) { 452 case HPC_REVISION_1: 453 return (1); 454 455 case HPC_REVISION_15: 456 return (15); 457 458 case HPC_REVISION_3: 459 return (3); 460 } 461 462 /* XXX We should really come up with an autodetect mechanism */ 463 switch (mach_type) { 464 case MACH_SGI_IP12: 465 hpctype = 1; 466 break; 467 468 case MACH_SGI_IP20: 469 hpctype = 15; 470 break; 471 472 case MACH_SGI_IP22: 473 hpctype = 3; 474 break; 475 476 default: 477 return (0); 478 } 479 480 /* 481 * Verify HPC1 or HPC1.5 482 * 483 * For some reason the endian register isn't mapped on all 484 * machines (HPC1 machines?). 485 */ 486 if (hpctype == 1 || hpctype == 15) { 487 u_int32_t reg; 488 489 if (!badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 490 HPC1_BIGENDIAN), 4)) { 491 reg = *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 492 HPC1_BIGENDIAN); 493 494 if (((reg >> HPC1_REVSHIFT) & HPC1_REVMASK) == 495 HPC1_REV15) 496 hpctype = 15; 497 else 498 hpctype = 1; 499 } else 500 hpctype = 1; 501 } 502 503 return (hpctype); 504 } 505 506 int 507 hpc_submatch(struct device *parent, struct cfdata *cf, void *aux) 508 { 509 struct hpc_attach_args *ha = aux; 510 511 if (cf->cf_loc[HPCCF_OFFSET] != HPCCF_OFFSET_DEFAULT && 512 (bus_addr_t) cf->cf_loc[HPCCF_OFFSET] != ha->ha_devoff) 513 return (0); 514 515 return (config_match(parent, cf, aux)); 516 } 517 518 int 519 hpc_print(void *aux, const char *pnp) 520 { 521 struct hpc_attach_args *ha = aux; 522 523 if (pnp) 524 printf("%s at %s", ha->ha_name, pnp); 525 526 printf(" offset 0x%lx", ha->ha_devoff); 527 528 return (UNCONF); 529 } 530 531 int 532 hpc_power_intr(void *arg) 533 { 534 u_int32_t pwr_reg; 535 536 pwr_reg = *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)); 537 *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)) = pwr_reg; 538 539 printf("hpc_power_intr: panel reg = %08x\n", pwr_reg); 540 541 if (pwr_reg & 2) 542 cpu_reboot(RB_HALT, NULL); 543 544 return 1; 545 } 546 547 #if defined(BLINK) 548 static void 549 hpc_blink(void *self) 550 { 551 struct hpc_softc *sc = (struct hpc_softc *) self; 552 register int s; 553 int value; 554 555 s = splhigh(); 556 557 value = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(HPC1_AUX_REGS); 558 value ^= HPC1_AUX_CONSLED; 559 *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(HPC1_AUX_REGS) = value; 560 splx(s); 561 562 /* 563 * Blink rate is: 564 * full cycle every second if completely idle (loadav = 0) 565 * full cycle every 2 seconds if loadav = 1 566 * full cycle every 3 seconds if loadav = 2 567 * etc. 568 */ 569 s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); 570 callout_reset(&hpc_blink_ch, s, hpc_blink, sc); 571 } 572 #endif 573 574
Indexes created Mon Sep 22 21:09:42 GMT 2025