hpc.c revision 1.41
1 /* $NetBSD: hpc.c,v 1.41 2006/12/22 05:26:01 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang 5 * Copyright (c) 2001 Rafal K. Boni 6 * Copyright (c) 2001 Jason R. Thorpe 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.41 2006/12/22 05:26:01 rumble Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/reboot.h> 45 #include <sys/callout.h> 46 47 #define _SGIMIPS_BUS_DMA_PRIVATE 48 #include <machine/bus.h> 49 #include <machine/machtype.h> 50 51 #include <sgimips/gio/gioreg.h> 52 #include <sgimips/gio/giovar.h> 53 54 #include <sgimips/hpc/hpcvar.h> 55 #include <sgimips/hpc/hpcreg.h> 56 #include <sgimips/ioc/iocreg.h> 57 58 #include "locators.h" 59 60 static const struct hpc_device { 61 const char *hd_name; 62 bus_addr_t hd_base; 63 bus_addr_t hd_devoff; 64 bus_addr_t hd_dmaoff; 65 int hd_irq; 66 int hd_sysmask; 67 } hpc_devices[] = { 68 { "zsc", 69 HPC_BASE_ADDRESS_0, 70 /* XXX Magic numbers */ 71 HPC3_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0, 72 29, 73 HPCDEV_IP22 | HPCDEV_IP24 }, 74 75 /* probe order is important for IP20 zsc */ 76 77 { "zsc", /* serial 0/1 duart 1 */ 78 HPC_BASE_ADDRESS_0, 79 0x0d10, 0, 80 5, 81 HPCDEV_IP12 | HPCDEV_IP20 }, 82 83 { "zsc", /* kbd/ms duart 0 */ 84 HPC_BASE_ADDRESS_0, 85 0x0d00, 0, 86 5, 87 HPCDEV_IP12 | HPCDEV_IP20 }, 88 89 { "pckbc", 90 HPC_BASE_ADDRESS_0, 91 HPC3_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0, 92 28, 93 HPCDEV_IP22 | HPCDEV_IP24 }, 94 95 { "sq", 96 HPC_BASE_ADDRESS_0, 97 HPC3_ENET_DEVREGS, HPC3_ENET_REGS, 98 3, 99 HPCDEV_IP22 | HPCDEV_IP24 }, 100 101 { "sq", 102 HPC_BASE_ADDRESS_0, 103 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 104 3, 105 HPCDEV_IP12 | HPCDEV_IP20 }, 106 107 { "sq", 108 HPC_BASE_ADDRESS_1, 109 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 110 6, 111 HPCDEV_IP12 | HPCDEV_IP20 }, 112 113 { "sq", 114 HPC_BASE_ADDRESS_1, 115 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 116 22, 117 HPCDEV_IP24 }, 118 119 { "sq", 120 HPC_BASE_ADDRESS_2, 121 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 122 15, 123 HPCDEV_IP12 | HPCDEV_IP20 }, 124 125 { "sq", 126 HPC_BASE_ADDRESS_2, 127 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 128 23, 129 HPCDEV_IP24 }, 130 131 { "wdsc", 132 HPC_BASE_ADDRESS_0, 133 HPC3_SCSI0_DEVREGS, HPC3_SCSI0_REGS, 134 1, /* XXX 1 = IRQ_LOCAL0 + 1 */ 135 HPCDEV_IP22 | HPCDEV_IP24 }, 136 137 { "wdsc", 138 HPC_BASE_ADDRESS_0, 139 HPC3_SCSI1_DEVREGS, HPC3_SCSI1_REGS, 140 2, /* XXX 2 = IRQ_LOCAL0 + 2 */ 141 HPCDEV_IP22 }, 142 143 { "wdsc", 144 HPC_BASE_ADDRESS_0, 145 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 146 2, /* XXX 1 = IRQ_LOCAL0 + 2 */ 147 HPCDEV_IP12 | HPCDEV_IP20 }, 148 149 { "dpclock", 150 HPC_BASE_ADDRESS_0, 151 HPC1_PBUS_BBRAM, 0, 152 -1, 153 HPCDEV_IP12 | HPCDEV_IP20 }, 154 155 { "dsclock", 156 HPC_BASE_ADDRESS_0, 157 HPC3_PBUS_BBRAM, 0, 158 -1, 159 HPCDEV_IP22 | HPCDEV_IP24 }, 160 161 { "haltwo", 162 HPC_BASE_ADDRESS_0, 163 HPC3_PBUS_CH0_DEVREGS, HPC3_PBUS_DMAREGS, 164 8 + 4, /* XXX IRQ_LOCAL1 + 4 */ 165 HPCDEV_IP22 | HPCDEV_IP24 }, 166 167 { "pi1ppc", 168 HPC_BASE_ADDRESS_0, 169 HPC3_PBUS_CH6_DEVREGS + IOC_PLP_REGS, 0, 170 -1, 171 HPCDEV_IP22 | HPCDEV_IP24 }, 172 173 { NULL, 174 0, 175 0, 0, 176 0, 177 0 178 } 179 }; 180 181 struct hpc_softc { 182 struct device sc_dev; 183 184 bus_addr_t sc_base; 185 186 bus_space_tag_t sc_ct; 187 bus_space_handle_t sc_ch; 188 }; 189 190 static struct hpc_values hpc1_values = { 191 .revision = 1, 192 .scsi0_regs = HPC1_SCSI0_REGS, 193 .scsi0_regs_size = HPC1_SCSI0_REGS_SIZE, 194 .scsi0_cbp = HPC1_SCSI0_CBP, 195 .scsi0_ndbp = HPC1_SCSI0_NDBP, 196 .scsi0_bc = HPC1_SCSI0_BC, 197 .scsi0_ctl = HPC1_SCSI0_CTL, 198 .scsi0_gio = HPC1_SCSI0_GIO, 199 .scsi0_dev = HPC1_SCSI0_DEV, 200 .scsi0_dmacfg = HPC1_SCSI0_DMACFG, 201 .scsi0_piocfg = HPC1_SCSI0_PIOCFG, 202 .scsi1_regs = HPC1_SCSI1_REGS, 203 .scsi1_regs_size = HPC1_SCSI1_REGS_SIZE, 204 .scsi1_cbp = HPC1_SCSI1_CBP, 205 .scsi1_ndbp = HPC1_SCSI1_NDBP, 206 .scsi1_bc = HPC1_SCSI1_BC, 207 .scsi1_ctl = HPC1_SCSI1_CTL, 208 .scsi1_gio = HPC1_SCSI1_GIO, 209 .scsi1_dev = HPC1_SCSI1_DEV, 210 .scsi1_dmacfg = HPC1_SCSI1_DMACFG, 211 .scsi1_piocfg = HPC1_SCSI1_PIOCFG, 212 .dmactl_dir = HPC1_DMACTL_DIR, 213 .dmactl_flush = HPC1_DMACTL_FLUSH, 214 .dmactl_active = HPC1_DMACTL_ACTIVE, 215 .dmactl_reset = HPC1_DMACTL_RESET, 216 .enet_regs = HPC1_ENET_REGS, 217 .enet_regs_size = HPC1_ENET_REGS_SIZE, 218 .enet_intdelay = HPC1_ENET_INTDELAY, 219 .enet_intdelayval = HPC1_ENET_INTDELAY_OFF, 220 .enetr_cbp = HPC1_ENETR_CBP, 221 .enetr_ndbp = HPC1_ENETR_NDBP, 222 .enetr_bc = HPC1_ENETR_BC, 223 .enetr_ctl = HPC1_ENETR_CTL, 224 .enetr_ctl_active = HPC1_ENETR_CTL_ACTIVE, 225 .enetr_reset = HPC1_ENETR_RESET, 226 .enetr_dmacfg = 0, 227 .enetr_piocfg = 0, 228 .enetx_cbp = HPC1_ENETX_CBP, 229 .enetx_ndbp = HPC1_ENETX_NDBP, 230 .enetx_bc = HPC1_ENETX_BC, 231 .enetx_ctl = HPC1_ENETX_CTL, 232 .enetx_ctl_active = HPC1_ENETX_CTL_ACTIVE, 233 .enetx_dev = 0, 234 .enetr_fifo = HPC1_ENETR_FIFO, 235 .enetr_fifo_size = HPC1_ENETR_FIFO_SIZE, 236 .enetx_fifo = HPC1_ENETX_FIFO, 237 .enetx_fifo_size = HPC1_ENETX_FIFO_SIZE, 238 .scsi0_devregs_size = HPC1_SCSI0_DEVREGS_SIZE, 239 .scsi1_devregs_size = HPC1_SCSI0_DEVREGS_SIZE, 240 .enet_devregs = HPC1_ENET_DEVREGS, 241 .enet_devregs_size = HPC1_ENET_DEVREGS_SIZE, 242 .pbus_fifo = 0, 243 .pbus_fifo_size = 0, 244 .pbus_bbram = 0, 245 #define MAX_SCSI_XFER (512*1024) 246 .scsi_max_xfer = MAX_SCSI_XFER, 247 .scsi_dma_segs = (MAX_SCSI_XFER / 4096), 248 .scsi_dma_segs_size = 4096, 249 .clk_freq = 100, 250 .dma_datain_cmd = (HPC1_DMACTL_ACTIVE | HPC1_DMACTL_DIR), 251 .dma_dataout_cmd = HPC1_DMACTL_ACTIVE, 252 .scsi_dmactl_flush = HPC1_DMACTL_FLUSH, 253 .scsi_dmactl_active = HPC1_DMACTL_ACTIVE, 254 .scsi_dmactl_reset = HPC1_DMACTL_RESET 255 }; 256 257 static struct hpc_values hpc3_values = { 258 .revision = 3, 259 .scsi0_regs = HPC3_SCSI0_REGS, 260 .scsi0_regs_size = HPC3_SCSI0_REGS_SIZE, 261 .scsi0_cbp = HPC3_SCSI0_CBP, 262 .scsi0_ndbp = HPC3_SCSI0_NDBP, 263 .scsi0_bc = HPC3_SCSI0_BC, 264 .scsi0_ctl = HPC3_SCSI0_CTL, 265 .scsi0_gio = HPC3_SCSI0_GIO, 266 .scsi0_dev = HPC3_SCSI0_DEV, 267 .scsi0_dmacfg = HPC3_SCSI0_DMACFG, 268 .scsi0_piocfg = HPC3_SCSI0_PIOCFG, 269 .scsi1_regs = HPC3_SCSI1_REGS, 270 .scsi1_regs_size = HPC3_SCSI1_REGS_SIZE, 271 .scsi1_cbp = HPC3_SCSI1_CBP, 272 .scsi1_ndbp = HPC3_SCSI1_NDBP, 273 .scsi1_bc = HPC3_SCSI1_BC, 274 .scsi1_ctl = HPC3_SCSI1_CTL, 275 .scsi1_gio = HPC3_SCSI1_GIO, 276 .scsi1_dev = HPC3_SCSI1_DEV, 277 .scsi1_dmacfg = HPC3_SCSI1_DMACFG, 278 .scsi1_piocfg = HPC3_SCSI1_PIOCFG, 279 .dmactl_dir = HPC3_DMACTL_DIR, 280 .dmactl_flush = HPC3_DMACTL_FLUSH, 281 .dmactl_active = HPC3_DMACTL_ACTIVE, 282 .dmactl_reset = HPC3_DMACTL_RESET, 283 .enet_regs = HPC3_ENET_REGS, 284 .enet_regs_size = HPC3_ENET_REGS_SIZE, 285 .enet_intdelay = 0, 286 .enet_intdelayval = 0, 287 .enetr_cbp = HPC3_ENETR_CBP, 288 .enetr_ndbp = HPC3_ENETR_NDBP, 289 .enetr_bc = HPC3_ENETR_BC, 290 .enetr_ctl = HPC3_ENETR_CTL, 291 .enetr_ctl_active = HPC3_ENETR_CTL_ACTIVE, 292 .enetr_reset = HPC3_ENETR_RESET, 293 .enetr_dmacfg = HPC3_ENETR_DMACFG, 294 .enetr_piocfg = HPC3_ENETR_PIOCFG, 295 .enetx_cbp = HPC3_ENETX_CBP, 296 .enetx_ndbp = HPC3_ENETX_NDBP, 297 .enetx_bc = HPC3_ENETX_BC, 298 .enetx_ctl = HPC3_ENETX_CTL, 299 .enetx_ctl_active = HPC3_ENETX_CTL_ACTIVE, 300 .enetx_dev = HPC3_ENETX_DEV, 301 .enetr_fifo = HPC3_ENETR_FIFO, 302 .enetr_fifo_size = HPC3_ENETR_FIFO_SIZE, 303 .enetx_fifo = HPC3_ENETX_FIFO, 304 .enetx_fifo_size = HPC3_ENETX_FIFO_SIZE, 305 .scsi0_devregs_size = HPC3_SCSI0_DEVREGS_SIZE, 306 .scsi1_devregs_size = HPC3_SCSI1_DEVREGS_SIZE, 307 .enet_devregs = HPC3_ENET_DEVREGS, 308 .enet_devregs_size = HPC3_ENET_DEVREGS_SIZE, 309 .pbus_fifo = HPC3_PBUS_FIFO, 310 .pbus_fifo_size = HPC3_PBUS_FIFO_SIZE, 311 .pbus_bbram = HPC3_PBUS_BBRAM, 312 .scsi_max_xfer = MAX_SCSI_XFER, 313 .scsi_dma_segs = (MAX_SCSI_XFER / 8192), 314 .scsi_dma_segs_size = 8192, 315 .clk_freq = 100, 316 .dma_datain_cmd = HPC3_DMACTL_ACTIVE, 317 .dma_dataout_cmd = (HPC3_DMACTL_ACTIVE | HPC3_DMACTL_DIR), 318 .scsi_dmactl_flush = HPC3_DMACTL_FLUSH, 319 .scsi_dmactl_active = HPC3_DMACTL_ACTIVE, 320 .scsi_dmactl_reset = HPC3_DMACTL_RESET 321 }; 322 323 324 static int powerintr_established; 325 326 static int hpc_match(struct device *, struct cfdata *, void *); 327 static void hpc_attach(struct device *, struct device *, void *); 328 static int hpc_print(void *, const char *); 329 330 static int hpc_revision(struct hpc_softc *, struct gio_attach_args *); 331 332 static int hpc_submatch(struct device *, struct cfdata *, 333 const int *, void *); 334 335 static int hpc_power_intr(void *); 336 337 #if defined(BLINK) 338 static struct callout hpc_blink_ch = CALLOUT_INITIALIZER; 339 static void hpc_blink(void *); 340 #endif 341 342 CFATTACH_DECL(hpc, sizeof(struct hpc_softc), 343 hpc_match, hpc_attach, NULL, NULL); 344 345 static int 346 hpc_match(struct device *parent, struct cfdata *cf, void *aux) 347 { 348 struct gio_attach_args* ga = aux; 349 350 /* Make sure it's actually there and readable */ 351 if (badaddr((void*)MIPS_PHYS_TO_KSEG1(ga->ga_addr), sizeof(u_int32_t))) 352 return 0; 353 354 return 1; 355 } 356 357 static void 358 hpc_attach(struct device *parent, struct device *self, void *aux) 359 { 360 struct hpc_softc *sc = (struct hpc_softc *)self; 361 struct gio_attach_args* ga = aux; 362 struct hpc_attach_args ha; 363 const struct hpc_device *hd; 364 uint32_t hpctype; 365 int sysmask; 366 367 switch (mach_type) { 368 case MACH_SGI_IP12: 369 sysmask = HPCDEV_IP12; 370 break; 371 372 case MACH_SGI_IP20: 373 sysmask = HPCDEV_IP20; 374 break; 375 376 case MACH_SGI_IP22: 377 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 378 sysmask = HPCDEV_IP22; 379 else 380 sysmask = HPCDEV_IP24; 381 break; 382 383 default: 384 panic("hpc_attach: can't handle HPC on an IP%d", mach_type); 385 }; 386 387 if ((hpctype = hpc_revision(sc, ga)) == 0) 388 panic("hpc_attach: could not identify HPC revision\n"); 389 390 /* force big-endian mode */ 391 if (hpctype == 15) 392 *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr+HPC1_BIGENDIAN) = 0; 393 394 printf(": SGI HPC%d%s\n", (hpctype == 3) ? 3 : 1, 395 (hpctype == 15) ? ".5" : ""); 396 397 sc->sc_ct = 1; 398 sc->sc_ch = ga->ga_ioh; 399 400 sc->sc_base = ga->ga_addr; 401 402 for (hd = hpc_devices; hd->hd_name != NULL; hd++) { 403 if (!(hd->hd_sysmask & sysmask) || hd->hd_base != sc->sc_base) 404 continue; 405 406 ha.ha_name = hd->hd_name; 407 ha.ha_devoff = hd->hd_devoff; 408 ha.ha_dmaoff = hd->hd_dmaoff; 409 ha.ha_irq = hd->hd_irq; 410 411 /* XXX This is disgusting. */ 412 ha.ha_st = 1; 413 ha.ha_sh = MIPS_PHYS_TO_KSEG1(sc->sc_base); 414 ha.ha_dmat = &sgimips_default_bus_dma_tag; 415 if (hpctype == 3) 416 ha.hpc_regs = &hpc3_values; 417 else 418 ha.hpc_regs = &hpc1_values; 419 ha.hpc_regs->revision = hpctype; 420 421 (void) config_found_sm_loc(self, "hpc", NULL, &ha, hpc_print, 422 hpc_submatch); 423 } 424 425 /* 426 * XXX: Only attach the powerfail interrupt once, since the 427 * interrupt code doesn't let you share interrupt just yet. 428 * 429 * Since the powerfail interrupt is hardcoded to read from 430 * a specific register anyway (XXX#2!), we don't care when 431 * it gets attached, as long as it only happens once. 432 */ 433 if (mach_type == MACH_SGI_IP22 && !powerintr_established) { 434 cpu_intr_establish(9, IPL_NONE, hpc_power_intr, sc); 435 powerintr_established++; 436 } 437 438 #if defined(BLINK) 439 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) 440 hpc_blink(sc); 441 #endif 442 } 443 444 /* 445 * HPC revision detection isn't as simple as it should be. Devices probe 446 * differently depending on their slots, but luckily there is only one 447 * instance in which we have to decide the major revision (HPC1 vs HPC3). 448 * 449 * The HPC is found in the following configurations: 450 * o Personal Iris 4D/3x: 451 * One on-board HPC1 or HPC1.5. 452 * 453 * o Indigo R3k/R4k: 454 * One on-board HPC1 or HPC1.5. 455 * Up to two additional HPC1.5's in GIO slots 0 and 1. 456 * 457 * o Indy: 458 * One on-board HPC3. 459 * Up to two additional HPC1.5's in GIO slots 0 and 1. 460 * 461 * o Challenge S 462 * One on-board HPC3. 463 * Up to one additional HPC3 on the IOPLUS board (if installed). 464 * Up to one additional HPC1.5 in slot 1 of the IOPLUS board. 465 * 466 * o Indigo2, Challenge M 467 * One on-board HPC3. 468 * 469 * All we really have to worry about is the IP22 case. 470 */ 471 static int 472 hpc_revision(struct hpc_softc *sc, struct gio_attach_args *ga) 473 { 474 475 /* No hardware ever supported the last hpc base address. */ 476 if (ga->ga_addr == HPC_BASE_ADDRESS_3) 477 return (0); 478 479 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) { 480 u_int32_t reg; 481 482 if (!badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 483 HPC1_BIGENDIAN), 4)) { 484 reg = *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 485 HPC1_BIGENDIAN); 486 487 if (((reg >> HPC1_REVSHIFT) & HPC1_REVMASK) == 488 HPC1_REV15) 489 return (15); 490 else 491 return (1); 492 } 493 494 return (1); 495 } 496 497 /* 498 * If IP22, probe slot 0 to determine if HPC1.5 or HPC3. Slot 1 must 499 * be HPC1.5. 500 * 501 * XXX - If Challenge S is Fullhouse, but without the eisa presence bit, 502 * we could just conditionalise on that, no? Or is it Guinness? 503 */ 504 if (mach_type == MACH_SGI_IP22) { 505 if (ga->ga_addr == HPC_BASE_ADDRESS_0) 506 return (3); 507 508 if (ga->ga_addr == HPC_BASE_ADDRESS_2) 509 return (15); 510 511 /* 512 * Probe for it. We use one of the PBUS registers. Note 513 * that this probe succeeds with my E++ adapter in slot 1, 514 * but it appears to do the right thing in slot 0! 515 */ 516 if (badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 517 HPC3_PBUS_CH7_BP), 4)) 518 return (15); 519 else 520 return (3); 521 } 522 523 return (0); 524 } 525 526 static int 527 hpc_submatch(struct device *parent, struct cfdata *cf, 528 const int *ldesc, void *aux) 529 { 530 struct hpc_attach_args *ha = aux; 531 532 if (cf->cf_loc[HPCCF_OFFSET] != HPCCF_OFFSET_DEFAULT && 533 (bus_addr_t) cf->cf_loc[HPCCF_OFFSET] != ha->ha_devoff) 534 return (0); 535 536 return (config_match(parent, cf, aux)); 537 } 538 539 static int 540 hpc_print(void *aux, const char *pnp) 541 { 542 struct hpc_attach_args *ha = aux; 543 544 if (pnp) 545 printf("%s at %s", ha->ha_name, pnp); 546 547 printf(" offset 0x%lx", ha->ha_devoff); 548 549 return (UNCONF); 550 } 551 552 static int 553 hpc_power_intr(void *arg) 554 { 555 u_int32_t pwr_reg; 556 557 pwr_reg = *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)); 558 *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)) = pwr_reg; 559 560 printf("hpc_power_intr: panel reg = %08x\n", pwr_reg); 561 562 if (pwr_reg & 2) 563 cpu_reboot(RB_HALT, NULL); 564 565 return 1; 566 } 567 568 #if defined(BLINK) 569 static void 570 hpc_blink(void *self) 571 { 572 struct hpc_softc *sc = (struct hpc_softc *) self; 573 register int s; 574 int value; 575 576 s = splhigh(); 577 578 value = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(HPC1_AUX_REGS); 579 value ^= HPC1_AUX_CONSLED; 580 *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(HPC1_AUX_REGS) = value; 581 splx(s); 582 583 /* 584 * Blink rate is: 585 * full cycle every second if completely idle (loadav = 0) 586 * full cycle every 2 seconds if loadav = 1 587 * full cycle every 3 seconds if loadav = 2 588 * etc. 589 */ 590 s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); 591 callout_reset(&hpc_blink_ch, s, hpc_blink, sc); 592 } 593 #endif 594 595
Indexes created Mon Sep 22 10:09:38 GMT 2025