hpc.c revision 1.49
1 /* $NetBSD: hpc.c,v 1.49 2006/12/22 23:36:42 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang 5 * Copyright (c) 2001 Rafal K. Boni 6 * Copyright (c) 2001 Jason R. Thorpe 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.49 2006/12/22 23:36:42 rumble Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/reboot.h> 45 #include <sys/callout.h> 46 47 #define _SGIMIPS_BUS_DMA_PRIVATE 48 #include <machine/bus.h> 49 #include <machine/machtype.h> 50 51 #include <sgimips/gio/gioreg.h> 52 #include <sgimips/gio/giovar.h> 53 54 #include <sgimips/hpc/hpcvar.h> 55 #include <sgimips/hpc/hpcreg.h> 56 #include <sgimips/ioc/iocreg.h> 57 58 #include <dev/ic/smc93cx6var.h> 59 60 #include "locators.h" 61 62 struct hpc_device { 63 const char *hd_name; 64 bus_addr_t hd_base; 65 bus_addr_t hd_devoff; 66 bus_addr_t hd_dmaoff; 67 int hd_irq; 68 int hd_sysmask; 69 }; 70 71 static const struct hpc_device hpc1_devices[] = { 72 /* probe order is important for IP20 zsc */ 73 74 { "zsc", /* Personal Iris/Indigo serial 0/1 duart 1 */ 75 HPC_BASE_ADDRESS_0, 76 0x0d10, 0, 77 5, 78 HPCDEV_IP12 | HPCDEV_IP20 }, 79 80 { "zsc", /* Personal Iris/Indigo kbd/ms duart 0 */ 81 HPC_BASE_ADDRESS_0, 82 0x0d00, 0, 83 5, 84 HPCDEV_IP12 | HPCDEV_IP20 }, 85 86 { "sq", /* Personal Iris/Indigo onboard ethernet */ 87 HPC_BASE_ADDRESS_0, 88 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 89 3, 90 HPCDEV_IP12 | HPCDEV_IP20 }, 91 92 { "sq", /* E++ GIO adapter slot 0 (Indigo) */ 93 HPC_BASE_ADDRESS_1, 94 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 95 6, 96 HPCDEV_IP12 | HPCDEV_IP20 }, 97 98 { "sq", /* E++ GIO adapter slot 0 (Indy) */ 99 HPC_BASE_ADDRESS_1, 100 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 101 22, 102 HPCDEV_IP24 }, 103 104 { "sq", /* E++ GIO adapter slot 1 (Indigo) */ 105 HPC_BASE_ADDRESS_2, 106 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 107 6, 108 HPCDEV_IP12 | HPCDEV_IP20 }, 109 110 { "sq", /* E++ GIO adapter slot 1 (Indy/Challenge S) */ 111 HPC_BASE_ADDRESS_2, 112 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 113 23, 114 HPCDEV_IP24 }, 115 116 { "wdsc", /* Personal Iris/Indigo onboard SCSI */ 117 HPC_BASE_ADDRESS_0, 118 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 119 2, /* XXX 1 = IRQ_LOCAL0 + 2 */ 120 HPCDEV_IP12 | HPCDEV_IP20 }, 121 122 { "dpclock", /* Personal Iris/Indigo clock */ 123 HPC_BASE_ADDRESS_0, 124 HPC1_PBUS_BBRAM, 0, 125 -1, 126 HPCDEV_IP12 | HPCDEV_IP20 }, 127 128 { NULL, 129 0, 130 0, 0, 131 0, 132 0 133 } 134 }; 135 136 static const struct hpc_device hpc3_devices[] = { 137 { "zsc", /* serial 0/1 duart 0 */ 138 HPC_BASE_ADDRESS_0, 139 /* XXX Magic numbers */ 140 HPC3_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0, 141 29, 142 HPCDEV_IP22 | HPCDEV_IP24 }, 143 144 { "pckbc", /* Indigo2/Indy ps2 keyboard/mouse controller */ 145 HPC_BASE_ADDRESS_0, 146 HPC3_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0, 147 28, 148 HPCDEV_IP22 | HPCDEV_IP24 }, 149 150 { "sq", /* Indigo2/Indy/Challenge S/Challenge M onboard enet */ 151 HPC_BASE_ADDRESS_0, 152 HPC3_ENET_DEVREGS, HPC3_ENET_REGS, 153 3, 154 HPCDEV_IP22 | HPCDEV_IP24 }, 155 156 { "sq", /* Challenge S IOPLUS secondary ethernet */ 157 HPC_BASE_ADDRESS_1, 158 HPC3_ENET_DEVREGS, HPC3_ENET_REGS, 159 22, 160 HPCDEV_IP24 }, 161 162 { "wdsc", /* Indigo2/Indy/Challenge S/Challenge M onboard SCSI */ 163 HPC_BASE_ADDRESS_0, 164 HPC3_SCSI0_DEVREGS, HPC3_SCSI0_REGS, 165 1, /* XXX 1 = IRQ_LOCAL0 + 1 */ 166 HPCDEV_IP22 | HPCDEV_IP24 }, 167 168 { "wdsc", /* Indigo2/Challenge M secondary onboard SCSI */ 169 HPC_BASE_ADDRESS_0, 170 HPC3_SCSI1_DEVREGS, HPC3_SCSI1_REGS, 171 2, /* XXX 2 = IRQ_LOCAL0 + 2 */ 172 HPCDEV_IP22 }, 173 174 { "dsclock", /* Indigo2/Indy/Challenge S/Challenge M clock */ 175 HPC_BASE_ADDRESS_0, 176 HPC3_PBUS_BBRAM, 0, 177 -1, 178 HPCDEV_IP22 | HPCDEV_IP24 }, 179 180 { "haltwo", /* Indigo2/Indy onboard audio */ 181 HPC_BASE_ADDRESS_0, 182 HPC3_PBUS_CH0_DEVREGS, HPC3_PBUS_DMAREGS, 183 8 + 4, /* XXX IRQ_LOCAL1 + 4 */ 184 HPCDEV_IP22 | HPCDEV_IP24 }, 185 186 { "pi1ppc", /* Indigo2/Indy/Challenge S/Challenge M onboard pport */ 187 HPC_BASE_ADDRESS_0, 188 HPC3_PBUS_CH6_DEVREGS + IOC_PLP_REGS, 0, 189 -1, 190 HPCDEV_IP22 | HPCDEV_IP24 }, 191 192 { NULL, 193 0, 194 0, 0, 195 0, 196 0 197 } 198 }; 199 200 struct hpc_softc { 201 struct device sc_dev; 202 203 bus_addr_t sc_base; 204 205 bus_space_tag_t sc_ct; 206 bus_space_handle_t sc_ch; 207 }; 208 209 static struct hpc_values hpc1_values = { 210 .revision = 1, 211 .scsi0_regs = HPC1_SCSI0_REGS, 212 .scsi0_regs_size = HPC1_SCSI0_REGS_SIZE, 213 .scsi0_cbp = HPC1_SCSI0_CBP, 214 .scsi0_ndbp = HPC1_SCSI0_NDBP, 215 .scsi0_bc = HPC1_SCSI0_BC, 216 .scsi0_ctl = HPC1_SCSI0_CTL, 217 .scsi0_gio = HPC1_SCSI0_GIO, 218 .scsi0_dev = HPC1_SCSI0_DEV, 219 .scsi0_dmacfg = HPC1_SCSI0_DMACFG, 220 .scsi0_piocfg = HPC1_SCSI0_PIOCFG, 221 .scsi1_regs = 0, 222 .scsi1_regs_size = 0, 223 .scsi1_cbp = 0, 224 .scsi1_ndbp = 0, 225 .scsi1_bc = 0, 226 .scsi1_ctl = 0, 227 .scsi1_gio = 0, 228 .scsi1_dev = 0, 229 .scsi1_dmacfg = 0, 230 .scsi1_piocfg = 0, 231 .enet_regs = HPC1_ENET_REGS, 232 .enet_regs_size = HPC1_ENET_REGS_SIZE, 233 .enet_intdelay = HPC1_ENET_INTDELAY, 234 .enet_intdelayval = HPC1_ENET_INTDELAY_OFF, 235 .enetr_cbp = HPC1_ENETR_CBP, 236 .enetr_ndbp = HPC1_ENETR_NDBP, 237 .enetr_bc = HPC1_ENETR_BC, 238 .enetr_ctl = HPC1_ENETR_CTL, 239 .enetr_ctl_active = HPC1_ENETR_CTL_ACTIVE, 240 .enetr_reset = HPC1_ENETR_RESET, 241 .enetr_dmacfg = 0, 242 .enetr_piocfg = 0, 243 .enetx_cbp = HPC1_ENETX_CBP, 244 .enetx_ndbp = HPC1_ENETX_NDBP, 245 .enetx_bc = HPC1_ENETX_BC, 246 .enetx_ctl = HPC1_ENETX_CTL, 247 .enetx_ctl_active = HPC1_ENETX_CTL_ACTIVE, 248 .enetx_dev = 0, 249 .enetr_fifo = HPC1_ENETR_FIFO, 250 .enetr_fifo_size = HPC1_ENETR_FIFO_SIZE, 251 .enetx_fifo = HPC1_ENETX_FIFO, 252 .enetx_fifo_size = HPC1_ENETX_FIFO_SIZE, 253 .scsi0_devregs_size = HPC1_SCSI0_DEVREGS_SIZE, 254 .scsi1_devregs_size = 0, 255 .enet_devregs = HPC1_ENET_DEVREGS, 256 .enet_devregs_size = HPC1_ENET_DEVREGS_SIZE, 257 .pbus_fifo = 0, 258 .pbus_fifo_size = 0, 259 .pbus_bbram = 0, 260 #define MAX_SCSI_XFER (512*1024) 261 .scsi_max_xfer = MAX_SCSI_XFER, 262 .scsi_dma_segs = (MAX_SCSI_XFER / 4096), 263 .scsi_dma_segs_size = 4096, 264 .scsi_dma_datain_cmd = (HPC1_SCSI_DMACTL_ACTIVE | HPC1_SCSI_DMACTL_DIR), 265 .scsi_dma_dataout_cmd = HPC1_SCSI_DMACTL_ACTIVE, 266 .scsi_dmactl_flush = HPC1_SCSI_DMACTL_FLUSH, 267 .scsi_dmactl_active = HPC1_SCSI_DMACTL_ACTIVE, 268 .scsi_dmactl_reset = HPC1_SCSI_DMACTL_RESET 269 }; 270 271 static struct hpc_values hpc3_values = { 272 .revision = 3, 273 .scsi0_regs = HPC3_SCSI0_REGS, 274 .scsi0_regs_size = HPC3_SCSI0_REGS_SIZE, 275 .scsi0_cbp = HPC3_SCSI0_CBP, 276 .scsi0_ndbp = HPC3_SCSI0_NDBP, 277 .scsi0_bc = HPC3_SCSI0_BC, 278 .scsi0_ctl = HPC3_SCSI0_CTL, 279 .scsi0_gio = HPC3_SCSI0_GIO, 280 .scsi0_dev = HPC3_SCSI0_DEV, 281 .scsi0_dmacfg = HPC3_SCSI0_DMACFG, 282 .scsi0_piocfg = HPC3_SCSI0_PIOCFG, 283 .scsi1_regs = HPC3_SCSI1_REGS, 284 .scsi1_regs_size = HPC3_SCSI1_REGS_SIZE, 285 .scsi1_cbp = HPC3_SCSI1_CBP, 286 .scsi1_ndbp = HPC3_SCSI1_NDBP, 287 .scsi1_bc = HPC3_SCSI1_BC, 288 .scsi1_ctl = HPC3_SCSI1_CTL, 289 .scsi1_gio = HPC3_SCSI1_GIO, 290 .scsi1_dev = HPC3_SCSI1_DEV, 291 .scsi1_dmacfg = HPC3_SCSI1_DMACFG, 292 .scsi1_piocfg = HPC3_SCSI1_PIOCFG, 293 .enet_regs = HPC3_ENET_REGS, 294 .enet_regs_size = HPC3_ENET_REGS_SIZE, 295 .enet_intdelay = 0, 296 .enet_intdelayval = 0, 297 .enetr_cbp = HPC3_ENETR_CBP, 298 .enetr_ndbp = HPC3_ENETR_NDBP, 299 .enetr_bc = HPC3_ENETR_BC, 300 .enetr_ctl = HPC3_ENETR_CTL, 301 .enetr_ctl_active = HPC3_ENETR_CTL_ACTIVE, 302 .enetr_reset = HPC3_ENETR_RESET, 303 .enetr_dmacfg = HPC3_ENETR_DMACFG, 304 .enetr_piocfg = HPC3_ENETR_PIOCFG, 305 .enetx_cbp = HPC3_ENETX_CBP, 306 .enetx_ndbp = HPC3_ENETX_NDBP, 307 .enetx_bc = HPC3_ENETX_BC, 308 .enetx_ctl = HPC3_ENETX_CTL, 309 .enetx_ctl_active = HPC3_ENETX_CTL_ACTIVE, 310 .enetx_dev = HPC3_ENETX_DEV, 311 .enetr_fifo = HPC3_ENETR_FIFO, 312 .enetr_fifo_size = HPC3_ENETR_FIFO_SIZE, 313 .enetx_fifo = HPC3_ENETX_FIFO, 314 .enetx_fifo_size = HPC3_ENETX_FIFO_SIZE, 315 .scsi0_devregs_size = HPC3_SCSI0_DEVREGS_SIZE, 316 .scsi1_devregs_size = HPC3_SCSI1_DEVREGS_SIZE, 317 .enet_devregs = HPC3_ENET_DEVREGS, 318 .enet_devregs_size = HPC3_ENET_DEVREGS_SIZE, 319 .pbus_fifo = HPC3_PBUS_FIFO, 320 .pbus_fifo_size = HPC3_PBUS_FIFO_SIZE, 321 .pbus_bbram = HPC3_PBUS_BBRAM, 322 .scsi_max_xfer = MAX_SCSI_XFER, 323 .scsi_dma_segs = (MAX_SCSI_XFER / 8192), 324 .scsi_dma_segs_size = 8192, 325 .scsi_dma_datain_cmd = HPC3_SCSI_DMACTL_ACTIVE, 326 .scsi_dma_dataout_cmd =(HPC3_SCSI_DMACTL_ACTIVE | HPC3_SCSI_DMACTL_DIR), 327 .scsi_dmactl_flush = HPC3_SCSI_DMACTL_FLUSH, 328 .scsi_dmactl_active = HPC3_SCSI_DMACTL_ACTIVE, 329 .scsi_dmactl_reset = HPC3_SCSI_DMACTL_RESET 330 }; 331 332 333 static int powerintr_established; 334 335 static int hpc_match(struct device *, struct cfdata *, void *); 336 static void hpc_attach(struct device *, struct device *, void *); 337 static int hpc_print(void *, const char *); 338 339 static int hpc_revision(struct hpc_softc *, struct gio_attach_args *); 340 341 static int hpc_submatch(struct device *, struct cfdata *, 342 const int *, void *); 343 344 static int hpc_power_intr(void *); 345 346 #if defined(BLINK) 347 static struct callout hpc_blink_ch = CALLOUT_INITIALIZER; 348 static void hpc_blink(void *); 349 #endif 350 351 static int hpc_read_eeprom(int, bus_space_tag_t, bus_space_handle_t, 352 uint8_t *, size_t); 353 354 CFATTACH_DECL(hpc, sizeof(struct hpc_softc), 355 hpc_match, hpc_attach, NULL, NULL); 356 357 static int 358 hpc_match(struct device *parent, struct cfdata *cf, void *aux) 359 { 360 struct gio_attach_args* ga = aux; 361 362 /* Make sure it's actually there and readable */ 363 if (badaddr((void*)MIPS_PHYS_TO_KSEG1(ga->ga_addr), sizeof(u_int32_t))) 364 return 0; 365 366 return 1; 367 } 368 369 static void 370 hpc_attach(struct device *parent, struct device *self, void *aux) 371 { 372 struct hpc_softc *sc = (struct hpc_softc *)self; 373 struct gio_attach_args* ga = aux; 374 struct hpc_attach_args ha; 375 const struct hpc_device *hd; 376 uint32_t hpctype; 377 int isonboard; 378 int isioplus; 379 int sysmask; 380 381 switch (mach_type) { 382 case MACH_SGI_IP12: 383 sysmask = HPCDEV_IP12; 384 break; 385 386 case MACH_SGI_IP20: 387 sysmask = HPCDEV_IP20; 388 break; 389 390 case MACH_SGI_IP22: 391 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 392 sysmask = HPCDEV_IP22; 393 else 394 sysmask = HPCDEV_IP24; 395 break; 396 397 default: 398 panic("hpc_attach: can't handle HPC on an IP%d", mach_type); 399 }; 400 401 if ((hpctype = hpc_revision(sc, ga)) == 0) 402 panic("hpc_attach: could not identify HPC revision\n"); 403 404 /* force big-endian mode */ 405 if (hpctype == 15) 406 *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr+HPC1_BIGENDIAN) = 0; 407 408 /* 409 * All machines have only one HPC on the mainboard itself. ''Extra'' 410 * HPCs require bus arbiter and other magic to run happily. 411 */ 412 isonboard = (ga->ga_addr == HPC_BASE_ADDRESS_0); 413 isioplus = (ga->ga_addr == HPC_BASE_ADDRESS_1 && hpctype == 3 && 414 sysmask == HPCDEV_IP24); 415 416 printf(": SGI HPC%d%s (%s)\n", (hpctype == 3) ? 3 : 1, 417 (hpctype == 15) ? ".5" : "", (isonboard) ? "onboard" : 418 (isioplus) ? "IOPLUS mezzanine" : "GIO slot"); 419 420 /* configure the bus arbiter appropriately (never happens on Indigo2) */ 421 if (!isonboard) { 422 int arb_slot; 423 424 arb_slot = (ga->ga_addr == HPC_BASE_ADDRESS_1) ? 425 GIO_SLOT_EXP0 : GIO_SLOT_EXP1; 426 427 if (gio_arb_config(arb_slot, GIO_ARB_RT | GIO_ARB_MST)) { 428 printf("%s: failed to configure GIO bus arbiter\n", 429 sc->sc_dev.dv_xname); 430 return; 431 } 432 } 433 434 sc->sc_ct = SGIMIPS_BUS_SPACE_HPC; 435 sc->sc_ch = ga->ga_ioh; 436 437 sc->sc_base = ga->ga_addr; 438 439 hd = (hpctype == 3) ? hpc3_devices : hpc1_devices; 440 for (; hd->hd_name != NULL; hd++) { 441 if (!(hd->hd_sysmask & sysmask) || hd->hd_base != sc->sc_base) 442 continue; 443 444 ha.ha_name = hd->hd_name; 445 ha.ha_devoff = hd->hd_devoff; 446 ha.ha_dmaoff = hd->hd_dmaoff; 447 ha.ha_irq = hd->hd_irq; 448 449 /* XXX This is disgusting. */ 450 ha.ha_st = SGIMIPS_BUS_SPACE_HPC; 451 ha.ha_sh = MIPS_PHYS_TO_KSEG1(sc->sc_base); 452 ha.ha_dmat = &sgimips_default_bus_dma_tag; 453 if (hpctype == 3) 454 ha.hpc_regs = &hpc3_values; 455 else 456 ha.hpc_regs = &hpc1_values; 457 ha.hpc_regs->revision = hpctype; 458 hpc_read_eeprom(hpctype, ha.ha_st, ha.ha_sh, ha.hpc_eeprom, 459 sizeof(ha.hpc_eeprom)); 460 461 (void) config_found_sm_loc(self, "hpc", NULL, &ha, hpc_print, 462 hpc_submatch); 463 } 464 465 /* 466 * XXX: Only attach the powerfail interrupt once, since the 467 * interrupt code doesn't let you share interrupt just yet. 468 * 469 * Since the powerfail interrupt is hardcoded to read from 470 * a specific register anyway (XXX#2!), we don't care when 471 * it gets attached, as long as it only happens once. 472 */ 473 if (mach_type == MACH_SGI_IP22 && !powerintr_established) { 474 cpu_intr_establish(9, IPL_NONE, hpc_power_intr, sc); 475 powerintr_established++; 476 } 477 478 #if defined(BLINK) 479 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) 480 hpc_blink(sc); 481 #endif 482 } 483 484 /* 485 * HPC revision detection isn't as simple as it should be. Devices probe 486 * differently depending on their slots, but luckily there is only one 487 * instance in which we have to decide the major revision (HPC1 vs HPC3). 488 * 489 * The HPC is found in the following configurations: 490 * o Personal Iris 4D/3x: 491 * One on-board HPC1 or HPC1.5. 492 * 493 * o Indigo R3k/R4k: 494 * One on-board HPC1 or HPC1.5. 495 * Up to two additional HPC1.5's in GIO slots 0 and 1. 496 * 497 * o Indy: 498 * One on-board HPC3. 499 * Up to two additional HPC1.5's in GIO slots 0 and 1. 500 * 501 * o Challenge S 502 * One on-board HPC3. 503 * Up to one additional HPC3 on the IOPLUS board (if installed). 504 * Up to one additional HPC1.5 in slot 1 of the IOPLUS board. 505 * 506 * o Indigo2, Challenge M 507 * One on-board HPC3. 508 * 509 * All we really have to worry about is the IP22 case. 510 */ 511 static int 512 hpc_revision(struct hpc_softc *sc, struct gio_attach_args *ga) 513 { 514 515 /* No hardware ever supported the last hpc base address. */ 516 if (ga->ga_addr == HPC_BASE_ADDRESS_3) 517 return (0); 518 519 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) { 520 u_int32_t reg; 521 522 if (!badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 523 HPC1_BIGENDIAN), 4)) { 524 reg = *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 525 HPC1_BIGENDIAN); 526 527 if (((reg >> HPC1_REVSHIFT) & HPC1_REVMASK) == 528 HPC1_REV15) 529 return (15); 530 else 531 return (1); 532 } 533 534 return (1); 535 } 536 537 /* 538 * If IP22, probe slot 0 to determine if HPC1.5 or HPC3. Slot 1 must 539 * be HPC1.5. 540 * 541 * XXX - If Challenge S is Fullhouse, but without the eisa presence bit, 542 * we could just conditionalise on that, no? Or is it Guinness? 543 */ 544 if (mach_type == MACH_SGI_IP22) { 545 if (ga->ga_addr == HPC_BASE_ADDRESS_0) 546 return (3); 547 548 if (ga->ga_addr == HPC_BASE_ADDRESS_2) 549 return (15); 550 551 /* 552 * Probe for it. We use one of the PBUS registers. Note 553 * that this probe succeeds with my E++ adapter in slot 1, 554 * but it appears to do the right thing in slot 0! 555 */ 556 if (badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 557 HPC3_PBUS_CH7_BP), 4)) 558 return (15); 559 else 560 return (3); 561 } 562 563 return (0); 564 } 565 566 static int 567 hpc_submatch(struct device *parent, struct cfdata *cf, 568 const int *ldesc, void *aux) 569 { 570 struct hpc_attach_args *ha = aux; 571 572 if (cf->cf_loc[HPCCF_OFFSET] != HPCCF_OFFSET_DEFAULT && 573 (bus_addr_t) cf->cf_loc[HPCCF_OFFSET] != ha->ha_devoff) 574 return (0); 575 576 return (config_match(parent, cf, aux)); 577 } 578 579 static int 580 hpc_print(void *aux, const char *pnp) 581 { 582 struct hpc_attach_args *ha = aux; 583 584 if (pnp) 585 printf("%s at %s", ha->ha_name, pnp); 586 587 printf(" offset 0x%lx", ha->ha_devoff); 588 589 return (UNCONF); 590 } 591 592 static int 593 hpc_power_intr(void *arg) 594 { 595 u_int32_t pwr_reg; 596 597 pwr_reg = *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)); 598 *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)) = pwr_reg; 599 600 printf("hpc_power_intr: panel reg = %08x\n", pwr_reg); 601 602 if (pwr_reg & 2) 603 cpu_reboot(RB_HALT, NULL); 604 605 return 1; 606 } 607 608 #if defined(BLINK) 609 static void 610 hpc_blink(void *self) 611 { 612 struct hpc_softc *sc = (struct hpc_softc *) self; 613 register int s; 614 int value; 615 616 s = splhigh(); 617 618 value = *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + 619 HPC1_AUX_REGS); 620 value ^= HPC1_AUX_CONSLED; 621 *(volatile u_int8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + 622 HPC1_AUX_REGS) = value; 623 splx(s); 624 625 /* 626 * Blink rate is: 627 * full cycle every second if completely idle (loadav = 0) 628 * full cycle every 2 seconds if loadav = 1 629 * full cycle every 3 seconds if loadav = 2 630 * etc. 631 */ 632 s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); 633 callout_reset(&hpc_blink_ch, s, hpc_blink, sc); 634 } 635 #endif 636 637 /* 638 * Read the eeprom associated with one of the HPC's. 639 * 640 * NB: An eeprom is not always present, but the HPC should be able to 641 * handle this gracefully. Any consumers should validate the data to 642 * ensure it's reasonable. 643 */ 644 static int 645 hpc_read_eeprom(int hpctype, bus_space_tag_t t, bus_space_handle_t h, 646 uint8_t *buf, size_t len) 647 { 648 struct seeprom_descriptor sd; 649 bus_space_handle_t bsh; 650 bus_space_tag_t tag; 651 bus_size_t offset; 652 653 if (!len || len & 0x1) 654 return (1); 655 656 offset = (hpctype == 3) ? HPC3_EEPROM_DATA : HPC1_AUX_REGS; 657 658 tag = SGIMIPS_BUS_SPACE_NORMAL; 659 if (bus_space_subregion(t, h, offset, 1, &bsh) != 0) 660 return (1); 661 662 sd.sd_chip = C56_66; 663 sd.sd_tag = tag; 664 sd.sd_bsh = bsh; 665 sd.sd_regsize = 1; 666 sd.sd_control_offset = 0; 667 sd.sd_status_offset = 0; 668 sd.sd_dataout_offset = 0; 669 sd.sd_DI = 0x10; /* EEPROM -> CPU */ 670 sd.sd_DO = 0x08; /* CPU -> EEPROM */ 671 sd.sd_CK = 0x04; 672 sd.sd_CS = 0x02; 673 sd.sd_MS = 0; 674 sd.sd_RDY = 0; 675 676 if (read_seeprom(&sd, (uint16_t *)buf, 0, len / 2) != 1) 677 return (1); 678 679 bus_space_unmap(t, bsh, 1); 680 681 return (0); 682 } 683
Indexes created Mon Sep 22 05:09:51 GMT 2025