hpc.c revision 1.51
1 /* $NetBSD: hpc.c,v 1.51 2006/12/29 07:15:01 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang 5 * Copyright (c) 2001 Rafal K. Boni 6 * Copyright (c) 2001 Jason R. Thorpe 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.51 2006/12/29 07:15:01 rumble Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/reboot.h> 45 #include <sys/callout.h> 46 47 #define _SGIMIPS_BUS_DMA_PRIVATE 48 #include <machine/bus.h> 49 #include <machine/machtype.h> 50 #include <machine/sysconf.h> 51 52 #include <sgimips/gio/gioreg.h> 53 #include <sgimips/gio/giovar.h> 54 55 #include <sgimips/hpc/hpcvar.h> 56 #include <sgimips/hpc/hpcreg.h> 57 #include <sgimips/ioc/iocreg.h> 58 59 #include <dev/ic/smc93cx6var.h> 60 61 #include "locators.h" 62 63 struct hpc_device { 64 const char *hd_name; 65 bus_addr_t hd_base; 66 bus_addr_t hd_devoff; 67 bus_addr_t hd_dmaoff; 68 int hd_irq; 69 int hd_sysmask; 70 }; 71 72 static const struct hpc_device hpc1_devices[] = { 73 /* probe order is important for IP20 zsc */ 74 75 { "zsc", /* Personal Iris/Indigo serial 0/1 duart 1 */ 76 HPC_BASE_ADDRESS_0, 77 0x0d10, 0, 78 5, 79 HPCDEV_IP12 | HPCDEV_IP20 }, 80 81 { "zsc", /* Personal Iris/Indigo kbd/ms duart 0 */ 82 HPC_BASE_ADDRESS_0, 83 0x0d00, 0, 84 5, 85 HPCDEV_IP12 | HPCDEV_IP20 }, 86 87 { "sq", /* Personal Iris/Indigo onboard ethernet */ 88 HPC_BASE_ADDRESS_0, 89 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 90 3, 91 HPCDEV_IP12 | HPCDEV_IP20 }, 92 93 { "sq", /* E++ GIO adapter slot 0 (Indigo) */ 94 HPC_BASE_ADDRESS_1, 95 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 96 6, 97 HPCDEV_IP12 | HPCDEV_IP20 }, 98 99 { "sq", /* E++ GIO adapter slot 0 (Indy) */ 100 HPC_BASE_ADDRESS_1, 101 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 102 22, 103 HPCDEV_IP24 }, 104 105 { "sq", /* E++ GIO adapter slot 1 (Indigo) */ 106 HPC_BASE_ADDRESS_2, 107 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 108 6, 109 HPCDEV_IP12 | HPCDEV_IP20 }, 110 111 { "sq", /* E++ GIO adapter slot 1 (Indy/Challenge S) */ 112 HPC_BASE_ADDRESS_2, 113 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 114 23, 115 HPCDEV_IP24 }, 116 117 { "wdsc", /* Personal Iris/Indigo onboard SCSI */ 118 HPC_BASE_ADDRESS_0, 119 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 120 2, /* XXX 1 = IRQ_LOCAL0 + 2 */ 121 HPCDEV_IP12 | HPCDEV_IP20 }, 122 123 { "dpclock", /* Personal Iris/Indigo clock */ 124 HPC_BASE_ADDRESS_0, 125 HPC1_PBUS_BBRAM, 0, 126 -1, 127 HPCDEV_IP12 | HPCDEV_IP20 }, 128 129 { NULL, 130 0, 131 0, 0, 132 0, 133 0 134 } 135 }; 136 137 static const struct hpc_device hpc3_devices[] = { 138 { "zsc", /* serial 0/1 duart 0 */ 139 HPC_BASE_ADDRESS_0, 140 /* XXX Magic numbers */ 141 HPC3_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0, 142 29, 143 HPCDEV_IP22 | HPCDEV_IP24 }, 144 145 { "pckbc", /* Indigo2/Indy ps2 keyboard/mouse controller */ 146 HPC_BASE_ADDRESS_0, 147 HPC3_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0, 148 28, 149 HPCDEV_IP22 | HPCDEV_IP24 }, 150 151 { "sq", /* Indigo2/Indy/Challenge S/Challenge M onboard enet */ 152 HPC_BASE_ADDRESS_0, 153 HPC3_ENET_DEVREGS, HPC3_ENET_REGS, 154 3, 155 HPCDEV_IP22 | HPCDEV_IP24 }, 156 157 { "sq", /* Challenge S IOPLUS secondary ethernet */ 158 HPC_BASE_ADDRESS_1, 159 HPC3_ENET_DEVREGS, HPC3_ENET_REGS, 160 22, 161 HPCDEV_IP24 }, 162 163 { "wdsc", /* Indigo2/Indy/Challenge S/Challenge M onboard SCSI */ 164 HPC_BASE_ADDRESS_0, 165 HPC3_SCSI0_DEVREGS, HPC3_SCSI0_REGS, 166 1, /* XXX 1 = IRQ_LOCAL0 + 1 */ 167 HPCDEV_IP22 | HPCDEV_IP24 }, 168 169 { "wdsc", /* Indigo2/Challenge M secondary onboard SCSI */ 170 HPC_BASE_ADDRESS_0, 171 HPC3_SCSI1_DEVREGS, HPC3_SCSI1_REGS, 172 2, /* XXX 2 = IRQ_LOCAL0 + 2 */ 173 HPCDEV_IP22 }, 174 175 { "dsclock", /* Indigo2/Indy/Challenge S/Challenge M clock */ 176 HPC_BASE_ADDRESS_0, 177 HPC3_PBUS_BBRAM, 0, 178 -1, 179 HPCDEV_IP22 | HPCDEV_IP24 }, 180 181 { "haltwo", /* Indigo2/Indy onboard audio */ 182 HPC_BASE_ADDRESS_0, 183 HPC3_PBUS_CH0_DEVREGS, HPC3_PBUS_DMAREGS, 184 8 + 4, /* XXX IRQ_LOCAL1 + 4 */ 185 HPCDEV_IP22 | HPCDEV_IP24 }, 186 187 { "pi1ppc", /* Indigo2/Indy/Challenge S/Challenge M onboard pport */ 188 HPC_BASE_ADDRESS_0, 189 HPC3_PBUS_CH6_DEVREGS + IOC_PLP_REGS, 0, 190 -1, 191 HPCDEV_IP22 | HPCDEV_IP24 }, 192 193 { NULL, 194 0, 195 0, 0, 196 0, 197 0 198 } 199 }; 200 201 struct hpc_softc { 202 struct device sc_dev; 203 204 bus_addr_t sc_base; 205 206 bus_space_tag_t sc_ct; 207 bus_space_handle_t sc_ch; 208 }; 209 210 static struct hpc_values hpc1_values = { 211 .revision = 1, 212 .scsi0_regs = HPC1_SCSI0_REGS, 213 .scsi0_regs_size = HPC1_SCSI0_REGS_SIZE, 214 .scsi0_cbp = HPC1_SCSI0_CBP, 215 .scsi0_ndbp = HPC1_SCSI0_NDBP, 216 .scsi0_bc = HPC1_SCSI0_BC, 217 .scsi0_ctl = HPC1_SCSI0_CTL, 218 .scsi0_gio = HPC1_SCSI0_GIO, 219 .scsi0_dev = HPC1_SCSI0_DEV, 220 .scsi0_dmacfg = HPC1_SCSI0_DMACFG, 221 .scsi0_piocfg = HPC1_SCSI0_PIOCFG, 222 .scsi1_regs = 0, 223 .scsi1_regs_size = 0, 224 .scsi1_cbp = 0, 225 .scsi1_ndbp = 0, 226 .scsi1_bc = 0, 227 .scsi1_ctl = 0, 228 .scsi1_gio = 0, 229 .scsi1_dev = 0, 230 .scsi1_dmacfg = 0, 231 .scsi1_piocfg = 0, 232 .enet_regs = HPC1_ENET_REGS, 233 .enet_regs_size = HPC1_ENET_REGS_SIZE, 234 .enet_intdelay = HPC1_ENET_INTDELAY, 235 .enet_intdelayval = HPC1_ENET_INTDELAY_OFF, 236 .enetr_cbp = HPC1_ENETR_CBP, 237 .enetr_ndbp = HPC1_ENETR_NDBP, 238 .enetr_bc = HPC1_ENETR_BC, 239 .enetr_ctl = HPC1_ENETR_CTL, 240 .enetr_ctl_active = HPC1_ENETR_CTL_ACTIVE, 241 .enetr_reset = HPC1_ENETR_RESET, 242 .enetr_dmacfg = 0, 243 .enetr_piocfg = 0, 244 .enetx_cbp = HPC1_ENETX_CBP, 245 .enetx_ndbp = HPC1_ENETX_NDBP, 246 .enetx_bc = HPC1_ENETX_BC, 247 .enetx_ctl = HPC1_ENETX_CTL, 248 .enetx_ctl_active = HPC1_ENETX_CTL_ACTIVE, 249 .enetx_dev = 0, 250 .enetr_fifo = HPC1_ENETR_FIFO, 251 .enetr_fifo_size = HPC1_ENETR_FIFO_SIZE, 252 .enetx_fifo = HPC1_ENETX_FIFO, 253 .enetx_fifo_size = HPC1_ENETX_FIFO_SIZE, 254 .scsi0_devregs_size = HPC1_SCSI0_DEVREGS_SIZE, 255 .scsi1_devregs_size = 0, 256 .enet_devregs = HPC1_ENET_DEVREGS, 257 .enet_devregs_size = HPC1_ENET_DEVREGS_SIZE, 258 .pbus_fifo = 0, 259 .pbus_fifo_size = 0, 260 .pbus_bbram = 0, 261 #define MAX_SCSI_XFER (512*1024) 262 .scsi_max_xfer = MAX_SCSI_XFER, 263 .scsi_dma_segs = (MAX_SCSI_XFER / 4096), 264 .scsi_dma_segs_size = 4096, 265 .scsi_dma_datain_cmd = (HPC1_SCSI_DMACTL_ACTIVE | HPC1_SCSI_DMACTL_DIR), 266 .scsi_dma_dataout_cmd = HPC1_SCSI_DMACTL_ACTIVE, 267 .scsi_dmactl_flush = HPC1_SCSI_DMACTL_FLUSH, 268 .scsi_dmactl_active = HPC1_SCSI_DMACTL_ACTIVE, 269 .scsi_dmactl_reset = HPC1_SCSI_DMACTL_RESET 270 }; 271 272 static struct hpc_values hpc3_values = { 273 .revision = 3, 274 .scsi0_regs = HPC3_SCSI0_REGS, 275 .scsi0_regs_size = HPC3_SCSI0_REGS_SIZE, 276 .scsi0_cbp = HPC3_SCSI0_CBP, 277 .scsi0_ndbp = HPC3_SCSI0_NDBP, 278 .scsi0_bc = HPC3_SCSI0_BC, 279 .scsi0_ctl = HPC3_SCSI0_CTL, 280 .scsi0_gio = HPC3_SCSI0_GIO, 281 .scsi0_dev = HPC3_SCSI0_DEV, 282 .scsi0_dmacfg = HPC3_SCSI0_DMACFG, 283 .scsi0_piocfg = HPC3_SCSI0_PIOCFG, 284 .scsi1_regs = HPC3_SCSI1_REGS, 285 .scsi1_regs_size = HPC3_SCSI1_REGS_SIZE, 286 .scsi1_cbp = HPC3_SCSI1_CBP, 287 .scsi1_ndbp = HPC3_SCSI1_NDBP, 288 .scsi1_bc = HPC3_SCSI1_BC, 289 .scsi1_ctl = HPC3_SCSI1_CTL, 290 .scsi1_gio = HPC3_SCSI1_GIO, 291 .scsi1_dev = HPC3_SCSI1_DEV, 292 .scsi1_dmacfg = HPC3_SCSI1_DMACFG, 293 .scsi1_piocfg = HPC3_SCSI1_PIOCFG, 294 .enet_regs = HPC3_ENET_REGS, 295 .enet_regs_size = HPC3_ENET_REGS_SIZE, 296 .enet_intdelay = 0, 297 .enet_intdelayval = 0, 298 .enetr_cbp = HPC3_ENETR_CBP, 299 .enetr_ndbp = HPC3_ENETR_NDBP, 300 .enetr_bc = HPC3_ENETR_BC, 301 .enetr_ctl = HPC3_ENETR_CTL, 302 .enetr_ctl_active = HPC3_ENETR_CTL_ACTIVE, 303 .enetr_reset = HPC3_ENETR_RESET, 304 .enetr_dmacfg = HPC3_ENETR_DMACFG, 305 .enetr_piocfg = HPC3_ENETR_PIOCFG, 306 .enetx_cbp = HPC3_ENETX_CBP, 307 .enetx_ndbp = HPC3_ENETX_NDBP, 308 .enetx_bc = HPC3_ENETX_BC, 309 .enetx_ctl = HPC3_ENETX_CTL, 310 .enetx_ctl_active = HPC3_ENETX_CTL_ACTIVE, 311 .enetx_dev = HPC3_ENETX_DEV, 312 .enetr_fifo = HPC3_ENETR_FIFO, 313 .enetr_fifo_size = HPC3_ENETR_FIFO_SIZE, 314 .enetx_fifo = HPC3_ENETX_FIFO, 315 .enetx_fifo_size = HPC3_ENETX_FIFO_SIZE, 316 .scsi0_devregs_size = HPC3_SCSI0_DEVREGS_SIZE, 317 .scsi1_devregs_size = HPC3_SCSI1_DEVREGS_SIZE, 318 .enet_devregs = HPC3_ENET_DEVREGS, 319 .enet_devregs_size = HPC3_ENET_DEVREGS_SIZE, 320 .pbus_fifo = HPC3_PBUS_FIFO, 321 .pbus_fifo_size = HPC3_PBUS_FIFO_SIZE, 322 .pbus_bbram = HPC3_PBUS_BBRAM, 323 .scsi_max_xfer = MAX_SCSI_XFER, 324 .scsi_dma_segs = (MAX_SCSI_XFER / 8192), 325 .scsi_dma_segs_size = 8192, 326 .scsi_dma_datain_cmd = HPC3_SCSI_DMACTL_ACTIVE, 327 .scsi_dma_dataout_cmd =(HPC3_SCSI_DMACTL_ACTIVE | HPC3_SCSI_DMACTL_DIR), 328 .scsi_dmactl_flush = HPC3_SCSI_DMACTL_FLUSH, 329 .scsi_dmactl_active = HPC3_SCSI_DMACTL_ACTIVE, 330 .scsi_dmactl_reset = HPC3_SCSI_DMACTL_RESET 331 }; 332 333 334 static int powerintr_established; 335 336 static int hpc_match(struct device *, struct cfdata *, void *); 337 static void hpc_attach(struct device *, struct device *, void *); 338 static int hpc_print(void *, const char *); 339 340 static int hpc_revision(struct hpc_softc *, struct gio_attach_args *); 341 342 static int hpc_submatch(struct device *, struct cfdata *, 343 const int *, void *); 344 345 static int hpc_power_intr(void *); 346 347 #if defined(BLINK) 348 static struct callout hpc_blink_ch = CALLOUT_INITIALIZER; 349 static void hpc_blink(void *); 350 #endif 351 352 static int hpc_read_eeprom(int, bus_space_tag_t, bus_space_handle_t, 353 uint8_t *, size_t); 354 355 CFATTACH_DECL(hpc, sizeof(struct hpc_softc), 356 hpc_match, hpc_attach, NULL, NULL); 357 358 static int 359 hpc_match(struct device *parent, struct cfdata *cf, void *aux) 360 { 361 struct gio_attach_args* ga = aux; 362 363 /* Make sure it's actually there and readable */ 364 if (platform.badaddr((void*)MIPS_PHYS_TO_KSEG1(ga->ga_addr), 365 sizeof(u_int32_t))) 366 return 0; 367 368 return 1; 369 } 370 371 static void 372 hpc_attach(struct device *parent, struct device *self, void *aux) 373 { 374 struct hpc_softc *sc = (struct hpc_softc *)self; 375 struct gio_attach_args* ga = aux; 376 struct hpc_attach_args ha; 377 const struct hpc_device *hd; 378 uint32_t hpctype; 379 int isonboard; 380 int isioplus; 381 int sysmask; 382 383 switch (mach_type) { 384 case MACH_SGI_IP12: 385 sysmask = HPCDEV_IP12; 386 break; 387 388 case MACH_SGI_IP20: 389 sysmask = HPCDEV_IP20; 390 break; 391 392 case MACH_SGI_IP22: 393 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 394 sysmask = HPCDEV_IP22; 395 else 396 sysmask = HPCDEV_IP24; 397 break; 398 399 default: 400 panic("hpc_attach: can't handle HPC on an IP%d", mach_type); 401 }; 402 403 if ((hpctype = hpc_revision(sc, ga)) == 0) 404 panic("hpc_attach: could not identify HPC revision\n"); 405 406 /* force big-endian mode */ 407 if (hpctype == 15) 408 *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr+HPC1_BIGENDIAN) = 0; 409 410 /* 411 * All machines have only one HPC on the mainboard itself. ''Extra'' 412 * HPCs require bus arbiter and other magic to run happily. 413 */ 414 isonboard = (ga->ga_addr == HPC_BASE_ADDRESS_0); 415 isioplus = (ga->ga_addr == HPC_BASE_ADDRESS_1 && hpctype == 3 && 416 sysmask == HPCDEV_IP24); 417 418 printf(": SGI HPC%d%s (%s)\n", (hpctype == 3) ? 3 : 1, 419 (hpctype == 15) ? ".5" : "", (isonboard) ? "onboard" : 420 (isioplus) ? "IOPLUS mezzanine" : "GIO slot"); 421 422 /* configure the bus arbiter appropriately (never happens on Indigo2) */ 423 if (!isonboard) { 424 int arb_slot; 425 426 arb_slot = (ga->ga_addr == HPC_BASE_ADDRESS_1) ? 427 GIO_SLOT_EXP0 : GIO_SLOT_EXP1; 428 429 if (gio_arb_config(arb_slot, GIO_ARB_RT | GIO_ARB_MST)) { 430 printf("%s: failed to configure GIO bus arbiter\n", 431 sc->sc_dev.dv_xname); 432 return; 433 } 434 } 435 436 sc->sc_ct = SGIMIPS_BUS_SPACE_HPC; 437 sc->sc_ch = ga->ga_ioh; 438 439 sc->sc_base = ga->ga_addr; 440 441 hd = (hpctype == 3) ? hpc3_devices : hpc1_devices; 442 for (; hd->hd_name != NULL; hd++) { 443 if (!(hd->hd_sysmask & sysmask) || hd->hd_base != sc->sc_base) 444 continue; 445 446 ha.ha_name = hd->hd_name; 447 ha.ha_devoff = hd->hd_devoff; 448 ha.ha_dmaoff = hd->hd_dmaoff; 449 ha.ha_irq = hd->hd_irq; 450 451 /* XXX This is disgusting. */ 452 ha.ha_st = SGIMIPS_BUS_SPACE_HPC; 453 ha.ha_sh = MIPS_PHYS_TO_KSEG1(sc->sc_base); 454 ha.ha_dmat = &sgimips_default_bus_dma_tag; 455 if (hpctype == 3) 456 ha.hpc_regs = &hpc3_values; 457 else 458 ha.hpc_regs = &hpc1_values; 459 ha.hpc_regs->revision = hpctype; 460 hpc_read_eeprom(hpctype, ha.ha_st, ha.ha_sh, ha.hpc_eeprom, 461 sizeof(ha.hpc_eeprom)); 462 463 (void) config_found_sm_loc(self, "hpc", NULL, &ha, hpc_print, 464 hpc_submatch); 465 } 466 467 /* 468 * XXX: Only attach the powerfail interrupt once, since the 469 * interrupt code doesn't let you share interrupt just yet. 470 * 471 * Since the powerfail interrupt is hardcoded to read from 472 * a specific register anyway (XXX#2!), we don't care when 473 * it gets attached, as long as it only happens once. 474 */ 475 if (mach_type == MACH_SGI_IP22 && !powerintr_established) { 476 cpu_intr_establish(9, IPL_NONE, hpc_power_intr, sc); 477 powerintr_established++; 478 } 479 480 #if defined(BLINK) 481 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) 482 hpc_blink(sc); 483 #endif 484 } 485 486 /* 487 * HPC revision detection isn't as simple as it should be. Devices probe 488 * differently depending on their slots, but luckily there is only one 489 * instance in which we have to decide the major revision (HPC1 vs HPC3). 490 * 491 * The HPC is found in the following configurations: 492 * o Personal Iris 4D/3x: 493 * One on-board HPC1 or HPC1.5. 494 * 495 * o Indigo R3k/R4k: 496 * One on-board HPC1 or HPC1.5. 497 * Up to two additional HPC1.5's in GIO slots 0 and 1. 498 * 499 * o Indy: 500 * One on-board HPC3. 501 * Up to two additional HPC1.5's in GIO slots 0 and 1. 502 * 503 * o Challenge S 504 * One on-board HPC3. 505 * Up to one additional HPC3 on the IOPLUS board (if installed). 506 * Up to one additional HPC1.5 in slot 1 of the IOPLUS board. 507 * 508 * o Indigo2, Challenge M 509 * One on-board HPC3. 510 * 511 * All we really have to worry about is the IP22 case. 512 */ 513 static int 514 hpc_revision(struct hpc_softc *sc, struct gio_attach_args *ga) 515 { 516 517 /* No hardware ever supported the last hpc base address. */ 518 if (ga->ga_addr == HPC_BASE_ADDRESS_3) 519 return (0); 520 521 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) { 522 u_int32_t reg; 523 524 if (!platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 525 HPC1_BIGENDIAN), 4)) { 526 reg = *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 527 HPC1_BIGENDIAN); 528 529 if (((reg >> HPC1_REVSHIFT) & HPC1_REVMASK) == 530 HPC1_REV15) 531 return (15); 532 else 533 return (1); 534 } 535 536 return (1); 537 } 538 539 /* 540 * If IP22, probe slot 0 to determine if HPC1.5 or HPC3. Slot 1 must 541 * be HPC1.5. 542 */ 543 if (mach_type == MACH_SGI_IP22) { 544 if (ga->ga_addr == HPC_BASE_ADDRESS_0) 545 return (3); 546 547 if (ga->ga_addr == HPC_BASE_ADDRESS_2) 548 return (15); 549 550 /* 551 * Probe for it. We use one of the PBUS registers. Note 552 * that this probe succeeds with my E++ adapter in slot 1 553 * (bad), but it appears to always do the right thing in 554 * slot 0 (good!) and we're only worried about that one 555 * anyhow. 556 */ 557 if (platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 558 HPC3_PBUS_CH7_BP), 4)) 559 return (15); 560 else 561 return (3); 562 } 563 564 return (0); 565 } 566 567 static int 568 hpc_submatch(struct device *parent, struct cfdata *cf, 569 const int *ldesc, void *aux) 570 { 571 struct hpc_attach_args *ha = aux; 572 573 if (cf->cf_loc[HPCCF_OFFSET] != HPCCF_OFFSET_DEFAULT && 574 (bus_addr_t) cf->cf_loc[HPCCF_OFFSET] != ha->ha_devoff) 575 return (0); 576 577 return (config_match(parent, cf, aux)); 578 } 579 580 static int 581 hpc_print(void *aux, const char *pnp) 582 { 583 struct hpc_attach_args *ha = aux; 584 585 if (pnp) 586 printf("%s at %s", ha->ha_name, pnp); 587 588 printf(" offset 0x%lx", ha->ha_devoff); 589 590 return (UNCONF); 591 } 592 593 static int 594 hpc_power_intr(void *arg) 595 { 596 u_int32_t pwr_reg; 597 598 pwr_reg = *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)); 599 *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)) = pwr_reg; 600 601 printf("hpc_power_intr: panel reg = %08x\n", pwr_reg); 602 603 if (pwr_reg & 2) 604 cpu_reboot(RB_HALT, NULL); 605 606 return 1; 607 } 608 609 #if defined(BLINK) 610 static void 611 hpc_blink(void *self) 612 { 613 struct hpc_softc *sc = (struct hpc_softc *) self; 614 register int s; 615 int value; 616 617 s = splhigh(); 618 619 value = *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + 620 HPC1_AUX_REGS); 621 value ^= HPC1_AUX_CONSLED; 622 *(volatile u_int8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + 623 HPC1_AUX_REGS) = value; 624 splx(s); 625 626 /* 627 * Blink rate is: 628 * full cycle every second if completely idle (loadav = 0) 629 * full cycle every 2 seconds if loadav = 1 630 * full cycle every 3 seconds if loadav = 2 631 * etc. 632 */ 633 s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); 634 callout_reset(&hpc_blink_ch, s, hpc_blink, sc); 635 } 636 #endif 637 638 /* 639 * Read the eeprom associated with one of the HPC's. 640 * 641 * NB: An eeprom is not always present, but the HPC should be able to 642 * handle this gracefully. Any consumers should validate the data to 643 * ensure it's reasonable. 644 */ 645 static int 646 hpc_read_eeprom(int hpctype, bus_space_tag_t t, bus_space_handle_t h, 647 uint8_t *buf, size_t len) 648 { 649 struct seeprom_descriptor sd; 650 bus_space_handle_t bsh; 651 bus_space_tag_t tag; 652 bus_size_t offset; 653 654 if (!len || len & 0x1) 655 return (1); 656 657 offset = (hpctype == 3) ? HPC3_EEPROM_DATA : HPC1_AUX_REGS; 658 659 tag = SGIMIPS_BUS_SPACE_NORMAL; 660 if (bus_space_subregion(t, h, offset, 1, &bsh) != 0) 661 return (1); 662 663 sd.sd_chip = C56_66; 664 sd.sd_tag = tag; 665 sd.sd_bsh = bsh; 666 sd.sd_regsize = 1; 667 sd.sd_control_offset = 0; 668 sd.sd_status_offset = 0; 669 sd.sd_dataout_offset = 0; 670 sd.sd_DI = 0x10; /* EEPROM -> CPU */ 671 sd.sd_DO = 0x08; /* CPU -> EEPROM */ 672 sd.sd_CK = 0x04; 673 sd.sd_CS = 0x02; 674 sd.sd_MS = 0; 675 sd.sd_RDY = 0; 676 677 if (read_seeprom(&sd, (uint16_t *)buf, 0, len / 2) != 1) 678 return (1); 679 680 bus_space_unmap(t, bsh, 1); 681 682 return (0); 683 } 684
Indexes created Mon Sep 22 13:09:51 GMT 2025