hpc.c revision 1.55
1 /* $NetBSD: hpc.c,v 1.55 2007/02/20 23:49:20 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang 5 * Copyright (c) 2001 Rafal K. Boni 6 * Copyright (c) 2001 Jason R. Thorpe 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.55 2007/02/20 23:49:20 rumble Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/reboot.h> 45 #include <sys/callout.h> 46 47 #define _SGIMIPS_BUS_DMA_PRIVATE 48 #include <machine/bus.h> 49 #include <machine/machtype.h> 50 #include <machine/sysconf.h> 51 52 #include <sgimips/gio/gioreg.h> 53 #include <sgimips/gio/giovar.h> 54 55 #include <sgimips/hpc/hpcvar.h> 56 #include <sgimips/hpc/hpcreg.h> 57 #include <sgimips/ioc/iocreg.h> 58 59 #include <dev/ic/smc93cx6var.h> 60 61 #include "locators.h" 62 63 struct hpc_device { 64 const char *hd_name; 65 bus_addr_t hd_base; 66 bus_addr_t hd_devoff; 67 bus_addr_t hd_dmaoff; 68 int hd_irq; 69 int hd_sysmask; 70 }; 71 72 static const struct hpc_device hpc1_devices[] = { 73 /* probe order is important for IP20 zsc */ 74 75 { "zsc", /* Personal Iris/Indigo serial 0/1 duart 1 */ 76 HPC_BASE_ADDRESS_0, 77 0x0d10, 0, 78 5, 79 HPCDEV_IP12 | HPCDEV_IP20 }, 80 81 { "zsc", /* Personal Iris/Indigo kbd/ms duart 0 */ 82 HPC_BASE_ADDRESS_0, 83 0x0d00, 0, 84 5, 85 HPCDEV_IP12 | HPCDEV_IP20 }, 86 87 { "sq", /* Personal Iris/Indigo onboard ethernet */ 88 HPC_BASE_ADDRESS_0, 89 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 90 3, 91 HPCDEV_IP12 | HPCDEV_IP20 }, 92 93 { "sq", /* E++ GIO adapter slot 0 (Indigo) */ 94 HPC_BASE_ADDRESS_1, 95 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 96 6, 97 HPCDEV_IP12 | HPCDEV_IP20 }, 98 99 { "sq", /* E++ GIO adapter slot 0 (Indy) */ 100 HPC_BASE_ADDRESS_1, 101 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 102 22, 103 HPCDEV_IP24 }, 104 105 { "sq", /* E++ GIO adapter slot 1 (Indigo) */ 106 HPC_BASE_ADDRESS_2, 107 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 108 6, 109 HPCDEV_IP12 | HPCDEV_IP20 }, 110 111 { "sq", /* E++ GIO adapter slot 1 (Indy/Challenge S) */ 112 HPC_BASE_ADDRESS_2, 113 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 114 23, 115 HPCDEV_IP24 }, 116 117 { "wdsc", /* Personal Iris/Indigo onboard SCSI */ 118 HPC_BASE_ADDRESS_0, 119 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 120 2, /* XXX 1 = IRQ_LOCAL0 + 2 */ 121 HPCDEV_IP12 | HPCDEV_IP20 }, 122 123 { "wdsc", /* GIO32 SCSI adapter slot 0 (Indigo) */ 124 HPC_BASE_ADDRESS_1, 125 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 126 6, 127 HPCDEV_IP12 | HPCDEV_IP20 }, 128 129 { "wdsc", /* GIO32 SCSI adapter slot 0 (Indy) */ 130 HPC_BASE_ADDRESS_1, 131 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 132 22, 133 HPCDEV_IP24 }, 134 135 { "wdsc", /* GIO32 SCSI adapter slot 1 (Indigo) */ 136 HPC_BASE_ADDRESS_2, 137 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 138 6, 139 HPCDEV_IP12 | HPCDEV_IP20 }, 140 141 { "wdsc", /* GIO32 SCSI adapter slot 1 (Indy/Challenge S) */ 142 HPC_BASE_ADDRESS_2, 143 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 144 23, 145 HPCDEV_IP24 }, 146 147 { "dpclock", /* Personal Iris/Indigo clock */ 148 HPC_BASE_ADDRESS_0, 149 HPC1_PBUS_BBRAM, 0, 150 -1, 151 HPCDEV_IP12 | HPCDEV_IP20 }, 152 153 { NULL, 154 0, 155 0, 0, 156 0, 157 0 158 } 159 }; 160 161 static const struct hpc_device hpc3_devices[] = { 162 { "zsc", /* serial 0/1 duart 0 */ 163 HPC_BASE_ADDRESS_0, 164 /* XXX Magic numbers */ 165 HPC3_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0, 166 29, 167 HPCDEV_IP22 | HPCDEV_IP24 }, 168 169 { "pckbc", /* Indigo2/Indy ps2 keyboard/mouse controller */ 170 HPC_BASE_ADDRESS_0, 171 HPC3_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0, 172 28, 173 HPCDEV_IP22 | HPCDEV_IP24 }, 174 175 { "sq", /* Indigo2/Indy/Challenge S/Challenge M onboard enet */ 176 HPC_BASE_ADDRESS_0, 177 HPC3_ENET_DEVREGS, HPC3_ENET_REGS, 178 3, 179 HPCDEV_IP22 | HPCDEV_IP24 }, 180 181 { "sq", /* Challenge S IOPLUS secondary ethernet */ 182 HPC_BASE_ADDRESS_1, 183 HPC3_ENET_DEVREGS, HPC3_ENET_REGS, 184 0, 185 HPCDEV_IP24 }, 186 187 { "wdsc", /* Indigo2/Indy/Challenge S/Challenge M onboard SCSI */ 188 HPC_BASE_ADDRESS_0, 189 HPC3_SCSI0_DEVREGS, HPC3_SCSI0_REGS, 190 1, /* XXX 1 = IRQ_LOCAL0 + 1 */ 191 HPCDEV_IP22 | HPCDEV_IP24 }, 192 193 { "wdsc", /* Indigo2/Challenge M secondary onboard SCSI */ 194 HPC_BASE_ADDRESS_0, 195 HPC3_SCSI1_DEVREGS, HPC3_SCSI1_REGS, 196 2, /* XXX 2 = IRQ_LOCAL0 + 2 */ 197 HPCDEV_IP22 }, 198 199 { "dsclock", /* Indigo2/Indy/Challenge S/Challenge M clock */ 200 HPC_BASE_ADDRESS_0, 201 HPC3_PBUS_BBRAM, 0, 202 -1, 203 HPCDEV_IP22 | HPCDEV_IP24 }, 204 205 { "haltwo", /* Indigo2/Indy onboard audio */ 206 HPC_BASE_ADDRESS_0, 207 HPC3_PBUS_CH0_DEVREGS, HPC3_PBUS_DMAREGS, 208 8 + 4, /* XXX IRQ_LOCAL1 + 4 */ 209 HPCDEV_IP22 | HPCDEV_IP24 }, 210 211 { "pi1ppc", /* Indigo2/Indy/Challenge S/Challenge M onboard pport */ 212 HPC_BASE_ADDRESS_0, 213 HPC3_PBUS_CH6_DEVREGS + IOC_PLP_REGS, 0, 214 -1, 215 HPCDEV_IP22 | HPCDEV_IP24 }, 216 217 { NULL, 218 0, 219 0, 0, 220 0, 221 0 222 } 223 }; 224 225 struct hpc_softc { 226 struct device sc_dev; 227 228 bus_addr_t sc_base; 229 230 bus_space_tag_t sc_ct; 231 bus_space_handle_t sc_ch; 232 }; 233 234 static struct hpc_values hpc1_values = { 235 .revision = 1, 236 .scsi0_regs = HPC1_SCSI0_REGS, 237 .scsi0_regs_size = HPC1_SCSI0_REGS_SIZE, 238 .scsi0_cbp = HPC1_SCSI0_CBP, 239 .scsi0_ndbp = HPC1_SCSI0_NDBP, 240 .scsi0_bc = HPC1_SCSI0_BC, 241 .scsi0_ctl = HPC1_SCSI0_CTL, 242 .scsi0_gio = HPC1_SCSI0_GIO, 243 .scsi0_dev = HPC1_SCSI0_DEV, 244 .scsi0_dmacfg = HPC1_SCSI0_DMACFG, 245 .scsi0_piocfg = HPC1_SCSI0_PIOCFG, 246 .scsi1_regs = 0, 247 .scsi1_regs_size = 0, 248 .scsi1_cbp = 0, 249 .scsi1_ndbp = 0, 250 .scsi1_bc = 0, 251 .scsi1_ctl = 0, 252 .scsi1_gio = 0, 253 .scsi1_dev = 0, 254 .scsi1_dmacfg = 0, 255 .scsi1_piocfg = 0, 256 .enet_regs = HPC1_ENET_REGS, 257 .enet_regs_size = HPC1_ENET_REGS_SIZE, 258 .enet_intdelay = HPC1_ENET_INTDELAY, 259 .enet_intdelayval = HPC1_ENET_INTDELAY_OFF, 260 .enetr_cbp = HPC1_ENETR_CBP, 261 .enetr_ndbp = HPC1_ENETR_NDBP, 262 .enetr_bc = HPC1_ENETR_BC, 263 .enetr_ctl = HPC1_ENETR_CTL, 264 .enetr_ctl_active = HPC1_ENETR_CTL_ACTIVE, 265 .enetr_reset = HPC1_ENETR_RESET, 266 .enetr_dmacfg = 0, 267 .enetr_piocfg = 0, 268 .enetx_cbp = HPC1_ENETX_CBP, 269 .enetx_ndbp = HPC1_ENETX_NDBP, 270 .enetx_bc = HPC1_ENETX_BC, 271 .enetx_ctl = HPC1_ENETX_CTL, 272 .enetx_ctl_active = HPC1_ENETX_CTL_ACTIVE, 273 .enetx_dev = 0, 274 .enetr_fifo = HPC1_ENETR_FIFO, 275 .enetr_fifo_size = HPC1_ENETR_FIFO_SIZE, 276 .enetx_fifo = HPC1_ENETX_FIFO, 277 .enetx_fifo_size = HPC1_ENETX_FIFO_SIZE, 278 .scsi0_devregs_size = HPC1_SCSI0_DEVREGS_SIZE, 279 .scsi1_devregs_size = 0, 280 .enet_devregs = HPC1_ENET_DEVREGS, 281 .enet_devregs_size = HPC1_ENET_DEVREGS_SIZE, 282 .pbus_fifo = 0, 283 .pbus_fifo_size = 0, 284 .pbus_bbram = 0, 285 #define MAX_SCSI_XFER (512*1024) 286 .scsi_max_xfer = MAX_SCSI_XFER, 287 .scsi_dma_segs = (MAX_SCSI_XFER / 4096), 288 .scsi_dma_segs_size = 4096, 289 .scsi_dma_datain_cmd = (HPC1_SCSI_DMACTL_ACTIVE | HPC1_SCSI_DMACTL_DIR), 290 .scsi_dma_dataout_cmd = HPC1_SCSI_DMACTL_ACTIVE, 291 .scsi_dmactl_flush = HPC1_SCSI_DMACTL_FLUSH, 292 .scsi_dmactl_active = HPC1_SCSI_DMACTL_ACTIVE, 293 .scsi_dmactl_reset = HPC1_SCSI_DMACTL_RESET 294 }; 295 296 static struct hpc_values hpc3_values = { 297 .revision = 3, 298 .scsi0_regs = HPC3_SCSI0_REGS, 299 .scsi0_regs_size = HPC3_SCSI0_REGS_SIZE, 300 .scsi0_cbp = HPC3_SCSI0_CBP, 301 .scsi0_ndbp = HPC3_SCSI0_NDBP, 302 .scsi0_bc = HPC3_SCSI0_BC, 303 .scsi0_ctl = HPC3_SCSI0_CTL, 304 .scsi0_gio = HPC3_SCSI0_GIO, 305 .scsi0_dev = HPC3_SCSI0_DEV, 306 .scsi0_dmacfg = HPC3_SCSI0_DMACFG, 307 .scsi0_piocfg = HPC3_SCSI0_PIOCFG, 308 .scsi1_regs = HPC3_SCSI1_REGS, 309 .scsi1_regs_size = HPC3_SCSI1_REGS_SIZE, 310 .scsi1_cbp = HPC3_SCSI1_CBP, 311 .scsi1_ndbp = HPC3_SCSI1_NDBP, 312 .scsi1_bc = HPC3_SCSI1_BC, 313 .scsi1_ctl = HPC3_SCSI1_CTL, 314 .scsi1_gio = HPC3_SCSI1_GIO, 315 .scsi1_dev = HPC3_SCSI1_DEV, 316 .scsi1_dmacfg = HPC3_SCSI1_DMACFG, 317 .scsi1_piocfg = HPC3_SCSI1_PIOCFG, 318 .enet_regs = HPC3_ENET_REGS, 319 .enet_regs_size = HPC3_ENET_REGS_SIZE, 320 .enet_intdelay = 0, 321 .enet_intdelayval = 0, 322 .enetr_cbp = HPC3_ENETR_CBP, 323 .enetr_ndbp = HPC3_ENETR_NDBP, 324 .enetr_bc = HPC3_ENETR_BC, 325 .enetr_ctl = HPC3_ENETR_CTL, 326 .enetr_ctl_active = HPC3_ENETR_CTL_ACTIVE, 327 .enetr_reset = HPC3_ENETR_RESET, 328 .enetr_dmacfg = HPC3_ENETR_DMACFG, 329 .enetr_piocfg = HPC3_ENETR_PIOCFG, 330 .enetx_cbp = HPC3_ENETX_CBP, 331 .enetx_ndbp = HPC3_ENETX_NDBP, 332 .enetx_bc = HPC3_ENETX_BC, 333 .enetx_ctl = HPC3_ENETX_CTL, 334 .enetx_ctl_active = HPC3_ENETX_CTL_ACTIVE, 335 .enetx_dev = HPC3_ENETX_DEV, 336 .enetr_fifo = HPC3_ENETR_FIFO, 337 .enetr_fifo_size = HPC3_ENETR_FIFO_SIZE, 338 .enetx_fifo = HPC3_ENETX_FIFO, 339 .enetx_fifo_size = HPC3_ENETX_FIFO_SIZE, 340 .scsi0_devregs_size = HPC3_SCSI0_DEVREGS_SIZE, 341 .scsi1_devregs_size = HPC3_SCSI1_DEVREGS_SIZE, 342 .enet_devregs = HPC3_ENET_DEVREGS, 343 .enet_devregs_size = HPC3_ENET_DEVREGS_SIZE, 344 .pbus_fifo = HPC3_PBUS_FIFO, 345 .pbus_fifo_size = HPC3_PBUS_FIFO_SIZE, 346 .pbus_bbram = HPC3_PBUS_BBRAM, 347 .scsi_max_xfer = MAX_SCSI_XFER, 348 .scsi_dma_segs = (MAX_SCSI_XFER / 8192), 349 .scsi_dma_segs_size = 8192, 350 .scsi_dma_datain_cmd = HPC3_SCSI_DMACTL_ACTIVE, 351 .scsi_dma_dataout_cmd =(HPC3_SCSI_DMACTL_ACTIVE | HPC3_SCSI_DMACTL_DIR), 352 .scsi_dmactl_flush = HPC3_SCSI_DMACTL_FLUSH, 353 .scsi_dmactl_active = HPC3_SCSI_DMACTL_ACTIVE, 354 .scsi_dmactl_reset = HPC3_SCSI_DMACTL_RESET 355 }; 356 357 358 static int powerintr_established; 359 360 static int hpc_match(struct device *, struct cfdata *, void *); 361 static void hpc_attach(struct device *, struct device *, void *); 362 static int hpc_print(void *, const char *); 363 364 static int hpc_revision(struct hpc_softc *, struct gio_attach_args *); 365 366 static int hpc_submatch(struct device *, struct cfdata *, 367 const int *, void *); 368 369 static int hpc_power_intr(void *); 370 371 #if defined(BLINK) 372 static struct callout hpc_blink_ch = CALLOUT_INITIALIZER; 373 static void hpc_blink(void *); 374 #endif 375 376 static int hpc_read_eeprom(int, bus_space_tag_t, bus_space_handle_t, 377 uint8_t *, size_t); 378 379 CFATTACH_DECL(hpc, sizeof(struct hpc_softc), 380 hpc_match, hpc_attach, NULL, NULL); 381 382 static int 383 hpc_match(struct device *parent, struct cfdata *cf, void *aux) 384 { 385 struct gio_attach_args* ga = aux; 386 387 /* Make sure it's actually there and readable */ 388 if (platform.badaddr((void*)MIPS_PHYS_TO_KSEG1(ga->ga_addr), 389 sizeof(u_int32_t))) 390 return 0; 391 392 return 1; 393 } 394 395 static void 396 hpc_attach(struct device *parent, struct device *self, void *aux) 397 { 398 struct hpc_softc *sc = (struct hpc_softc *)self; 399 struct gio_attach_args* ga = aux; 400 struct hpc_attach_args ha; 401 const struct hpc_device *hd; 402 uint32_t hpctype; 403 int isonboard; 404 int isioplus; 405 int sysmask; 406 407 switch (mach_type) { 408 case MACH_SGI_IP12: 409 sysmask = HPCDEV_IP12; 410 break; 411 412 case MACH_SGI_IP20: 413 sysmask = HPCDEV_IP20; 414 break; 415 416 case MACH_SGI_IP22: 417 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 418 sysmask = HPCDEV_IP22; 419 else 420 sysmask = HPCDEV_IP24; 421 break; 422 423 default: 424 panic("hpc_attach: can't handle HPC on an IP%d", mach_type); 425 }; 426 427 if ((hpctype = hpc_revision(sc, ga)) == 0) 428 panic("hpc_attach: could not identify HPC revision\n"); 429 430 /* force big-endian mode */ 431 if (hpctype == 15) 432 *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr+HPC1_BIGENDIAN) = 0; 433 434 /* 435 * All machines have only one HPC on the mainboard itself. ''Extra'' 436 * HPCs require bus arbiter and other magic to run happily. 437 */ 438 isonboard = (ga->ga_addr == HPC_BASE_ADDRESS_0); 439 isioplus = (ga->ga_addr == HPC_BASE_ADDRESS_1 && hpctype == 3 && 440 sysmask == HPCDEV_IP24); 441 442 printf(": SGI HPC%d%s (%s)\n", (hpctype == 3) ? 3 : 1, 443 (hpctype == 15) ? ".5" : "", (isonboard) ? "onboard" : 444 (isioplus) ? "IOPLUS mezzanine" : "GIO slot"); 445 446 /* 447 * Configure the bus arbiter appropriately. 448 * 449 * In the case of Challenge S, we must tell the IOPLUS board which 450 * DMA channel to use (we steal it from one of the slots). SGI permits 451 * an HPC1.5 in slot 1, in which case IOPLUS must use EXP0, or any 452 * other DMA-capable board in slot 0, which leaves us to use EXP1. Of 453 * course, this means that only one GIO board may use DMA. 454 * 455 * Note that this never happens on Indigo2. 456 */ 457 if (isioplus) { 458 int arb_slot; 459 460 if (platform.badaddr( 461 (void *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_2), 4)) 462 arb_slot = GIO_SLOT_EXP1; 463 else 464 arb_slot = GIO_SLOT_EXP0; 465 466 if (gio_arb_config(arb_slot, GIO_ARB_LB | GIO_ARB_MST | 467 GIO_ARB_64BIT | GIO_ARB_HPC2_64BIT)) { 468 printf("%s: failed to configure GIO bus arbiter\n", 469 sc->sc_dev.dv_xname); 470 return; 471 } 472 473 printf("%s: using EXP%d's DMA channel\n", sc->sc_dev.dv_xname, 474 (arb_slot == GIO_SLOT_EXP0) ? 0 : 1); 475 476 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 477 HPC3_PBUS_CFGPIO_REGS, 0x0003ffff); 478 479 if (arb_slot == GIO_SLOT_EXP0) 480 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 481 HPC3_PBUS_CH0_DEVREGS, 0x20202020); 482 else 483 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 484 HPC3_PBUS_CH0_DEVREGS, 0x30303030); 485 } else if (!isonboard) { 486 int arb_slot; 487 488 arb_slot = (ga->ga_addr == HPC_BASE_ADDRESS_1) ? 489 GIO_SLOT_EXP0 : GIO_SLOT_EXP1; 490 491 if (gio_arb_config(arb_slot, GIO_ARB_RT | GIO_ARB_MST)) { 492 printf("%s: failed to configure GIO bus arbiter\n", 493 sc->sc_dev.dv_xname); 494 return; 495 } 496 } 497 498 sc->sc_ct = SGIMIPS_BUS_SPACE_HPC; 499 sc->sc_ch = ga->ga_ioh; 500 501 sc->sc_base = ga->ga_addr; 502 503 hpc_read_eeprom(hpctype, SGIMIPS_BUS_SPACE_HPC, 504 MIPS_PHYS_TO_KSEG1(sc->sc_base), ha.hpc_eeprom, 505 sizeof(ha.hpc_eeprom)); 506 507 hd = (hpctype == 3) ? hpc3_devices : hpc1_devices; 508 for (; hd->hd_name != NULL; hd++) { 509 if (!(hd->hd_sysmask & sysmask) || hd->hd_base != sc->sc_base) 510 continue; 511 512 ha.ha_name = hd->hd_name; 513 ha.ha_devoff = hd->hd_devoff; 514 ha.ha_dmaoff = hd->hd_dmaoff; 515 ha.ha_irq = hd->hd_irq; 516 517 /* XXX This is disgusting. */ 518 ha.ha_st = SGIMIPS_BUS_SPACE_HPC; 519 ha.ha_sh = MIPS_PHYS_TO_KSEG1(sc->sc_base); 520 ha.ha_dmat = &sgimips_default_bus_dma_tag; 521 if (hpctype == 3) 522 ha.hpc_regs = &hpc3_values; 523 else 524 ha.hpc_regs = &hpc1_values; 525 ha.hpc_regs->revision = hpctype; 526 527 /* XXXgross! avoid complaining in E++ and GIO32 SCSI cases */ 528 if (hpctype != 3 && sc->sc_base != HPC_BASE_ADDRESS_0) { 529 (void)config_found_sm_loc(self, "hpc", NULL, &ha, 530 NULL, hpc_submatch); 531 } else { 532 (void)config_found_sm_loc(self, "hpc", NULL, &ha, 533 hpc_print, hpc_submatch); 534 } 535 } 536 537 /* 538 * XXX: Only attach the powerfail interrupt once, since the 539 * interrupt code doesn't let you share interrupt just yet. 540 * 541 * Since the powerfail interrupt is hardcoded to read from 542 * a specific register anyway (XXX#2!), we don't care when 543 * it gets attached, as long as it only happens once. 544 */ 545 if (mach_type == MACH_SGI_IP22 && !powerintr_established) { 546 cpu_intr_establish(9, IPL_NONE, hpc_power_intr, sc); 547 powerintr_established++; 548 } 549 550 #if defined(BLINK) 551 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) 552 hpc_blink(sc); 553 #endif 554 } 555 556 /* 557 * HPC revision detection isn't as simple as it should be. Devices probe 558 * differently depending on their slots, but luckily there is only one 559 * instance in which we have to decide the major revision (HPC1 vs HPC3). 560 * 561 * The HPC is found in the following configurations: 562 * o Personal Iris 4D/3x: 563 * One on-board HPC1 or HPC1.5. 564 * 565 * o Indigo R3k/R4k: 566 * One on-board HPC1 or HPC1.5. 567 * Up to two additional HPC1.5's in GIO slots 0 and 1. 568 * 569 * o Indy: 570 * One on-board HPC3. 571 * Up to two additional HPC1.5's in GIO slots 0 and 1. 572 * 573 * o Challenge S 574 * One on-board HPC3. 575 * Up to one additional HPC3 on the IOPLUS board (if installed). 576 * Up to one additional HPC1.5 in slot 1 of the IOPLUS board. 577 * 578 * o Indigo2, Challenge M 579 * One on-board HPC3. 580 * 581 * All we really have to worry about is the IP22 case. 582 */ 583 static int 584 hpc_revision(struct hpc_softc *sc, struct gio_attach_args *ga) 585 { 586 587 /* No hardware ever supported the last hpc base address. */ 588 if (ga->ga_addr == HPC_BASE_ADDRESS_3) 589 return (0); 590 591 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) { 592 u_int32_t reg; 593 594 if (!platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 595 HPC1_BIGENDIAN), 4)) { 596 reg = *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 597 HPC1_BIGENDIAN); 598 599 if (((reg >> HPC1_REVSHIFT) & HPC1_REVMASK) == 600 HPC1_REV15) 601 return (15); 602 else 603 return (1); 604 } 605 606 return (1); 607 } 608 609 /* 610 * If IP22, probe slot 0 to determine if HPC1.5 or HPC3. Slot 1 must 611 * be HPC1.5. 612 */ 613 if (mach_type == MACH_SGI_IP22) { 614 if (ga->ga_addr == HPC_BASE_ADDRESS_0) 615 return (3); 616 617 if (ga->ga_addr == HPC_BASE_ADDRESS_2) 618 return (15); 619 620 /* 621 * Probe for it. We use one of the PBUS registers. Note 622 * that this probe succeeds with my E++ adapter in slot 1 623 * (bad), but it appears to always do the right thing in 624 * slot 0 (good!) and we're only worried about that one 625 * anyhow. 626 */ 627 if (platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 628 HPC3_PBUS_CH7_BP), 4)) 629 return (15); 630 else 631 return (3); 632 } 633 634 return (0); 635 } 636 637 static int 638 hpc_submatch(struct device *parent, struct cfdata *cf, 639 const int *ldesc, void *aux) 640 { 641 struct hpc_attach_args *ha = aux; 642 643 if (cf->cf_loc[HPCCF_OFFSET] != HPCCF_OFFSET_DEFAULT && 644 (bus_addr_t) cf->cf_loc[HPCCF_OFFSET] != ha->ha_devoff) 645 return (0); 646 647 return (config_match(parent, cf, aux)); 648 } 649 650 static int 651 hpc_print(void *aux, const char *pnp) 652 { 653 struct hpc_attach_args *ha = aux; 654 655 if (pnp) 656 printf("%s at %s", ha->ha_name, pnp); 657 658 printf(" offset 0x%lx", ha->ha_devoff); 659 660 return (UNCONF); 661 } 662 663 static int 664 hpc_power_intr(void *arg) 665 { 666 u_int32_t pwr_reg; 667 668 pwr_reg = *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)); 669 *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)) = pwr_reg; 670 671 printf("hpc_power_intr: panel reg = %08x\n", pwr_reg); 672 673 if (pwr_reg & 2) 674 cpu_reboot(RB_HALT, NULL); 675 676 return 1; 677 } 678 679 #if defined(BLINK) 680 static void 681 hpc_blink(void *self) 682 { 683 struct hpc_softc *sc = (struct hpc_softc *) self; 684 register int s; 685 int value; 686 687 s = splhigh(); 688 689 value = *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + 690 HPC1_AUX_REGS); 691 value ^= HPC1_AUX_CONSLED; 692 *(volatile u_int8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + 693 HPC1_AUX_REGS) = value; 694 splx(s); 695 696 /* 697 * Blink rate is: 698 * full cycle every second if completely idle (loadav = 0) 699 * full cycle every 2 seconds if loadav = 1 700 * full cycle every 3 seconds if loadav = 2 701 * etc. 702 */ 703 s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); 704 callout_reset(&hpc_blink_ch, s, hpc_blink, sc); 705 } 706 #endif 707 708 /* 709 * Read the eeprom associated with one of the HPC's. 710 * 711 * NB: An eeprom is not always present, but the HPC should be able to 712 * handle this gracefully. Any consumers should validate the data to 713 * ensure it's reasonable. 714 */ 715 static int 716 hpc_read_eeprom(int hpctype, bus_space_tag_t t, bus_space_handle_t h, 717 uint8_t *buf, size_t len) 718 { 719 struct seeprom_descriptor sd; 720 bus_space_handle_t bsh; 721 bus_space_tag_t tag; 722 bus_size_t offset; 723 724 if (!len || len & 0x1) 725 return (1); 726 727 offset = (hpctype == 3) ? HPC3_EEPROM_DATA : HPC1_AUX_REGS; 728 729 tag = SGIMIPS_BUS_SPACE_NORMAL; 730 if (bus_space_subregion(t, h, offset, 1, &bsh) != 0) 731 return (1); 732 733 sd.sd_chip = C56_66; 734 sd.sd_tag = tag; 735 sd.sd_bsh = bsh; 736 sd.sd_regsize = 1; 737 sd.sd_control_offset = 0; 738 sd.sd_status_offset = 0; 739 sd.sd_dataout_offset = 0; 740 sd.sd_DI = 0x10; /* EEPROM -> CPU */ 741 sd.sd_DO = 0x08; /* CPU -> EEPROM */ 742 sd.sd_CK = 0x04; 743 sd.sd_CS = 0x02; 744 sd.sd_MS = 0; 745 sd.sd_RDY = 0; 746 747 if (read_seeprom(&sd, (uint16_t *)buf, 0, len / 2) != 1) 748 return (1); 749 750 bus_space_unmap(t, bsh, 1); 751 752 return (0); 753 } 754
Indexes created Mon Sep 22 05:09:51 GMT 2025