hpc.c revision 1.61
1 /* $NetBSD: hpc.c,v 1.61 2009/02/12 06:33:57 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang 5 * Copyright (c) 2001 Rafal K. Boni 6 * Copyright (c) 2001 Jason R. Thorpe 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.61 2009/02/12 06:33:57 rumble Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/reboot.h> 45 #include <sys/callout.h> 46 47 #define _SGIMIPS_BUS_DMA_PRIVATE 48 #include <machine/bus.h> 49 #include <machine/machtype.h> 50 #include <machine/sysconf.h> 51 52 #include <sgimips/gio/gioreg.h> 53 #include <sgimips/gio/giovar.h> 54 55 #include <sgimips/hpc/hpcvar.h> 56 #include <sgimips/hpc/hpcreg.h> 57 #include <sgimips/ioc/iocreg.h> 58 59 #include <dev/ic/smc93cx6var.h> 60 61 #include "locators.h" 62 63 struct hpc_device { 64 const char *hd_name; 65 bus_addr_t hd_base; 66 bus_addr_t hd_devoff; 67 bus_addr_t hd_dmaoff; 68 int hd_irq; 69 int hd_sysmask; 70 }; 71 72 static const struct hpc_device hpc1_devices[] = { 73 /* probe order is important for IP20 zsc */ 74 75 { "zsc", /* Personal Iris/Indigo serial 0/1 duart 1 */ 76 HPC_BASE_ADDRESS_0, 77 0x0d10, 0, 78 5, 79 HPCDEV_IP12 | HPCDEV_IP20 }, 80 81 { "zsc", /* Personal Iris/Indigo kbd/ms duart 0 */ 82 HPC_BASE_ADDRESS_0, 83 0x0d00, 0, 84 5, 85 HPCDEV_IP12 | HPCDEV_IP20 }, 86 87 { "sq", /* Personal Iris/Indigo onboard ethernet */ 88 HPC_BASE_ADDRESS_0, 89 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 90 3, 91 HPCDEV_IP12 | HPCDEV_IP20 }, 92 93 { "sq", /* E++ GIO adapter slot 0 (Indigo) */ 94 HPC_BASE_ADDRESS_1, 95 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 96 6, 97 HPCDEV_IP12 | HPCDEV_IP20 }, 98 99 { "sq", /* E++ GIO adapter slot 0 (Indy) */ 100 HPC_BASE_ADDRESS_1, 101 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 102 22, 103 HPCDEV_IP24 }, 104 105 { "sq", /* E++ GIO adapter slot 1 (Indigo) */ 106 HPC_BASE_ADDRESS_2, 107 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 108 6, 109 HPCDEV_IP12 | HPCDEV_IP20 }, 110 111 { "sq", /* E++ GIO adapter slot 1 (Indy/Challenge S) */ 112 HPC_BASE_ADDRESS_2, 113 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 114 23, 115 HPCDEV_IP24 }, 116 117 { "wdsc", /* Personal Iris/Indigo onboard SCSI */ 118 HPC_BASE_ADDRESS_0, 119 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 120 2, /* XXX 1 = IRQ_LOCAL0 + 2 */ 121 HPCDEV_IP12 | HPCDEV_IP20 }, 122 123 { "wdsc", /* GIO32 SCSI adapter slot 0 (Indigo) */ 124 HPC_BASE_ADDRESS_1, 125 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 126 6, 127 HPCDEV_IP12 | HPCDEV_IP20 }, 128 129 { "wdsc", /* GIO32 SCSI adapter slot 0 (Indy) */ 130 HPC_BASE_ADDRESS_1, 131 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 132 22, 133 HPCDEV_IP24 }, 134 135 { "wdsc", /* GIO32 SCSI adapter slot 1 (Indigo) */ 136 HPC_BASE_ADDRESS_2, 137 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 138 6, 139 HPCDEV_IP12 | HPCDEV_IP20 }, 140 141 { "wdsc", /* GIO32 SCSI adapter slot 1 (Indy/Challenge S) */ 142 HPC_BASE_ADDRESS_2, 143 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 144 23, 145 HPCDEV_IP24 }, 146 147 { NULL, 148 0, 149 0, 0, 150 0, 151 0 152 } 153 }; 154 155 static const struct hpc_device hpc3_devices[] = { 156 { "zsc", /* serial 0/1 duart 0 */ 157 HPC_BASE_ADDRESS_0, 158 /* XXX Magic numbers */ 159 HPC3_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0, 160 29, 161 HPCDEV_IP22 | HPCDEV_IP24 }, 162 163 { "pckbc", /* Indigo2/Indy ps2 keyboard/mouse controller */ 164 HPC_BASE_ADDRESS_0, 165 HPC3_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0, 166 28, 167 HPCDEV_IP22 | HPCDEV_IP24 }, 168 169 { "sq", /* Indigo2/Indy/Challenge S/Challenge M onboard enet */ 170 HPC_BASE_ADDRESS_0, 171 HPC3_ENET_DEVREGS, HPC3_ENET_REGS, 172 3, 173 HPCDEV_IP22 | HPCDEV_IP24 }, 174 175 { "sq", /* Challenge S IOPLUS secondary ethernet */ 176 HPC_BASE_ADDRESS_1, 177 HPC3_ENET_DEVREGS, HPC3_ENET_REGS, 178 0, 179 HPCDEV_IP24 }, 180 181 { "wdsc", /* Indigo2/Indy/Challenge S/Challenge M onboard SCSI */ 182 HPC_BASE_ADDRESS_0, 183 HPC3_SCSI0_DEVREGS, HPC3_SCSI0_REGS, 184 1, /* XXX 1 = IRQ_LOCAL0 + 1 */ 185 HPCDEV_IP22 | HPCDEV_IP24 }, 186 187 { "wdsc", /* Indigo2/Challenge M secondary onboard SCSI */ 188 HPC_BASE_ADDRESS_0, 189 HPC3_SCSI1_DEVREGS, HPC3_SCSI1_REGS, 190 2, /* XXX 2 = IRQ_LOCAL0 + 2 */ 191 HPCDEV_IP22 }, 192 193 { "haltwo", /* Indigo2/Indy onboard audio */ 194 HPC_BASE_ADDRESS_0, 195 HPC3_PBUS_CH0_DEVREGS, HPC3_PBUS_DMAREGS, 196 8 + 4, /* XXX IRQ_LOCAL1 + 4 */ 197 HPCDEV_IP22 | HPCDEV_IP24 }, 198 199 { "pi1ppc", /* Indigo2/Indy/Challenge S/Challenge M onboard pport */ 200 HPC_BASE_ADDRESS_0, 201 HPC3_PBUS_CH6_DEVREGS + IOC_PLP_REGS, 0, 202 -1, 203 HPCDEV_IP22 | HPCDEV_IP24 }, 204 205 { NULL, 206 0, 207 0, 0, 208 0, 209 0 210 } 211 }; 212 213 struct hpc_softc { 214 struct device sc_dev; 215 216 bus_addr_t sc_base; 217 218 bus_space_tag_t sc_ct; 219 bus_space_handle_t sc_ch; 220 }; 221 222 static struct hpc_values hpc1_values = { 223 .revision = 1, 224 .scsi0_regs = HPC1_SCSI0_REGS, 225 .scsi0_regs_size = HPC1_SCSI0_REGS_SIZE, 226 .scsi0_cbp = HPC1_SCSI0_CBP, 227 .scsi0_ndbp = HPC1_SCSI0_NDBP, 228 .scsi0_bc = HPC1_SCSI0_BC, 229 .scsi0_ctl = HPC1_SCSI0_CTL, 230 .scsi0_gio = HPC1_SCSI0_GIO, 231 .scsi0_dev = HPC1_SCSI0_DEV, 232 .scsi0_dmacfg = HPC1_SCSI0_DMACFG, 233 .scsi0_piocfg = HPC1_SCSI0_PIOCFG, 234 .scsi1_regs = 0, 235 .scsi1_regs_size = 0, 236 .scsi1_cbp = 0, 237 .scsi1_ndbp = 0, 238 .scsi1_bc = 0, 239 .scsi1_ctl = 0, 240 .scsi1_gio = 0, 241 .scsi1_dev = 0, 242 .scsi1_dmacfg = 0, 243 .scsi1_piocfg = 0, 244 .enet_regs = HPC1_ENET_REGS, 245 .enet_regs_size = HPC1_ENET_REGS_SIZE, 246 .enet_intdelay = HPC1_ENET_INTDELAY, 247 .enet_intdelayval = HPC1_ENET_INTDELAY_OFF, 248 .enetr_cbp = HPC1_ENETR_CBP, 249 .enetr_ndbp = HPC1_ENETR_NDBP, 250 .enetr_bc = HPC1_ENETR_BC, 251 .enetr_ctl = HPC1_ENETR_CTL, 252 .enetr_ctl_active = HPC1_ENETR_CTL_ACTIVE, 253 .enetr_reset = HPC1_ENETR_RESET, 254 .enetr_dmacfg = 0, 255 .enetr_piocfg = 0, 256 .enetx_cbp = HPC1_ENETX_CBP, 257 .enetx_ndbp = HPC1_ENETX_NDBP, 258 .enetx_bc = HPC1_ENETX_BC, 259 .enetx_ctl = HPC1_ENETX_CTL, 260 .enetx_ctl_active = HPC1_ENETX_CTL_ACTIVE, 261 .enetx_dev = 0, 262 .enetr_fifo = HPC1_ENETR_FIFO, 263 .enetr_fifo_size = HPC1_ENETR_FIFO_SIZE, 264 .enetx_fifo = HPC1_ENETX_FIFO, 265 .enetx_fifo_size = HPC1_ENETX_FIFO_SIZE, 266 .scsi0_devregs_size = HPC1_SCSI0_DEVREGS_SIZE, 267 .scsi1_devregs_size = 0, 268 .enet_devregs = HPC1_ENET_DEVREGS, 269 .enet_devregs_size = HPC1_ENET_DEVREGS_SIZE, 270 .pbus_fifo = 0, 271 .pbus_fifo_size = 0, 272 .pbus_bbram = 0, 273 #define MAX_SCSI_XFER (512*1024) 274 .scsi_max_xfer = MAX_SCSI_XFER, 275 .scsi_dma_segs = (MAX_SCSI_XFER / 4096), 276 .scsi_dma_segs_size = 4096, 277 .scsi_dma_datain_cmd = (HPC1_SCSI_DMACTL_ACTIVE | HPC1_SCSI_DMACTL_DIR), 278 .scsi_dma_dataout_cmd = HPC1_SCSI_DMACTL_ACTIVE, 279 .scsi_dmactl_flush = HPC1_SCSI_DMACTL_FLUSH, 280 .scsi_dmactl_active = HPC1_SCSI_DMACTL_ACTIVE, 281 .scsi_dmactl_reset = HPC1_SCSI_DMACTL_RESET 282 }; 283 284 static struct hpc_values hpc3_values = { 285 .revision = 3, 286 .scsi0_regs = HPC3_SCSI0_REGS, 287 .scsi0_regs_size = HPC3_SCSI0_REGS_SIZE, 288 .scsi0_cbp = HPC3_SCSI0_CBP, 289 .scsi0_ndbp = HPC3_SCSI0_NDBP, 290 .scsi0_bc = HPC3_SCSI0_BC, 291 .scsi0_ctl = HPC3_SCSI0_CTL, 292 .scsi0_gio = HPC3_SCSI0_GIO, 293 .scsi0_dev = HPC3_SCSI0_DEV, 294 .scsi0_dmacfg = HPC3_SCSI0_DMACFG, 295 .scsi0_piocfg = HPC3_SCSI0_PIOCFG, 296 .scsi1_regs = HPC3_SCSI1_REGS, 297 .scsi1_regs_size = HPC3_SCSI1_REGS_SIZE, 298 .scsi1_cbp = HPC3_SCSI1_CBP, 299 .scsi1_ndbp = HPC3_SCSI1_NDBP, 300 .scsi1_bc = HPC3_SCSI1_BC, 301 .scsi1_ctl = HPC3_SCSI1_CTL, 302 .scsi1_gio = HPC3_SCSI1_GIO, 303 .scsi1_dev = HPC3_SCSI1_DEV, 304 .scsi1_dmacfg = HPC3_SCSI1_DMACFG, 305 .scsi1_piocfg = HPC3_SCSI1_PIOCFG, 306 .enet_regs = HPC3_ENET_REGS, 307 .enet_regs_size = HPC3_ENET_REGS_SIZE, 308 .enet_intdelay = 0, 309 .enet_intdelayval = 0, 310 .enetr_cbp = HPC3_ENETR_CBP, 311 .enetr_ndbp = HPC3_ENETR_NDBP, 312 .enetr_bc = HPC3_ENETR_BC, 313 .enetr_ctl = HPC3_ENETR_CTL, 314 .enetr_ctl_active = HPC3_ENETR_CTL_ACTIVE, 315 .enetr_reset = HPC3_ENETR_RESET, 316 .enetr_dmacfg = HPC3_ENETR_DMACFG, 317 .enetr_piocfg = HPC3_ENETR_PIOCFG, 318 .enetx_cbp = HPC3_ENETX_CBP, 319 .enetx_ndbp = HPC3_ENETX_NDBP, 320 .enetx_bc = HPC3_ENETX_BC, 321 .enetx_ctl = HPC3_ENETX_CTL, 322 .enetx_ctl_active = HPC3_ENETX_CTL_ACTIVE, 323 .enetx_dev = HPC3_ENETX_DEV, 324 .enetr_fifo = HPC3_ENETR_FIFO, 325 .enetr_fifo_size = HPC3_ENETR_FIFO_SIZE, 326 .enetx_fifo = HPC3_ENETX_FIFO, 327 .enetx_fifo_size = HPC3_ENETX_FIFO_SIZE, 328 .scsi0_devregs_size = HPC3_SCSI0_DEVREGS_SIZE, 329 .scsi1_devregs_size = HPC3_SCSI1_DEVREGS_SIZE, 330 .enet_devregs = HPC3_ENET_DEVREGS, 331 .enet_devregs_size = HPC3_ENET_DEVREGS_SIZE, 332 .pbus_fifo = HPC3_PBUS_FIFO, 333 .pbus_fifo_size = HPC3_PBUS_FIFO_SIZE, 334 .pbus_bbram = HPC3_PBUS_BBRAM, 335 .scsi_max_xfer = MAX_SCSI_XFER, 336 .scsi_dma_segs = (MAX_SCSI_XFER / 8192), 337 .scsi_dma_segs_size = 8192, 338 .scsi_dma_datain_cmd = HPC3_SCSI_DMACTL_ACTIVE, 339 .scsi_dma_dataout_cmd =(HPC3_SCSI_DMACTL_ACTIVE | HPC3_SCSI_DMACTL_DIR), 340 .scsi_dmactl_flush = HPC3_SCSI_DMACTL_FLUSH, 341 .scsi_dmactl_active = HPC3_SCSI_DMACTL_ACTIVE, 342 .scsi_dmactl_reset = HPC3_SCSI_DMACTL_RESET 343 }; 344 345 346 static int powerintr_established; 347 348 static int hpc_match(struct device *, struct cfdata *, void *); 349 static void hpc_attach(struct device *, struct device *, void *); 350 static int hpc_print(void *, const char *); 351 352 static int hpc_revision(struct hpc_softc *, struct gio_attach_args *); 353 354 static int hpc_submatch(struct device *, struct cfdata *, 355 const int *, void *); 356 357 //static int hpc_power_intr(void *); 358 359 #if defined(BLINK) 360 static callout_t hpc_blink_ch; 361 static void hpc_blink(void *); 362 #endif 363 364 static int hpc_read_eeprom(int, bus_space_tag_t, bus_space_handle_t, 365 uint8_t *, size_t); 366 367 CFATTACH_DECL(hpc, sizeof(struct hpc_softc), 368 hpc_match, hpc_attach, NULL, NULL); 369 370 static int 371 hpc_match(struct device *parent, struct cfdata *cf, void *aux) 372 { 373 struct gio_attach_args* ga = aux; 374 375 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20 || 376 mach_type == MACH_SGI_IP22) { 377 /* Make sure it's actually there and readable */ 378 if (!platform.badaddr((void*)MIPS_PHYS_TO_KSEG1(ga->ga_addr), 379 sizeof(u_int32_t))) 380 return 1; 381 } 382 383 return 0; 384 } 385 386 static void 387 hpc_attach(struct device *parent, struct device *self, void *aux) 388 { 389 struct hpc_softc *sc = (struct hpc_softc *)self; 390 struct gio_attach_args* ga = aux; 391 struct hpc_attach_args ha; 392 const struct hpc_device *hd; 393 uint32_t hpctype; 394 int isonboard; 395 int isioplus; 396 int sysmask; 397 398 #ifdef BLINK 399 callout_init(&hpc_blink_ch, 0); 400 #endif 401 402 switch (mach_type) { 403 case MACH_SGI_IP12: 404 sysmask = HPCDEV_IP12; 405 break; 406 407 case MACH_SGI_IP20: 408 sysmask = HPCDEV_IP20; 409 break; 410 411 case MACH_SGI_IP22: 412 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 413 sysmask = HPCDEV_IP22; 414 else 415 sysmask = HPCDEV_IP24; 416 break; 417 418 default: 419 panic("hpc_attach: can't handle HPC on an IP%d", mach_type); 420 }; 421 422 if ((hpctype = hpc_revision(sc, ga)) == 0) 423 panic("hpc_attach: could not identify HPC revision\n"); 424 425 /* force big-endian mode */ 426 if (hpctype == 15) 427 *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr+HPC1_BIGENDIAN) = 0; 428 429 /* 430 * All machines have only one HPC on the mainboard itself. ''Extra'' 431 * HPCs require bus arbiter and other magic to run happily. 432 */ 433 isonboard = (ga->ga_addr == HPC_BASE_ADDRESS_0); 434 isioplus = (ga->ga_addr == HPC_BASE_ADDRESS_1 && hpctype == 3 && 435 sysmask == HPCDEV_IP24); 436 437 printf(": SGI HPC%d%s (%s)\n", (hpctype == 3) ? 3 : 1, 438 (hpctype == 15) ? ".5" : "", (isonboard) ? "onboard" : 439 (isioplus) ? "IOPLUS mezzanine" : "GIO slot"); 440 441 /* 442 * Configure the bus arbiter appropriately. 443 * 444 * In the case of Challenge S, we must tell the IOPLUS board which 445 * DMA channel to use (we steal it from one of the slots). SGI permits 446 * an HPC1.5 in slot 1, in which case IOPLUS must use EXP0, or any 447 * other DMA-capable board in slot 0, which leaves us to use EXP1. Of 448 * course, this means that only one GIO board may use DMA. 449 * 450 * Note that this never happens on Indigo2. 451 */ 452 if (isioplus) { 453 int arb_slot; 454 455 if (platform.badaddr( 456 (void *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_2), 4)) 457 arb_slot = GIO_SLOT_EXP1; 458 else 459 arb_slot = GIO_SLOT_EXP0; 460 461 if (gio_arb_config(arb_slot, GIO_ARB_LB | GIO_ARB_MST | 462 GIO_ARB_64BIT | GIO_ARB_HPC2_64BIT)) { 463 printf("%s: failed to configure GIO bus arbiter\n", 464 sc->sc_dev.dv_xname); 465 return; 466 } 467 468 printf("%s: using EXP%d's DMA channel\n", sc->sc_dev.dv_xname, 469 (arb_slot == GIO_SLOT_EXP0) ? 0 : 1); 470 471 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 472 HPC3_PBUS_CFGPIO_REGS, 0x0003ffff); 473 474 if (arb_slot == GIO_SLOT_EXP0) 475 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 476 HPC3_PBUS_CH0_DEVREGS, 0x20202020); 477 else 478 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 479 HPC3_PBUS_CH0_DEVREGS, 0x30303030); 480 } else if (!isonboard) { 481 int arb_slot; 482 483 arb_slot = (ga->ga_addr == HPC_BASE_ADDRESS_1) ? 484 GIO_SLOT_EXP0 : GIO_SLOT_EXP1; 485 486 if (gio_arb_config(arb_slot, GIO_ARB_RT | GIO_ARB_MST)) { 487 printf("%s: failed to configure GIO bus arbiter\n", 488 sc->sc_dev.dv_xname); 489 return; 490 } 491 } 492 493 sc->sc_ct = SGIMIPS_BUS_SPACE_HPC; 494 sc->sc_ch = ga->ga_ioh; 495 496 sc->sc_base = ga->ga_addr; 497 498 hpc_read_eeprom(hpctype, SGIMIPS_BUS_SPACE_HPC, 499 MIPS_PHYS_TO_KSEG1(sc->sc_base), ha.hpc_eeprom, 500 sizeof(ha.hpc_eeprom)); 501 502 hd = (hpctype == 3) ? hpc3_devices : hpc1_devices; 503 for (; hd->hd_name != NULL; hd++) { 504 if (!(hd->hd_sysmask & sysmask) || hd->hd_base != sc->sc_base) 505 continue; 506 507 ha.ha_name = hd->hd_name; 508 ha.ha_devoff = hd->hd_devoff; 509 ha.ha_dmaoff = hd->hd_dmaoff; 510 ha.ha_irq = hd->hd_irq; 511 512 /* XXX This is disgusting. */ 513 ha.ha_st = SGIMIPS_BUS_SPACE_HPC; 514 ha.ha_sh = MIPS_PHYS_TO_KSEG1(sc->sc_base); 515 ha.ha_dmat = &sgimips_default_bus_dma_tag; 516 if (hpctype == 3) 517 ha.hpc_regs = &hpc3_values; 518 else 519 ha.hpc_regs = &hpc1_values; 520 ha.hpc_regs->revision = hpctype; 521 522 /* XXXgross! avoid complaining in E++ and GIO32 SCSI cases */ 523 if (hpctype != 3 && sc->sc_base != HPC_BASE_ADDRESS_0) { 524 (void)config_found_sm_loc(self, "hpc", NULL, &ha, 525 NULL, hpc_submatch); 526 } else { 527 (void)config_found_sm_loc(self, "hpc", NULL, &ha, 528 hpc_print, hpc_submatch); 529 } 530 } 531 532 /* 533 * XXX: Only attach the powerfail interrupt once, since the 534 * interrupt code doesn't let you share interrupt just yet. 535 * 536 * Since the powerfail interrupt is hardcoded to read from 537 * a specific register anyway (XXX#2!), we don't care when 538 * it gets attached, as long as it only happens once. 539 */ 540 if (mach_type == MACH_SGI_IP22 && !powerintr_established) { 541 // cpu_intr_establish(9, IPL_NONE, hpc_power_intr, sc); 542 powerintr_established++; 543 } 544 545 #if defined(BLINK) 546 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) 547 hpc_blink(sc); 548 #endif 549 } 550 551 /* 552 * HPC revision detection isn't as simple as it should be. Devices probe 553 * differently depending on their slots, but luckily there is only one 554 * instance in which we have to decide the major revision (HPC1 vs HPC3). 555 * 556 * The HPC is found in the following configurations: 557 * o Personal Iris 4D/3x: 558 * One on-board HPC1 or HPC1.5. 559 * 560 * o Indigo R3k/R4k: 561 * One on-board HPC1 or HPC1.5. 562 * Up to two additional HPC1.5's in GIO slots 0 and 1. 563 * 564 * o Indy: 565 * One on-board HPC3. 566 * Up to two additional HPC1.5's in GIO slots 0 and 1. 567 * 568 * o Challenge S 569 * One on-board HPC3. 570 * Up to one additional HPC3 on the IOPLUS board (if installed). 571 * Up to one additional HPC1.5 in slot 1 of the IOPLUS board. 572 * 573 * o Indigo2, Challenge M 574 * One on-board HPC3. 575 * 576 * All we really have to worry about is the IP22 case. 577 */ 578 static int 579 hpc_revision(struct hpc_softc *sc, struct gio_attach_args *ga) 580 { 581 582 /* No hardware ever supported the last hpc base address. */ 583 if (ga->ga_addr == HPC_BASE_ADDRESS_3) 584 return (0); 585 586 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) { 587 u_int32_t reg; 588 589 if (!platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 590 HPC1_BIGENDIAN), 4)) { 591 reg = *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 592 HPC1_BIGENDIAN); 593 594 if (((reg >> HPC1_REVSHIFT) & HPC1_REVMASK) == 595 HPC1_REV15) 596 return (15); 597 else 598 return (1); 599 } 600 601 return (1); 602 } 603 604 /* 605 * If IP22, probe slot 0 to determine if HPC1.5 or HPC3. Slot 1 must 606 * be HPC1.5. 607 */ 608 if (mach_type == MACH_SGI_IP22) { 609 if (ga->ga_addr == HPC_BASE_ADDRESS_0) 610 return (3); 611 612 if (ga->ga_addr == HPC_BASE_ADDRESS_2) 613 return (15); 614 615 /* 616 * Probe for it. We use one of the PBUS registers. Note 617 * that this probe succeeds with my E++ adapter in slot 1 618 * (bad), but it appears to always do the right thing in 619 * slot 0 (good!) and we're only worried about that one 620 * anyhow. 621 */ 622 if (platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 623 HPC3_PBUS_CH7_BP), 4)) 624 return (15); 625 else 626 return (3); 627 } 628 629 return (0); 630 } 631 632 static int 633 hpc_submatch(struct device *parent, struct cfdata *cf, 634 const int *ldesc, void *aux) 635 { 636 struct hpc_attach_args *ha = aux; 637 638 if (cf->cf_loc[HPCCF_OFFSET] != HPCCF_OFFSET_DEFAULT && 639 (bus_addr_t) cf->cf_loc[HPCCF_OFFSET] != ha->ha_devoff) 640 return (0); 641 642 return (config_match(parent, cf, aux)); 643 } 644 645 static int 646 hpc_print(void *aux, const char *pnp) 647 { 648 struct hpc_attach_args *ha = aux; 649 650 if (pnp) 651 printf("%s at %s", ha->ha_name, pnp); 652 653 printf(" offset 0x%lx", (vaddr_t)ha->ha_devoff); 654 655 return (UNCONF); 656 } 657 658 #if 0 659 static int 660 hpc_power_intr(void *arg) 661 { 662 u_int32_t pwr_reg; 663 664 pwr_reg = *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)); 665 *((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)) = pwr_reg; 666 667 printf("hpc_power_intr: panel reg = %08x\n", pwr_reg); 668 669 if (pwr_reg & 2) 670 cpu_reboot(RB_HALT, NULL); 671 672 return 1; 673 } 674 #endif 675 676 #if defined(BLINK) 677 static void 678 hpc_blink(void *self) 679 { 680 struct hpc_softc *sc = (struct hpc_softc *) self; 681 register int s; 682 int value; 683 684 s = splhigh(); 685 686 value = *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + 687 HPC1_AUX_REGS); 688 value ^= HPC1_AUX_CONSLED; 689 *(volatile u_int8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + 690 HPC1_AUX_REGS) = value; 691 splx(s); 692 693 /* 694 * Blink rate is: 695 * full cycle every second if completely idle (loadav = 0) 696 * full cycle every 2 seconds if loadav = 1 697 * full cycle every 3 seconds if loadav = 2 698 * etc. 699 */ 700 s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); 701 callout_reset(&hpc_blink_ch, s, hpc_blink, sc); 702 } 703 #endif 704 705 /* 706 * Read the eeprom associated with one of the HPC's. 707 * 708 * NB: An eeprom is not always present, but the HPC should be able to 709 * handle this gracefully. Any consumers should validate the data to 710 * ensure it's reasonable. 711 */ 712 static int 713 hpc_read_eeprom(int hpctype, bus_space_tag_t t, bus_space_handle_t h, 714 uint8_t *buf, size_t len) 715 { 716 struct seeprom_descriptor sd; 717 bus_space_handle_t bsh; 718 bus_space_tag_t tag; 719 bus_size_t offset; 720 721 if (!len || len & 0x1) 722 return (1); 723 724 offset = (hpctype == 3) ? HPC3_EEPROM_DATA : HPC1_AUX_REGS; 725 726 tag = SGIMIPS_BUS_SPACE_NORMAL; 727 if (bus_space_subregion(t, h, offset, 1, &bsh) != 0) 728 return (1); 729 730 sd.sd_chip = C56_66; 731 sd.sd_tag = tag; 732 sd.sd_bsh = bsh; 733 sd.sd_regsize = 1; 734 sd.sd_control_offset = 0; 735 sd.sd_status_offset = 0; 736 sd.sd_dataout_offset = 0; 737 sd.sd_DI = 0x10; /* EEPROM -> CPU */ 738 sd.sd_DO = 0x08; /* CPU -> EEPROM */ 739 sd.sd_CK = 0x04; 740 sd.sd_CS = 0x02; 741 sd.sd_MS = 0; 742 sd.sd_RDY = 0; 743 744 if (read_seeprom(&sd, (uint16_t *)buf, 0, len / 2) != 1) 745 return (1); 746 747 bus_space_unmap(t, bsh, 1); 748 749 return (0); 750 } 751
Indexes created Tue Sep 23 02:09:52 GMT 2025