hpc.c revision 1.65
1 /* $NetBSD: hpc.c,v 1.65 2011/01/25 13:22:05 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang 5 * Copyright (c) 2001 Rafal K. Boni 6 * Copyright (c) 2001 Jason R. Thorpe 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.65 2011/01/25 13:22:05 tsutsui Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/reboot.h> 45 #include <sys/callout.h> 46 47 #define _SGIMIPS_BUS_DMA_PRIVATE 48 #include <machine/bus.h> 49 #include <machine/machtype.h> 50 #include <machine/sysconf.h> 51 52 #include <sgimips/gio/gioreg.h> 53 #include <sgimips/gio/giovar.h> 54 55 #include <sgimips/hpc/hpcvar.h> 56 #include <sgimips/hpc/hpcreg.h> 57 #include <sgimips/ioc/iocreg.h> 58 59 #include <dev/ic/smc93cx6var.h> 60 61 #include "locators.h" 62 63 struct hpc_device { 64 const char *hd_name; 65 bus_addr_t hd_base; 66 bus_addr_t hd_devoff; 67 bus_addr_t hd_dmaoff; 68 int hd_irq; 69 int hd_sysmask; 70 }; 71 72 static const struct hpc_device hpc1_devices[] = { 73 /* probe order is important for IP20 zsc */ 74 75 { "zsc", /* Personal Iris/Indigo serial 0/1 duart 1 */ 76 HPC_BASE_ADDRESS_0, 77 0x0d10, 0, 78 5, 79 HPCDEV_IP12 | HPCDEV_IP20 }, 80 81 { "zsc", /* Personal Iris/Indigo kbd/ms duart 0 */ 82 HPC_BASE_ADDRESS_0, 83 0x0d00, 0, 84 5, 85 HPCDEV_IP12 | HPCDEV_IP20 }, 86 87 { "sq", /* Personal Iris/Indigo onboard ethernet */ 88 HPC_BASE_ADDRESS_0, 89 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 90 3, 91 HPCDEV_IP12 | HPCDEV_IP20 }, 92 93 { "sq", /* E++ GIO adapter slot 0 (Indigo) */ 94 HPC_BASE_ADDRESS_1, 95 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 96 6, 97 HPCDEV_IP12 | HPCDEV_IP20 }, 98 99 { "sq", /* E++ GIO adapter slot 0 (Indy) */ 100 HPC_BASE_ADDRESS_1, 101 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 102 22, 103 HPCDEV_IP24 }, 104 105 { "sq", /* E++ GIO adapter slot 1 (Indigo) */ 106 HPC_BASE_ADDRESS_2, 107 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 108 6, 109 HPCDEV_IP12 | HPCDEV_IP20 }, 110 111 { "sq", /* E++ GIO adapter slot 1 (Indy/Challenge S) */ 112 HPC_BASE_ADDRESS_2, 113 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 114 23, 115 HPCDEV_IP24 }, 116 117 { "wdsc", /* Personal Iris/Indigo onboard SCSI */ 118 HPC_BASE_ADDRESS_0, 119 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 120 2, /* XXX 1 = IRQ_LOCAL0 + 2 */ 121 HPCDEV_IP12 | HPCDEV_IP20 }, 122 123 { "wdsc", /* GIO32 SCSI adapter slot 0 (Indigo) */ 124 HPC_BASE_ADDRESS_1, 125 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 126 6, 127 HPCDEV_IP12 | HPCDEV_IP20 }, 128 129 { "wdsc", /* GIO32 SCSI adapter slot 0 (Indy) */ 130 HPC_BASE_ADDRESS_1, 131 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 132 22, 133 HPCDEV_IP24 }, 134 135 { "wdsc", /* GIO32 SCSI adapter slot 1 (Indigo) */ 136 HPC_BASE_ADDRESS_2, 137 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 138 6, 139 HPCDEV_IP12 | HPCDEV_IP20 }, 140 141 { "wdsc", /* GIO32 SCSI adapter slot 1 (Indy/Challenge S) */ 142 HPC_BASE_ADDRESS_2, 143 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 144 23, 145 HPCDEV_IP24 }, 146 147 { NULL, 148 0, 149 0, 0, 150 0, 151 0 152 } 153 }; 154 155 static const struct hpc_device hpc3_devices[] = { 156 { "zsc", /* serial 0/1 duart 0 */ 157 HPC_BASE_ADDRESS_0, 158 /* XXX Magic numbers */ 159 HPC3_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0, 160 29, 161 HPCDEV_IP22 | HPCDEV_IP24 }, 162 163 { "pckbc", /* Indigo2/Indy ps2 keyboard/mouse controller */ 164 HPC_BASE_ADDRESS_0, 165 HPC3_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0, 166 28, 167 HPCDEV_IP22 | HPCDEV_IP24 }, 168 169 { "sq", /* Indigo2/Indy/Challenge S/Challenge M onboard enet */ 170 HPC_BASE_ADDRESS_0, 171 HPC3_ENET_DEVREGS, HPC3_ENET_REGS, 172 3, 173 HPCDEV_IP22 | HPCDEV_IP24 }, 174 175 { "sq", /* Challenge S IOPLUS secondary ethernet */ 176 HPC_BASE_ADDRESS_1, 177 HPC3_ENET_DEVREGS, HPC3_ENET_REGS, 178 0, 179 HPCDEV_IP24 }, 180 181 { "wdsc", /* Indigo2/Indy/Challenge S/Challenge M onboard SCSI */ 182 HPC_BASE_ADDRESS_0, 183 HPC3_SCSI0_DEVREGS, HPC3_SCSI0_REGS, 184 1, /* XXX 1 = IRQ_LOCAL0 + 1 */ 185 HPCDEV_IP22 | HPCDEV_IP24 }, 186 187 { "wdsc", /* Indigo2/Challenge M secondary onboard SCSI */ 188 HPC_BASE_ADDRESS_0, 189 HPC3_SCSI1_DEVREGS, HPC3_SCSI1_REGS, 190 2, /* XXX 2 = IRQ_LOCAL0 + 2 */ 191 HPCDEV_IP22 }, 192 193 { "haltwo", /* Indigo2/Indy onboard audio */ 194 HPC_BASE_ADDRESS_0, 195 HPC3_PBUS_CH0_DEVREGS, HPC3_PBUS_DMAREGS, 196 8 + 4, /* XXX IRQ_LOCAL1 + 4 */ 197 HPCDEV_IP22 | HPCDEV_IP24 }, 198 199 { "pi1ppc", /* Indigo2/Indy/Challenge S/Challenge M onboard pport */ 200 HPC_BASE_ADDRESS_0, 201 HPC3_PBUS_CH6_DEVREGS + IOC_PLP_REGS, 0, 202 -1, 203 HPCDEV_IP22 | HPCDEV_IP24 }, 204 205 { "panel", /* Indy front panel */ 206 HPC_BASE_ADDRESS_0, 207 HPC3_PBUS_CH6_DEVREGS + IOC_PANEL, 0, 208 9, 209 HPCDEV_IP24 }, 210 211 { NULL, 212 0, 213 0, 0, 214 0, 215 0 216 } 217 }; 218 219 struct hpc_softc { 220 device_t sc_dev; 221 222 bus_addr_t sc_base; 223 224 bus_space_tag_t sc_ct; 225 bus_space_handle_t sc_ch; 226 }; 227 228 static struct hpc_values hpc1_values = { 229 .revision = 1, 230 .scsi0_regs = HPC1_SCSI0_REGS, 231 .scsi0_regs_size = HPC1_SCSI0_REGS_SIZE, 232 .scsi0_cbp = HPC1_SCSI0_CBP, 233 .scsi0_ndbp = HPC1_SCSI0_NDBP, 234 .scsi0_bc = HPC1_SCSI0_BC, 235 .scsi0_ctl = HPC1_SCSI0_CTL, 236 .scsi0_gio = HPC1_SCSI0_GIO, 237 .scsi0_dev = HPC1_SCSI0_DEV, 238 .scsi0_dmacfg = HPC1_SCSI0_DMACFG, 239 .scsi0_piocfg = HPC1_SCSI0_PIOCFG, 240 .scsi1_regs = 0, 241 .scsi1_regs_size = 0, 242 .scsi1_cbp = 0, 243 .scsi1_ndbp = 0, 244 .scsi1_bc = 0, 245 .scsi1_ctl = 0, 246 .scsi1_gio = 0, 247 .scsi1_dev = 0, 248 .scsi1_dmacfg = 0, 249 .scsi1_piocfg = 0, 250 .enet_regs = HPC1_ENET_REGS, 251 .enet_regs_size = HPC1_ENET_REGS_SIZE, 252 .enet_intdelay = HPC1_ENET_INTDELAY, 253 .enet_intdelayval = HPC1_ENET_INTDELAY_OFF, 254 .enetr_cbp = HPC1_ENETR_CBP, 255 .enetr_ndbp = HPC1_ENETR_NDBP, 256 .enetr_bc = HPC1_ENETR_BC, 257 .enetr_ctl = HPC1_ENETR_CTL, 258 .enetr_ctl_active = HPC1_ENETR_CTL_ACTIVE, 259 .enetr_reset = HPC1_ENETR_RESET, 260 .enetr_dmacfg = 0, 261 .enetr_piocfg = 0, 262 .enetx_cbp = HPC1_ENETX_CBP, 263 .enetx_ndbp = HPC1_ENETX_NDBP, 264 .enetx_bc = HPC1_ENETX_BC, 265 .enetx_ctl = HPC1_ENETX_CTL, 266 .enetx_ctl_active = HPC1_ENETX_CTL_ACTIVE, 267 .enetx_dev = 0, 268 .enetr_fifo = HPC1_ENETR_FIFO, 269 .enetr_fifo_size = HPC1_ENETR_FIFO_SIZE, 270 .enetx_fifo = HPC1_ENETX_FIFO, 271 .enetx_fifo_size = HPC1_ENETX_FIFO_SIZE, 272 .scsi0_devregs_size = HPC1_SCSI0_DEVREGS_SIZE, 273 .scsi1_devregs_size = 0, 274 .enet_devregs = HPC1_ENET_DEVREGS, 275 .enet_devregs_size = HPC1_ENET_DEVREGS_SIZE, 276 .pbus_fifo = 0, 277 .pbus_fifo_size = 0, 278 .pbus_bbram = 0, 279 #define MAX_SCSI_XFER (512*1024) 280 .scsi_max_xfer = MAX_SCSI_XFER, 281 .scsi_dma_segs = (MAX_SCSI_XFER / 4096), 282 .scsi_dma_segs_size = 4096, 283 .scsi_dma_datain_cmd = (HPC1_SCSI_DMACTL_ACTIVE | HPC1_SCSI_DMACTL_DIR), 284 .scsi_dma_dataout_cmd = HPC1_SCSI_DMACTL_ACTIVE, 285 .scsi_dmactl_flush = HPC1_SCSI_DMACTL_FLUSH, 286 .scsi_dmactl_active = HPC1_SCSI_DMACTL_ACTIVE, 287 .scsi_dmactl_reset = HPC1_SCSI_DMACTL_RESET 288 }; 289 290 static struct hpc_values hpc3_values = { 291 .revision = 3, 292 .scsi0_regs = HPC3_SCSI0_REGS, 293 .scsi0_regs_size = HPC3_SCSI0_REGS_SIZE, 294 .scsi0_cbp = HPC3_SCSI0_CBP, 295 .scsi0_ndbp = HPC3_SCSI0_NDBP, 296 .scsi0_bc = HPC3_SCSI0_BC, 297 .scsi0_ctl = HPC3_SCSI0_CTL, 298 .scsi0_gio = HPC3_SCSI0_GIO, 299 .scsi0_dev = HPC3_SCSI0_DEV, 300 .scsi0_dmacfg = HPC3_SCSI0_DMACFG, 301 .scsi0_piocfg = HPC3_SCSI0_PIOCFG, 302 .scsi1_regs = HPC3_SCSI1_REGS, 303 .scsi1_regs_size = HPC3_SCSI1_REGS_SIZE, 304 .scsi1_cbp = HPC3_SCSI1_CBP, 305 .scsi1_ndbp = HPC3_SCSI1_NDBP, 306 .scsi1_bc = HPC3_SCSI1_BC, 307 .scsi1_ctl = HPC3_SCSI1_CTL, 308 .scsi1_gio = HPC3_SCSI1_GIO, 309 .scsi1_dev = HPC3_SCSI1_DEV, 310 .scsi1_dmacfg = HPC3_SCSI1_DMACFG, 311 .scsi1_piocfg = HPC3_SCSI1_PIOCFG, 312 .enet_regs = HPC3_ENET_REGS, 313 .enet_regs_size = HPC3_ENET_REGS_SIZE, 314 .enet_intdelay = 0, 315 .enet_intdelayval = 0, 316 .enetr_cbp = HPC3_ENETR_CBP, 317 .enetr_ndbp = HPC3_ENETR_NDBP, 318 .enetr_bc = HPC3_ENETR_BC, 319 .enetr_ctl = HPC3_ENETR_CTL, 320 .enetr_ctl_active = HPC3_ENETR_CTL_ACTIVE, 321 .enetr_reset = HPC3_ENETR_RESET, 322 .enetr_dmacfg = HPC3_ENETR_DMACFG, 323 .enetr_piocfg = HPC3_ENETR_PIOCFG, 324 .enetx_cbp = HPC3_ENETX_CBP, 325 .enetx_ndbp = HPC3_ENETX_NDBP, 326 .enetx_bc = HPC3_ENETX_BC, 327 .enetx_ctl = HPC3_ENETX_CTL, 328 .enetx_ctl_active = HPC3_ENETX_CTL_ACTIVE, 329 .enetx_dev = HPC3_ENETX_DEV, 330 .enetr_fifo = HPC3_ENETR_FIFO, 331 .enetr_fifo_size = HPC3_ENETR_FIFO_SIZE, 332 .enetx_fifo = HPC3_ENETX_FIFO, 333 .enetx_fifo_size = HPC3_ENETX_FIFO_SIZE, 334 .scsi0_devregs_size = HPC3_SCSI0_DEVREGS_SIZE, 335 .scsi1_devregs_size = HPC3_SCSI1_DEVREGS_SIZE, 336 .enet_devregs = HPC3_ENET_DEVREGS, 337 .enet_devregs_size = HPC3_ENET_DEVREGS_SIZE, 338 .pbus_fifo = HPC3_PBUS_FIFO, 339 .pbus_fifo_size = HPC3_PBUS_FIFO_SIZE, 340 .pbus_bbram = HPC3_PBUS_BBRAM, 341 .scsi_max_xfer = MAX_SCSI_XFER, 342 .scsi_dma_segs = (MAX_SCSI_XFER / 8192), 343 .scsi_dma_segs_size = 8192, 344 .scsi_dma_datain_cmd = HPC3_SCSI_DMACTL_ACTIVE, 345 .scsi_dma_dataout_cmd =(HPC3_SCSI_DMACTL_ACTIVE | HPC3_SCSI_DMACTL_DIR), 346 .scsi_dmactl_flush = HPC3_SCSI_DMACTL_FLUSH, 347 .scsi_dmactl_active = HPC3_SCSI_DMACTL_ACTIVE, 348 .scsi_dmactl_reset = HPC3_SCSI_DMACTL_RESET 349 }; 350 351 352 static int powerintr_established; 353 354 static int hpc_match(device_t, cfdata_t, void *); 355 static void hpc_attach(device_t, device_t, void *); 356 static int hpc_print(void *, const char *); 357 358 static int hpc_revision(struct hpc_softc *, struct gio_attach_args *); 359 360 static int hpc_submatch(device_t, cfdata_t, const int *, void *); 361 362 //static int hpc_power_intr(void *); 363 364 #if defined(BLINK) 365 static callout_t hpc_blink_ch; 366 static void hpc_blink(void *); 367 #endif 368 369 static int hpc_read_eeprom(int, bus_space_tag_t, bus_space_handle_t, 370 uint8_t *, size_t); 371 372 CFATTACH_DECL_NEW(hpc, sizeof(struct hpc_softc), 373 hpc_match, hpc_attach, NULL, NULL); 374 375 static int 376 hpc_match(device_t parent, cfdata_t cf, void *aux) 377 { 378 struct gio_attach_args* ga = aux; 379 380 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20 || 381 mach_type == MACH_SGI_IP22) { 382 /* Make sure it's actually there and readable */ 383 if (!platform.badaddr((void*)MIPS_PHYS_TO_KSEG1(ga->ga_addr), 384 sizeof(uint32_t))) 385 return 1; 386 } 387 388 return 0; 389 } 390 391 static void 392 hpc_attach(device_t parent, device_t self, void *aux) 393 { 394 struct hpc_softc *sc = device_private(self); 395 struct gio_attach_args* ga = aux; 396 struct hpc_attach_args ha; 397 const struct hpc_device *hd; 398 uint32_t hpctype; 399 int isonboard; 400 int isioplus; 401 int sysmask; 402 403 sc->sc_dev = self; 404 405 #ifdef BLINK 406 callout_init(&hpc_blink_ch, 0); 407 #endif 408 409 switch (mach_type) { 410 case MACH_SGI_IP12: 411 sysmask = HPCDEV_IP12; 412 break; 413 414 case MACH_SGI_IP20: 415 sysmask = HPCDEV_IP20; 416 break; 417 418 case MACH_SGI_IP22: 419 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 420 sysmask = HPCDEV_IP22; 421 else 422 sysmask = HPCDEV_IP24; 423 break; 424 425 default: 426 panic("hpc_attach: can't handle HPC on an IP%d", mach_type); 427 }; 428 429 if ((hpctype = hpc_revision(sc, ga)) == 0) 430 panic("hpc_attach: could not identify HPC revision\n"); 431 432 /* force big-endian mode */ 433 if (hpctype == 15) 434 *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr+HPC1_BIGENDIAN) = 0; 435 436 /* 437 * All machines have only one HPC on the mainboard itself. ''Extra'' 438 * HPCs require bus arbiter and other magic to run happily. 439 */ 440 isonboard = (ga->ga_addr == HPC_BASE_ADDRESS_0); 441 isioplus = (ga->ga_addr == HPC_BASE_ADDRESS_1 && hpctype == 3 && 442 sysmask == HPCDEV_IP24); 443 444 printf(": SGI HPC%d%s (%s)\n", (hpctype == 3) ? 3 : 1, 445 (hpctype == 15) ? ".5" : "", (isonboard) ? "onboard" : 446 (isioplus) ? "IOPLUS mezzanine" : "GIO slot"); 447 448 /* 449 * Configure the bus arbiter appropriately. 450 * 451 * In the case of Challenge S, we must tell the IOPLUS board which 452 * DMA channel to use (we steal it from one of the slots). SGI permits 453 * an HPC1.5 in slot 1, in which case IOPLUS must use EXP0, or any 454 * other DMA-capable board in slot 0, which leaves us to use EXP1. Of 455 * course, this means that only one GIO board may use DMA. 456 * 457 * Note that this never happens on Indigo2. 458 */ 459 if (isioplus) { 460 int arb_slot; 461 462 if (platform.badaddr( 463 (void *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_2), 4)) 464 arb_slot = GIO_SLOT_EXP1; 465 else 466 arb_slot = GIO_SLOT_EXP0; 467 468 if (gio_arb_config(arb_slot, GIO_ARB_LB | GIO_ARB_MST | 469 GIO_ARB_64BIT | GIO_ARB_HPC2_64BIT)) { 470 printf("%s: failed to configure GIO bus arbiter\n", 471 device_xname(sc->sc_dev)); 472 return; 473 } 474 475 printf("%s: using EXP%d's DMA channel\n", 476 device_xname(sc->sc_dev), 477 (arb_slot == GIO_SLOT_EXP0) ? 0 : 1); 478 479 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 480 HPC3_PBUS_CFGPIO_REGS, 0x0003ffff); 481 482 if (arb_slot == GIO_SLOT_EXP0) 483 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 484 HPC3_PBUS_CH0_DEVREGS, 0x20202020); 485 else 486 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 487 HPC3_PBUS_CH0_DEVREGS, 0x30303030); 488 } else if (!isonboard) { 489 int arb_slot; 490 491 arb_slot = (ga->ga_addr == HPC_BASE_ADDRESS_1) ? 492 GIO_SLOT_EXP0 : GIO_SLOT_EXP1; 493 494 if (gio_arb_config(arb_slot, GIO_ARB_RT | GIO_ARB_MST)) { 495 printf("%s: failed to configure GIO bus arbiter\n", 496 device_xname(sc->sc_dev)); 497 return; 498 } 499 } 500 501 sc->sc_ct = SGIMIPS_BUS_SPACE_HPC; 502 sc->sc_ch = ga->ga_ioh; 503 504 sc->sc_base = ga->ga_addr; 505 506 hpc_read_eeprom(hpctype, SGIMIPS_BUS_SPACE_HPC, 507 MIPS_PHYS_TO_KSEG1(sc->sc_base), ha.hpc_eeprom, 508 sizeof(ha.hpc_eeprom)); 509 510 hd = (hpctype == 3) ? hpc3_devices : hpc1_devices; 511 for (; hd->hd_name != NULL; hd++) { 512 if (!(hd->hd_sysmask & sysmask) || hd->hd_base != sc->sc_base) 513 continue; 514 515 ha.ha_name = hd->hd_name; 516 ha.ha_devoff = hd->hd_devoff; 517 ha.ha_dmaoff = hd->hd_dmaoff; 518 ha.ha_irq = hd->hd_irq; 519 520 /* XXX This is disgusting. */ 521 ha.ha_st = SGIMIPS_BUS_SPACE_HPC; 522 ha.ha_sh = MIPS_PHYS_TO_KSEG1(sc->sc_base); 523 ha.ha_dmat = &sgimips_default_bus_dma_tag; 524 if (hpctype == 3) 525 ha.hpc_regs = &hpc3_values; 526 else 527 ha.hpc_regs = &hpc1_values; 528 ha.hpc_regs->revision = hpctype; 529 530 /* XXXgross! avoid complaining in E++ and GIO32 SCSI cases */ 531 if (hpctype != 3 && sc->sc_base != HPC_BASE_ADDRESS_0) { 532 (void)config_found_sm_loc(self, "hpc", NULL, &ha, 533 NULL, hpc_submatch); 534 } else { 535 (void)config_found_sm_loc(self, "hpc", NULL, &ha, 536 hpc_print, hpc_submatch); 537 } 538 } 539 540 /* 541 * XXX: Only attach the powerfail interrupt once, since the 542 * interrupt code doesn't let you share interrupt just yet. 543 * 544 * Since the powerfail interrupt is hardcoded to read from 545 * a specific register anyway (XXX#2!), we don't care when 546 * it gets attached, as long as it only happens once. 547 */ 548 if (mach_type == MACH_SGI_IP22 && !powerintr_established) { 549 // cpu_intr_establish(9, IPL_NONE, hpc_power_intr, sc); 550 powerintr_established++; 551 } 552 553 #if defined(BLINK) 554 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) 555 hpc_blink(sc); 556 #endif 557 } 558 559 /* 560 * HPC revision detection isn't as simple as it should be. Devices probe 561 * differently depending on their slots, but luckily there is only one 562 * instance in which we have to decide the major revision (HPC1 vs HPC3). 563 * 564 * The HPC is found in the following configurations: 565 * o Personal Iris 4D/3x: 566 * One on-board HPC1 or HPC1.5. 567 * 568 * o Indigo R3k/R4k: 569 * One on-board HPC1 or HPC1.5. 570 * Up to two additional HPC1.5's in GIO slots 0 and 1. 571 * 572 * o Indy: 573 * One on-board HPC3. 574 * Up to two additional HPC1.5's in GIO slots 0 and 1. 575 * 576 * o Challenge S 577 * One on-board HPC3. 578 * Up to one additional HPC3 on the IOPLUS board (if installed). 579 * Up to one additional HPC1.5 in slot 1 of the IOPLUS board. 580 * 581 * o Indigo2, Challenge M 582 * One on-board HPC3. 583 * 584 * All we really have to worry about is the IP22 case. 585 */ 586 static int 587 hpc_revision(struct hpc_softc *sc, struct gio_attach_args *ga) 588 { 589 590 /* No hardware ever supported the last hpc base address. */ 591 if (ga->ga_addr == HPC_BASE_ADDRESS_3) 592 return (0); 593 594 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) { 595 uint32_t reg; 596 597 if (!platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 598 HPC1_BIGENDIAN), 4)) { 599 reg = *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 600 HPC1_BIGENDIAN); 601 602 if (((reg >> HPC1_REVSHIFT) & HPC1_REVMASK) == 603 HPC1_REV15) 604 return (15); 605 else 606 return (1); 607 } 608 609 return (1); 610 } 611 612 /* 613 * If IP22, probe slot 0 to determine if HPC1.5 or HPC3. Slot 1 must 614 * be HPC1.5. 615 */ 616 if (mach_type == MACH_SGI_IP22) { 617 if (ga->ga_addr == HPC_BASE_ADDRESS_0) 618 return (3); 619 620 if (ga->ga_addr == HPC_BASE_ADDRESS_2) 621 return (15); 622 623 /* 624 * Probe for it. We use one of the PBUS registers. Note 625 * that this probe succeeds with my E++ adapter in slot 1 626 * (bad), but it appears to always do the right thing in 627 * slot 0 (good!) and we're only worried about that one 628 * anyhow. 629 */ 630 if (platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 631 HPC3_PBUS_CH7_BP), 4)) 632 return (15); 633 else 634 return (3); 635 } 636 637 return (0); 638 } 639 640 static int 641 hpc_submatch(struct device *parent, struct cfdata *cf, 642 const int *ldesc, void *aux) 643 { 644 struct hpc_attach_args *ha = aux; 645 646 if (cf->cf_loc[HPCCF_OFFSET] != HPCCF_OFFSET_DEFAULT && 647 (bus_addr_t) cf->cf_loc[HPCCF_OFFSET] != ha->ha_devoff) 648 return (0); 649 650 return (config_match(parent, cf, aux)); 651 } 652 653 static int 654 hpc_print(void *aux, const char *pnp) 655 { 656 struct hpc_attach_args *ha = aux; 657 658 if (pnp) 659 printf("%s at %s", ha->ha_name, pnp); 660 661 printf(" offset %#" PRIxVADDR, (vaddr_t)ha->ha_devoff); 662 663 return (UNCONF); 664 } 665 666 #if 0 667 static int 668 hpc_power_intr(void *arg) 669 { 670 uint32_t pwr_reg; 671 672 pwr_reg = *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)); 673 *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(0x1fbd9850)) = pwr_reg; 674 675 printf("hpc_power_intr: panel reg = %08x\n", pwr_reg); 676 677 if (pwr_reg & 2) 678 cpu_reboot(RB_HALT, NULL); 679 680 return 1; 681 } 682 #endif 683 684 #if defined(BLINK) 685 static void 686 hpc_blink(void *arg) 687 { 688 struct hpc_softc *sc = arg; 689 register int s; 690 int value; 691 692 s = splhigh(); 693 694 value = *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + 695 HPC1_AUX_REGS); 696 value ^= HPC1_AUX_CONSLED; 697 *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + 698 HPC1_AUX_REGS) = value; 699 splx(s); 700 701 /* 702 * Blink rate is: 703 * full cycle every second if completely idle (loadav = 0) 704 * full cycle every 2 seconds if loadav = 1 705 * full cycle every 3 seconds if loadav = 2 706 * etc. 707 */ 708 s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); 709 callout_reset(&hpc_blink_ch, s, hpc_blink, sc); 710 } 711 #endif 712 713 /* 714 * Read the eeprom associated with one of the HPC's. 715 * 716 * NB: An eeprom is not always present, but the HPC should be able to 717 * handle this gracefully. Any consumers should validate the data to 718 * ensure it's reasonable. 719 */ 720 static int 721 hpc_read_eeprom(int hpctype, bus_space_tag_t t, bus_space_handle_t h, 722 uint8_t *buf, size_t len) 723 { 724 struct seeprom_descriptor sd; 725 bus_space_handle_t bsh; 726 bus_space_tag_t tag; 727 bus_size_t offset; 728 729 if (!len || len & 0x1) 730 return (1); 731 732 offset = (hpctype == 3) ? HPC3_EEPROM_DATA : HPC1_AUX_REGS; 733 734 tag = SGIMIPS_BUS_SPACE_NORMAL; 735 if (bus_space_subregion(t, h, offset, 1, &bsh) != 0) 736 return (1); 737 738 sd.sd_chip = C56_66; 739 sd.sd_tag = tag; 740 sd.sd_bsh = bsh; 741 sd.sd_regsize = 1; 742 sd.sd_control_offset = 0; 743 sd.sd_status_offset = 0; 744 sd.sd_dataout_offset = 0; 745 sd.sd_DI = 0x10; /* EEPROM -> CPU */ 746 sd.sd_DO = 0x08; /* CPU -> EEPROM */ 747 sd.sd_CK = 0x04; 748 sd.sd_CS = 0x02; 749 sd.sd_MS = 0; 750 sd.sd_RDY = 0; 751 752 if (read_seeprom(&sd, (uint16_t *)buf, 0, len / 2) != 1) 753 return (1); 754 755 bus_space_unmap(t, bsh, 1); 756 757 return (0); 758 } 759
Indexes created Mon Sep 22 05:09:51 GMT 2025