hpcdma.c revision 1.1.8.2 1 1.1.8.2 nathanw /* $NetBSD: hpcdma.c,v 1.1.8.2 2002/01/08 00:27:27 nathanw Exp $ */
2 1.1.8.2 nathanw
3 1.1.8.2 nathanw /*
4 1.1.8.2 nathanw * Copyright (c) 2001 Wayne Knowles
5 1.1.8.2 nathanw * All rights reserved.
6 1.1.8.2 nathanw *
7 1.1.8.2 nathanw * This code is derived from software contributed to The NetBSD Foundation
8 1.1.8.2 nathanw * by Wayne Knowles
9 1.1.8.2 nathanw *
10 1.1.8.2 nathanw * Redistribution and use in source and binary forms, with or without
11 1.1.8.2 nathanw * modification, are permitted provided that the following conditions
12 1.1.8.2 nathanw * are met:
13 1.1.8.2 nathanw * 1. Redistributions of source code must retain the above copyright
14 1.1.8.2 nathanw * notice, this list of conditions and the following disclaimer.
15 1.1.8.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright
16 1.1.8.2 nathanw * notice, this list of conditions and the following disclaimer in the
17 1.1.8.2 nathanw * documentation and/or other materials provided with the distribution.
18 1.1.8.2 nathanw * 3. All advertising materials mentioning features or use of this software
19 1.1.8.2 nathanw * must display the following acknowledgement:
20 1.1.8.2 nathanw * This product includes software developed by the NetBSD
21 1.1.8.2 nathanw * Foundation, Inc. and its contributors.
22 1.1.8.2 nathanw * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1.8.2 nathanw * contributors may be used to endorse or promote products derived
24 1.1.8.2 nathanw * from this software without specific prior written permission.
25 1.1.8.2 nathanw *
26 1.1.8.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1.8.2 nathanw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1.8.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1.8.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1.8.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1.8.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1.8.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1.8.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1.8.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1.8.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1.8.2 nathanw * POSSIBILITY OF SUCH DAMAGE.
37 1.1.8.2 nathanw */
38 1.1.8.2 nathanw
39 1.1.8.2 nathanw /*
40 1.1.8.2 nathanw * Support for SCSI DMA provided by the HPC.
41 1.1.8.2 nathanw *
42 1.1.8.2 nathanw * Note: We use SCSI0 offsets, etc. here. Since the layout of SCSI0
43 1.1.8.2 nathanw * and SCSI1 are the same, this is no problem.
44 1.1.8.2 nathanw */
45 1.1.8.2 nathanw
46 1.1.8.2 nathanw #include <sys/param.h>
47 1.1.8.2 nathanw #include <sys/systm.h>
48 1.1.8.2 nathanw #include <sys/device.h>
49 1.1.8.2 nathanw #include <sys/buf.h>
50 1.1.8.2 nathanw
51 1.1.8.2 nathanw #include <machine/bus.h>
52 1.1.8.2 nathanw
53 1.1.8.2 nathanw #include <sgimips/hpc/hpcvar.h>
54 1.1.8.2 nathanw #include <sgimips/hpc/hpcreg.h>
55 1.1.8.2 nathanw #include <sgimips/hpc/hpcdma.h>
56 1.1.8.2 nathanw
57 1.1.8.2 nathanw /*
58 1.1.8.2 nathanw * Allocate DMA Chain descriptor list
59 1.1.8.2 nathanw */
60 1.1.8.2 nathanw void
61 1.1.8.2 nathanw hpcdma_init(struct hpc_attach_args *haa, struct hpc_dma_softc *sc, int ndesc)
62 1.1.8.2 nathanw {
63 1.1.8.2 nathanw bus_dma_segment_t seg;
64 1.1.8.2 nathanw struct hpc_dma_desc *hdd;
65 1.1.8.2 nathanw int rseg, allocsz;
66 1.1.8.2 nathanw
67 1.1.8.2 nathanw sc->sc_bst = haa->ha_st;
68 1.1.8.2 nathanw sc->sc_dmat = haa->ha_dmat;
69 1.1.8.2 nathanw sc->sc_ndesc = ndesc;
70 1.1.8.2 nathanw sc->sc_flags = 0;
71 1.1.8.2 nathanw
72 1.1.8.2 nathanw if (bus_space_subregion(haa->ha_st, haa->ha_sh, haa->ha_dmaoff,
73 1.1.8.2 nathanw HPC_SCSI0_REGS_SIZE, &sc->sc_bsh) != 0) {
74 1.1.8.2 nathanw printf(": can't map DMA registers\n");
75 1.1.8.2 nathanw return;
76 1.1.8.2 nathanw }
77 1.1.8.2 nathanw
78 1.1.8.2 nathanw /* Alloc 1 additional descriptor - needed for DMA bug fix */
79 1.1.8.2 nathanw allocsz = sizeof(struct hpc_dma_desc) * (ndesc + 1);
80 1.1.8.2 nathanw KASSERT(allocsz <= NBPG);
81 1.1.8.2 nathanw
82 1.1.8.2 nathanw if (bus_dmamap_create(sc->sc_dmat, NBPG, 1 /*seg*/,
83 1.1.8.2 nathanw NBPG, 0, BUS_DMA_WAITOK,
84 1.1.8.2 nathanw &sc->sc_dmamap) != 0) {
85 1.1.8.2 nathanw printf(": failed to create dmamap\n");
86 1.1.8.2 nathanw return;
87 1.1.8.2 nathanw }
88 1.1.8.2 nathanw
89 1.1.8.2 nathanw /*
90 1.1.8.2 nathanw * Allocate a block of memory for dma chaining pointers
91 1.1.8.2 nathanw */
92 1.1.8.2 nathanw if (bus_dmamem_alloc(sc->sc_dmat, allocsz, 0, 0,
93 1.1.8.2 nathanw &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
94 1.1.8.2 nathanw printf(": can't allocate sglist\n");
95 1.1.8.2 nathanw return;
96 1.1.8.2 nathanw }
97 1.1.8.2 nathanw /* Map pages into kernel memory */
98 1.1.8.2 nathanw if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, allocsz,
99 1.1.8.2 nathanw (caddr_t *)&hdd, BUS_DMA_NOWAIT)) {
100 1.1.8.2 nathanw printf(": can't map sglist\n");
101 1.1.8.2 nathanw bus_dmamem_free(sc->sc_dmat, &seg, rseg);
102 1.1.8.2 nathanw return;
103 1.1.8.2 nathanw }
104 1.1.8.2 nathanw
105 1.1.8.2 nathanw if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, hdd,
106 1.1.8.2 nathanw allocsz, NULL, BUS_DMA_NOWAIT)) {
107 1.1.8.2 nathanw printf(": can't load sglist\n");
108 1.1.8.2 nathanw return;
109 1.1.8.2 nathanw }
110 1.1.8.2 nathanw
111 1.1.8.2 nathanw sc->sc_desc_kva = hdd;
112 1.1.8.2 nathanw sc->sc_desc_pa = (void *) sc->sc_dmamap->dm_segs[0].ds_addr;
113 1.1.8.2 nathanw }
114 1.1.8.2 nathanw
115 1.1.8.2 nathanw
116 1.1.8.2 nathanw void
117 1.1.8.2 nathanw hpcdma_sglist_create(struct hpc_dma_softc *sc, bus_dmamap_t dmamap)
118 1.1.8.2 nathanw {
119 1.1.8.2 nathanw struct hpc_dma_desc *hva, *hpa;
120 1.1.8.2 nathanw bus_dma_segment_t *segp;
121 1.1.8.2 nathanw int i;
122 1.1.8.2 nathanw
123 1.1.8.2 nathanw KASSERT(dmamap->dm_nsegs <= sc->sc_ndesc);
124 1.1.8.2 nathanw
125 1.1.8.2 nathanw hva = sc->sc_desc_kva;
126 1.1.8.2 nathanw hpa = sc->sc_desc_pa;
127 1.1.8.2 nathanw segp = dmamap->dm_segs;
128 1.1.8.2 nathanw
129 1.1.8.2 nathanw #ifdef DMA_DEBUG
130 1.1.8.2 nathanw printf("DMA_SGLIST<");
131 1.1.8.2 nathanw #endif
132 1.1.8.2 nathanw for (i = dmamap->dm_nsegs; i; i--) {
133 1.1.8.2 nathanw #ifdef DMA_DEBUG
134 1.1.8.2 nathanw printf("%p:%ld, ", (void *)segp->ds_addr, segp->ds_len);
135 1.1.8.2 nathanw #endif
136 1.1.8.2 nathanw hva->hdd_bufptr = segp->ds_addr;
137 1.1.8.2 nathanw hva->hdd_ctl = segp->ds_len;
138 1.1.8.2 nathanw hva->hdd_descptr = (u_int32_t) ++hpa;
139 1.1.8.2 nathanw ++hva; ++segp;
140 1.1.8.2 nathanw }
141 1.1.8.2 nathanw /* Work around HPC3 DMA bug */
142 1.1.8.2 nathanw hva->hdd_bufptr = 0;
143 1.1.8.2 nathanw hva->hdd_ctl = HDD_CTL_EOCHAIN;
144 1.1.8.2 nathanw hva->hdd_descptr = 0;
145 1.1.8.2 nathanw hva++;
146 1.1.8.2 nathanw #ifdef DMA_DEBUG
147 1.1.8.2 nathanw printf(">\n");
148 1.1.8.2 nathanw #endif
149 1.1.8.2 nathanw bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
150 1.1.8.2 nathanw 0, sc->sc_dmamap->dm_mapsize,
151 1.1.8.2 nathanw BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
152 1.1.8.2 nathanw
153 1.1.8.2 nathanw /* Load DMA Descriptor list */
154 1.1.8.2 nathanw bus_space_write_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_NDBP,
155 1.1.8.2 nathanw (u_int32_t)sc->sc_desc_pa);
156 1.1.8.2 nathanw }
157 1.1.8.2 nathanw
158 1.1.8.2 nathanw void
159 1.1.8.2 nathanw hpcdma_cntl(struct hpc_dma_softc *sc, uint32_t mode)
160 1.1.8.2 nathanw {
161 1.1.8.2 nathanw
162 1.1.8.2 nathanw bus_space_write_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL, mode);
163 1.1.8.2 nathanw }
164 1.1.8.2 nathanw
165 1.1.8.2 nathanw void
166 1.1.8.2 nathanw hpcdma_reset(struct hpc_dma_softc *sc)
167 1.1.8.2 nathanw {
168 1.1.8.2 nathanw
169 1.1.8.2 nathanw bus_space_write_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL,
170 1.1.8.2 nathanw HPC_DMACTL_RESET);
171 1.1.8.2 nathanw delay(100);
172 1.1.8.2 nathanw bus_space_write_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL, 0);
173 1.1.8.2 nathanw delay(1000);
174 1.1.8.2 nathanw }
175 1.1.8.2 nathanw
176 1.1.8.2 nathanw void
177 1.1.8.2 nathanw hpcdma_flush(struct hpc_dma_softc *sc)
178 1.1.8.2 nathanw {
179 1.1.8.2 nathanw u_int32_t mode;
180 1.1.8.2 nathanw
181 1.1.8.2 nathanw mode = bus_space_read_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL);
182 1.1.8.2 nathanw bus_space_write_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL,
183 1.1.8.2 nathanw mode | HPC_DMACTL_FLUSH);
184 1.1.8.2 nathanw
185 1.1.8.2 nathanw /* Wait for Active bit to drop */
186 1.1.8.2 nathanw while (bus_space_read_4(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL) &
187 1.1.8.2 nathanw HPC_DMACTL_ACTIVE) {
188 1.1.8.2 nathanw bus_space_barrier(sc->sc_bst, sc->sc_bsh, HPC_SCSI0_CTL, 4,
189 1.1.8.2 nathanw BUS_SPACE_BARRIER_READ);
190 1.1.8.2 nathanw }
191 1.1.8.2 nathanw }
192