hpcreg.h revision 1.10
1 /* $NetBSD: hpcreg.h,v 1.10 2003/12/29 06:33:57 sekiya Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Rafal K. Boni 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef _ARCH_SGIMIPS_HPC_HPCREG_H_ 31 #define _ARCH_SGIMIPS_HPC_HPCREG_H_ 32 33 /* 34 * HPC3 descriptor layout. 35 */ 36 struct hpc_dma_desc { 37 u_int32_t hdd_bufptr; /* Physical address of buffer */ 38 u_int32_t hdd_ctl; /* Control flags and byte count */ 39 u_int32_t hdd_descptr; /* Physical address of next descr. */ 40 u_int32_t hdd_pad; /* Pad out to quadword alignment */ 41 }; 42 43 /* 44 * The hdd_bufptr and hdd_ctl fields are swapped between HPC1 and 45 * HPC3. These fields are referenced by macro for readability. 46 */ 47 #define hpc1_hdd_ctl hdd_bufptr 48 #define hpc1_hdd_bufptr hdd_ctl 49 #define hpc3_hdd_ctl hdd_ctl 50 #define hpc3_hdd_bufptr hdd_bufptr 51 52 /* 53 * Control flags 54 */ 55 #define HDD_CTL_EOCHAIN 0x80000000 /* End of descriptor chain */ 56 #define HDD_CTL_EOPACKET 0x40000000 /* Ethernet: end of packet */ 57 #define HDD_CTL_INTR 0x20000000 /* Interrupt when finished */ 58 #define HDD_CTL_XMITDONE 0x00008000 /* Ethernet transmit done */ 59 #define HDD_CTL_OWN 0x00004000 /* CPU owns this frame */ 60 61 #define HDD_CTL_BYTECNT(x) ((x) & 0x3fff) /* Byte count: for ethernet 62 * rcv channel also doubles as 63 * length of packet received 64 */ 65 66 /* 67 * HPC memory map, as offsets from HPC base 68 * 69 * XXXrkb: should each section be used as a base and have the specific 70 * registers offset from there?? 71 * 72 * XXX: define register values as well as their offsets. 73 * 74 */ 75 #define HPC_PBUS_DMAREGS 0x00000000 /* DMA registers for PBus */ 76 #define HPC_PBUS_DMAREGS_SIZE 0x0000ffff /* channels 0 - 7 */ 77 78 #define HPC_PBUS_CH0_BP 0x00000000 /* Chan 0 Buffer Ptr */ 79 #define HPC_PBUS_CH0_DP 0x00000004 /* Chan 0 Descriptor Ptr */ 80 #define HPC_PBUS_CH0_CTL 0x00001000 /* Chan 0 Control Register */ 81 82 #define HPC_PBUS_CH1_BP 0x00002000 /* Chan 1 Buffer Ptr */ 83 #define HPC_PBUS_CH1_DP 0x00002004 /* Chan 1 Descriptor Ptr */ 84 #define HPC_PBUS_CH1_CTL 0x00003000 /* Chan 1 Control Register */ 85 86 #define HPC_PBUS_CH2_BP 0x00004000 /* Chan 2 Buffer Ptr */ 87 #define HPC_PBUS_CH2_DP 0x00004004 /* Chan 2 Descriptor Ptr */ 88 #define HPC_PBUS_CH2_CTL 0x00005000 /* Chan 2 Control Register */ 89 90 #define HPC_PBUS_CH3_BP 0x00006000 /* Chan 3 Buffer Ptr */ 91 #define HPC_PBUS_CH3_DP 0x00006004 /* Chan 3 Descriptor Ptr */ 92 #define HPC_PBUS_CH3_CTL 0x00007000 /* Chan 3 Control Register */ 93 94 #define HPC_PBUS_CH4_BP 0x00008000 /* Chan 4 Buffer Ptr */ 95 #define HPC_PBUS_CH4_DP 0x00008004 /* Chan 4 Descriptor Ptr */ 96 #define HPC_PBUS_CH4_CTL 0x00009000 /* Chan 4 Control Register */ 97 98 #define HPC_PBUS_CH5_BP 0x0000a000 /* Chan 5 Buffer Ptr */ 99 #define HPC_PBUS_CH5_DP 0x0000a004 /* Chan 5 Descriptor Ptr */ 100 #define HPC_PBUS_CH5_CTL 0x0000b000 /* Chan 5 Control Register */ 101 102 #define HPC_PBUS_CH6_BP 0x0000c000 /* Chan 6 Buffer Ptr */ 103 #define HPC_PBUS_CH6_DP 0x0000c004 /* Chan 6 Descriptor Ptr */ 104 #define HPC_PBUS_CH6_CTL 0x0000d000 /* Chan 6 Control Register */ 105 106 #define HPC_PBUS_CH7_BP 0x0000e000 /* Chan 7 Buffer Ptr */ 107 #define HPC_PBUS_CH7_DP 0x0000e004 /* Chan 7 Descriptor Ptr */ 108 #define HPC_PBUS_CH7_CTL 0x0000f000 /* Chan 7 Control Register */ 109 110 #define HPC_SCSI0_REGS 0x00010000 /* SCSI channel 0 registers */ 111 #define HPC_SCSI0_REGS_SIZE 0x00001fff 112 113 #define HPC_SCSI0_CBP 0x00000000 /* Current buffer ptr */ 114 #define HPC_SCSI0_NDBP 0x00000004 /* Next descriptor ptr */ 115 116 #define HPC_SCSI0_BC 0x00001000 /* DMA byte count & flags */ 117 #define HPC_SCSI0_CTL 0x00001004 /* DMA control flags */ 118 #define HPC_SCSI0_GIO 0x00001008 /* GIO DMA FIFO pointer */ 119 #define HPC_SCSI0_DEV 0x0000100c /* Device DMA FIFO pointer */ 120 #define HPC_SCSI0_DMACFG 0x00001010 /* DMA configururation */ 121 #define HPC_SCSI0_PIOCFG 0x00001014 /* PIO configururation */ 122 123 #define HPC_SCSI1_REGS 0x00012000 /* SCSI channel 1 registers */ 124 #define HPC_SCSI1_REGS_SIZE 0x00001fff 125 126 #define HPC_SCSI1_CBP 0x00000000 /* Current buffer ptr */ 127 #define HPC_SCSI1_NDBP 0x00000004 /* Next descriptor ptr */ 128 129 #define HPC_SCSI1_BC 0x00001000 /* DMA byte count & flags */ 130 #define HPC_SCSI1_CTL 0x00001004 /* DMA control flags */ 131 #define HPC_SCSI1_GIO 0x00001008 /* GIO DMA FIFO pointer */ 132 #define HPC_SCSI1_DEV 0x0000100c /* Device DMA FIFO pointer */ 133 #define HPC_SCSI1_DMACFG 0x00001010 /* DMA configururation */ 134 #define HPC_SCSI1_PIOCFG 0x00001014 /* PIO configururation */ 135 136 /* These are only valid for SCSI/ENETR, PBUS uses different definitions */ 137 #define HPC_DMACTL_IRQ 0x01 /* IRQ asserted, either dma done or parity */ 138 #define HPC_DMACTL_ENDIAN 0x02 /* DMA endian mode, 0=BE, 1=LE */ 139 #define HPC_DMACTL_DIR 0x04 /* DMA direction, 0=dev->mem, 1=mem->dev */ 140 #define HPC_DMACTL_FLUSH 0x08 /* Flush DMA FIFO's */ 141 #define HPC_DMACTL_ACTIVE 0x10 /* DMA channel is active */ 142 #define HPC_DMACTL_AMASK 0x20 /* DMA active inhibits PIO */ 143 #define HPC_DMACTL_RESET 0x40 /* Resets dma channel and external controller */ 144 #define HPC_DMACTL_PERR 0x80 /* Parity error on interface to controller */ 145 146 /* HPC_PBUS_CHx_CTL read: */ 147 #define HPC_PBUS_DMACTL_IRQ 0x01 /* IRQ asserted, DMA done */ 148 #define HPC_PBUS_DMACTL_ISACT 0x02 /* DMA channel is active */ 149 /* HPC_PBUS_CHx_CTL write: */ 150 #define HPC_PBUS_DMACTL_ENDIAN 0x02 /* DMA endianness, 0=BE 1=LE */ 151 #define HPC_PBUS_DMACTL_RECEIVE 0x04 /* DMA direction, 1=dev->mem, 0=mem->dev */ 152 #define HPC_PBUS_DMACTL_FLUSH 0x08 /* Flush DMA FIFO */ 153 #define HPC_PBUS_DMACTL_ACT 0x10 /* Activate DMA channel */ 154 #define HPC_PBUS_DMACTL_ACT_LD 0x20 /* Load enable for ACT */ 155 #define HPC_PBUS_DMACTL_RT 0x40 /* Enable real time GIO service for DMA */ 156 #define HPC_PBUS_DMACTL_HIGHWATER_SHIFT 8 157 #define HPC_PBUS_DMACTL_FIFOBEG_SHIFT 16 158 #define HPC_PBUS_DMACTL_FIFOEND_SHIFT 24 159 160 #define HPC_ENET_REGS 0x00014000 /* Ethernet registers */ 161 #define HPC_ENET_REGS_SIZE 0x00003fff 162 163 #define HPC_ENETR_CBP 0x00000000 /* Recv: Current buffer ptr */ 164 #define HPC_ENETR_NDBP 0x00000004 /* Recv: Next descriptor ptr */ 165 166 #define HPC_ENETR_BC 0x00001000 /* Recv: DMA byte cnt/flags */ 167 #define HPC_ENETR_CTL 0x00001004 /* Recv: DMA control flags */ 168 169 #define ENETR_CTL_STAT_5_0 0x003f /* Seeq irq status: bits 0-5 */ 170 #define ENETR_CTL_STAT_6 0x0040 /* Irq status: late_rxdc */ 171 #define ENETR_CTL_STAT_7 0x0080 /* Irq status: old/new bit */ 172 #define ENETR_CTL_LENDIAN 0x0100 /* DMA channel endian mode */ 173 #define ENETR_CTL_ACTIVE 0x0200 /* DMA channel active? */ 174 #define ENETR_CTL_ACTIVE_MSK 0x0400 /* DMA channel active? */ 175 #define ENETR_CTL_RBO 0x0800 /* Recv buffer overflow */ 176 177 #define HPC_ENETR_GIO 0x00001008 /* Recv: GIO DMA FIFO ptr */ 178 #define HPC_ENETR_DEV 0x0000100c /* Recv: Device DMA FIFO ptr */ 179 #define HPC_ENETR_RESET 0x00001014 /* Recv: Ethernet chip reset */ 180 181 #define ENETR_RESET_CH 0x0001 /* Reset controller & chan */ 182 #define ENETR_RESET_CLRINT 0x0002 /* Clear channel interrupt */ 183 #define ENETR_RESET_LOOPBK 0x0004 /* External loopback enable */ 184 #define ENETR_RESET_CLRRBO 0x0008 /* Clear RBO condition (??) */ 185 186 #define HPC_ENETR_DMACFG 0x00001018 /* Recv: DMA configururation */ 187 188 #define ENETR_DMACFG_D1 0x0000f /* DMA D1 state cycles */ 189 #define ENETR_DMACFG_D2 0x000f0 /* DMA D2 state cycles */ 190 #define ENETR_DMACFG_D3 0x00f00 /* DMA D3 state cycles */ 191 #define ENETR_DMACFG_WRCTL 0x01000 /* Enable IPG write */ 192 193 /* 194 * The following three bits work around bugs in the Seeq 8003; if you 195 * don't set them, the Seeq gets wonky pretty often. 196 */ 197 #define ENETR_DMACFG_FIX_RXDC 0x02000 /* Clear EOP bits on RXDC */ 198 #define ENETR_DMACFG_FIX_EOP 0x04000 /* Enable rxintr timeout */ 199 #define ENETR_DMACFG_FIX_INTR 0x08000 /* Enable EOP timeout */ 200 #define ENETR_DMACFG_TIMO 0x30000 /* Timeout for above two */ 201 202 #define HPC_ENETR_PIOCFG 0x0000101c /* Recv: PIO configururation */ 203 204 #define HPC_ENETX_CBP 0x00002000 /* Xmit: Current buffer ptr */ 205 #define HPC_ENETX_NDBP 0x00002004 /* Xmit: Next descriptor ptr */ 206 207 #define HPC_ENETX_BC 0x00003000 /* Xmit: DMA byte cnt/flags */ 208 #define HPC_ENETX_CTL 0x00003004 /* Xmit: DMA control flags */ 209 210 #define ENETX_CTL_STAT_5_0 0x003f /* Seeq irq status: bits 0-5 */ 211 #define ENETX_CTL_STAT_6 0x0040 /* Irq status: late_rxdc */ 212 #define ENETX_CTL_STAT_7 0x0080 /* Irq status: old/new bit */ 213 #define ENETX_CTL_LENDIAN 0x0100 /* DMA channel endian mode */ 214 #define ENETX_CTL_ACTIVE 0x0200 /* DMA channel active? */ 215 #define ENETX_CTL_ACTIVE_MSK 0x0400 /* DMA channel active? */ 216 #define ENETX_CTL_RBO 0x0800 /* Recv buffer overflow */ 217 218 #define HPC_ENETX_GIO 0x00003008 /* Xmit: GIO DMA FIFO ptr */ 219 #define HPC_ENETX_DEV 0x0000300c /* Xmit: Device DMA FIFO ptr */ 220 221 #define HPC_PBUS_FIFO 0x00020000 /* PBus DMA FIFO */ 222 #define HPC_PBUS_FIFO_SIZE 0x00007fff /* PBus DMA FIFO size */ 223 224 #define HPC_SCSI0_FIFO 0x00028000 /* SCSI0 DMA FIFO */ 225 #define HPC_SCSI0_FIFO_SIZE 0x00001fff /* SCSI0 DMA FIFO size */ 226 227 #define HPC_SCSI1_FIFO 0x0002a000 /* SCSI1 DMA FIFO */ 228 #define HPC_SCSI1_FIFO_SIZE 0x00001fff /* SCSI1 DMA FIFO size */ 229 230 #define HPC_ENETR_FIFO 0x0002c000 /* Ether recv DMA FIFO */ 231 #define HPC_ENETR_FIFO_SIZE 0x00001fff /* Ether recv DMA FIFO size */ 232 233 #define HPC_ENETX_FIFO 0x0002e000 /* Ether xmit DMA FIFO */ 234 #define HPC_ENETX_FIFO_SIZE 0x00001fff /* Ether xmit DMA FIFO size */ 235 236 /* 237 * HPCBUG: The interrupt status is split amongst two registers, and they're 238 * not even consecutive in the HPC address space. This is documented as a 239 * bug by SGI. 240 */ 241 #define HPC_INTRSTAT_40 0x00030000 /* Interrupt stat, bits 4:0 */ 242 #define HPC_INTRSTAT_95 0x0003000c /* Interrupt stat, bits 9:5 */ 243 244 #define HPC_GIO_MISC 0x00030004 /* GIO64 misc register */ 245 246 #define HPC_EEPROM_DATA 0x00030008 /* Serial EEPROM data reg. */ 247 248 #define HPC_GIO_BUSERR 0x00030010 /* GIO64 bus error intr stat */ 249 250 #define HPC_SCSI0_DEVREGS 0x00044000 /* SCSI channel 0 chip regs */ 251 #define HPC_SCSI0_DEVREGS_SIZE 0x000003ff /* Size of chip registers */ 252 253 #define HPC_SCSI1_DEVREGS 0x0004c000 /* SCSI channel 1 chip regs */ 254 #define HPC_SCSI1_DEVREGS_SIZE 0x000003ff /* Size of chip registers */ 255 256 #define HPC_ENET_DEVREGS 0x00054000 /* Ethernet chip registers */ 257 #define HPC_ENET_DEVREGS_SIZE 0x000004ff /* Size of chip registers */ 258 259 #define HPC_PBUS_DEVREGS 0x00054000 /* PBus PIO chip registers */ 260 #define HPC_PBUS_DEVREGS_SIZE 0x000003ff /* PBus PIO chip registers */ 261 262 #define HPC_PBUS_CH0_DEVREGS 0x00058000 /* PBus ch. 0 chip registers */ 263 #define HPC_PBUS_CH0_DEVREGS_SIZE 0x03ff 264 265 #define HPC_PBUS_CH1_DEVREGS 0x00058400 /* PBus ch. 1 chip registers */ 266 #define HPC_PBUS_CH1_DEVREGS_SIZE 0x03ff 267 268 #define HPC_PBUS_CH2_DEVREGS 0x00058800 /* PBus ch. 2 chip registers */ 269 #define HPC_PBUS_CH2_DEVREGS_SIZE 0x03ff 270 271 #define HPC_PBUS_CH3_DEVREGS 0x00058c00 /* PBus ch. 3 chip registers */ 272 #define HPC_PBUS_CH3_DEVREGS_SIZE 0x03ff 273 274 #define HPC_PBUS_CH4_DEVREGS 0x00059000 /* PBus ch. 4 chip registers */ 275 #define HPC_PBUS_CH4_DEVREGS_SIZE 0x03ff 276 277 #define HPC_PBUS_CH5_DEVREGS 0x00059400 /* PBus ch. 5 chip registers */ 278 #define HPC_PBUS_CH5_DEVREGS_SIZE 0x03ff 279 280 #define HPC_PBUS_CH6_DEVREGS 0x00059800 /* PBus ch. 6 chip registers */ 281 #define HPC_PBUS_CH6_DEVREGS_SIZE 0x03ff 282 283 #define HPC_PBUS_CH7_DEVREGS 0x00059c00 /* PBus ch. 7 chip registers */ 284 #define HPC_PBUS_CH7_DEVREGS_SIZE 0x03ff 285 286 #define HPC_PBUS_CH8_DEVREGS 0x0005a000 /* PBus ch. 8 chip registers */ 287 #define HPC_PBUS_CH8_DEVREGS_SIZE 0x03ff 288 289 #define HPC_PBUS_CH9_DEVREGS 0x0005a400 /* PBus ch. 9 chip registers */ 290 #define HPC_PBUS_CH9_DEVREGS_SIZE 0x03ff 291 292 #define HPC_PBUS_CH8_DEVREGS_2 0x0005a800 /* PBus ch. 8 chip registers */ 293 #define HPC_PBUS_CH8_DEVREGS_2_SIZE 0x03ff 294 295 #define HPC_PBUS_CH9_DEVREGS_2 0x0005ac00 /* PBus ch. 9 chip registers */ 296 #define HPC_PBUS_CH9_DEVREGS_2_SIZE 0x03ff 297 298 #define HPC_PBUS_CH8_DEVREGS_3 0x0005b000 /* PBus ch. 8 chip registers */ 299 #define HPC_PBUS_CH8_DEVREGS_3_SIZE 0x03ff 300 301 #define HPC_PBUS_CH9_DEVREGS_3 0x0005b400 /* PBus ch. 9 chip registers */ 302 #define HPC_PBUS_CH9_DEVREGS_3_SIZE 0x03ff 303 304 #define HPC_PBUS_CH8_DEVREGS_4 0x0005b800 /* PBus ch. 8 chip registers */ 305 #define HPC_PBUS_CH8_DEVREGS_4_SIZE 0x03ff 306 307 #define HPC_PBUS_CH9_DEVREGS_4 0x0005bc00 /* PBus ch. 9 chip registers */ 308 #define HPC_PBUS_CH9_DEVREGS_4_SIZE 0x03ff 309 310 #define HPC_PBUS_CFGDMA_REGS 0x0005c000 /* PBus DMA config registers */ 311 #define HPC_PBUS_CFGDMA_REGS_SIZE 0x0fff 312 313 #define HPC_PBUS_CH0_CFGDMA 0x0005c000 /* PBus Ch. 0 DMA config */ 314 #define HPC_PBUS_CH0_CFGDMA_SIZE 0x01ff 315 316 #define HPC_PBUS_CH1_CFGDMA 0x0005c200 /* PBus Ch. 1 DMA config */ 317 #define HPC_PBUS_CH1_CFGDMA_SIZE 0x01ff 318 319 #define HPC_PBUS_CH2_CFGDMA 0x0005c400 /* PBus Ch. 2 DMA config */ 320 #define HPC_PBUS_CH2_CFGDMA_SIZE 0x01ff 321 322 #define HPC_PBUS_CH3_CFGDMA 0x0005c600 /* PBus Ch. 3 DMA config */ 323 #define HPC_PBUS_CH3_CFGDMA_SIZE 0x01ff 324 325 #define HPC_PBUS_CH4_CFGDMA 0x0005c800 /* PBus Ch. 4 DMA config */ 326 #define HPC_PBUS_CH4_CFGDMA_SIZE 0x01ff 327 328 #define HPC_PBUS_CH5_CFGDMA 0x0005ca00 /* PBus Ch. 5 DMA config */ 329 #define HPC_PBUS_CH5_CFGDMA_SIZE 0x01ff 330 331 #define HPC_PBUS_CH6_CFGDMA 0x0005cc00 /* PBus Ch. 6 DMA config */ 332 #define HPC_PBUS_CH6_CFGDMA_SIZE 0x01ff 333 334 #define HPC_PBUS_CH7_CFGDMA 0x0005ce00 /* PBus Ch. 7 DMA config */ 335 #define HPC_PBUS_CH7_CFGDMA_SIZE 0x01ff 336 337 #define HPC_PBUS_CFGPIO_REGS 0x0005d000 /* PBus PIO config registers */ 338 #define HPC_PBUS_CFGPIO_REGS_SIZE 0x0fff 339 340 #define HPC_PBUS_CH0_CFGPIO 0x0005d000 /* PBus Ch. 0 PIO config */ 341 #define HPC_PBUS_CH1_CFGPIO 0x0005d100 /* PBus Ch. 1 PIO config */ 342 #define HPC_PBUS_CH2_CFGPIO 0x0005d200 /* PBus Ch. 2 PIO config */ 343 #define HPC_PBUS_CH3_CFGPIO 0x0005d300 /* PBus Ch. 3 PIO config */ 344 #define HPC_PBUS_CH4_CFGPIO 0x0005d400 /* PBus Ch. 4 PIO config */ 345 #define HPC_PBUS_CH5_CFGPIO 0x0005d500 /* PBus Ch. 5 PIO config */ 346 #define HPC_PBUS_CH6_CFGPIO 0x0005d600 /* PBus Ch. 6 PIO config */ 347 #define HPC_PBUS_CH7_CFGPIO 0x0005d700 /* PBus Ch. 7 PIO config */ 348 #define HPC_PBUS_CH8_CFGPIO 0x0005d800 /* PBus Ch. 8 PIO config */ 349 #define HPC_PBUS_CH9_CFGPIO 0x0005d900 /* PBus Ch. 9 PIO config */ 350 #define HPC_PBUS_CH8_CFGPIO_2 0x0005da00 /* PBus Ch. 8 PIO config */ 351 #define HPC_PBUS_CH9_CFGPIO_2 0x0005db00 /* PBus Ch. 9 PIO config */ 352 #define HPC_PBUS_CH8_CFGPIO_3 0x0005dc00 /* PBus Ch. 8 PIO config */ 353 #define HPC_PBUS_CH9_CFGPIO_3 0x0005dd00 /* PBus Ch. 9 PIO config */ 354 #define HPC_PBUS_CH8_CFGPIO_4 0x0005de00 /* PBus Ch. 8 PIO config */ 355 #define HPC_PBUS_CH9_CFGPIO_4 0x0005df00 /* PBus Ch. 9 PIO config */ 356 357 #define HPC_PBUS_PROM_WE 0x0005e000 /* PBus boot-prom write 358 * enable register 359 */ 360 361 #define HPC_PBUS_PROM_SWAP 0x0005e800 /* PBus boot-prom chip-select 362 * swap register 363 */ 364 365 #define HPC_PBUS_GEN_OUT 0x0005f000 /* PBus general-purpose output 366 * register 367 */ 368 369 #define HPC_PBUS_BBRAM 0x00060000 /* PBus battery-backed RAM 370 * external registers 371 */ 372 373 /* HPC1/HPC1.5 differs from HPC3 in several details. */ 374 375 #define HPC1_HDD_CTL_EOCHAIN 0x80000000 /* End of descriptor chain */ 376 #define HPC1_HDD_CTL_EOPACKET 0x80000000 /* Ethernet: end of packet */ 377 #define HPC1_HDD_CTL_INTR 0x00008000 /* Interrupt when finished */ 378 #define HPC1_HDD_CTL_OWN 0x40000000 /* CPU owns this frame */ 379 #define HPC1_HDD_CTL_BYTECNT(x) ((x) & 0x1fff) /* Byte count: for ethernet */ 380 #define HPC1_BIGENDIAN 0x000000c0 /* Endianness:5 revision:2 */ 381 #define HPC1_REVSHIFT 0x00000006 /* Revision rshft */ 382 #define HPC1_REVMASK 0x00000003 /* Revision mask */ 383 #define HPC1_REV15 0x00000001 /* HPC Revision 1.5 */ 384 #define HPC1_SCSI0_REGS 0x00000088 385 #define HPC1_SCSI0_REGS_SIZE 0x00000018 386 #define HPC1_SCSI0_CBP 0x00000004 /* Current buffer ptr */ 387 #define HPC1_SCSI0_NDBP 0x00000008 /* Next descriptor ptr */ 388 #define HPC1_SCSI0_BC 0x00000000 /* DMA byte count & flags */ 389 #define HPC1_SCSI0_CTL 0x0000000c /* DMA control flags */ 390 #define HPC1_SCSI0_DEV 0x00000014 /* Device DMA FIFO pointer */ 391 #define HPC1_SCSI0_DMACFG 0x00000010 /* DMA configuration */ 392 #define HPC1_SCSI0_GIO 0x00001008 /* GIO DMA FIFO pointer */ 393 #define HPC1_SCSI0_PIOCFG 0x00001014 /* PIO configuration */ 394 #define HPC1_SCSI1_REGS 0x00012000 /* SCSI channel 1 registers */ 395 #define HPC1_SCSI1_REGS_SIZE 0x00001fff 396 #define HPC1_SCSI1_CBP 0x00000000 /* Current buffer ptr */ 397 #define HPC1_SCSI1_NDBP 0x00000004 /* Next descriptor ptr */ 398 #define HPC1_SCSI1_BC 0x00001000 /* DMA byte count & flags */ 399 #define HPC1_SCSI1_CTL 0x00001004 /* DMA control flags */ 400 #define HPC1_SCSI1_GIO 0x00001008 /* GIO DMA FIFO pointer */ 401 #define HPC1_SCSI1_DEV 0x0000100c /* Device DMA FIFO pointer */ 402 #define HPC1_SCSI1_DMACFG 0x00001010 /* DMA configuration */ 403 #define HPC1_SCSI1_PIOCFG 0x00001014 /* PIO configuration */ 404 #define HPC1_DMACTL_RESET 0x01 /* Resets dma channel and external controller */ 405 #define HPC1_DMACTL_FLUSH 0x02 /* Flush DMA FIFO's */ 406 #define HPC1_DMACTL_DIR 0x10 /* DMA direction ~HPC3: 1=dev->mem, 0=mem->dev */ 407 #define HPC1_DMACTL_ACTIVE 0x80 /* DMA channel is active */ 408 #define HPC1_ENET_REGS 0x00000000 /* Ethernet registers */ 409 #define HPC1_ENET_REGS_SIZE 0x00000100 410 #define HPC1_ENET_INTDELAY 0x0000002c /* Interrupt Delay Count */ 411 #define HPC1_ENET_INTDELAYVAL 0x01000000 412 #define HPC1_ENETR_CBP 0x00000054 /* Recv: Current buffer ptr */ 413 #define HPC1_ENETR_NDBP 0x00000050 /* Recv: Next descriptor ptr */ 414 #define HPC1_ENETR_BC 0x00000048 /* Recv: DMA byte cnt/flags */ 415 #define HPC1_ENETR_CTL 0x00000038 /* Recv: DMA control flags */ 416 #define HPC1_ENETR_CTL_ACTIVE 0x00004000 /* DMA channel active? */ 417 #define HPC1_ENETR_RESET 0x0000003c /* Recv: Ethernet chip reset */ 418 #define HPC1_ENETR_RESET_CH 0x0001 /* Reset controller & chan */ 419 #define HPC1_ENETR_RESET_CLRINT 0x0002 /* Clear channel interrupt */ 420 #define HPC1_ENETR_RESET_LOOPBK 0x0004 /* External loopback enable */ 421 #define HPC1_ENETR_RESET_CLRRBO 0x0008 /* Clear RBO condition (??) */ 422 #define HPC1_ENETR_PIOCFG 0x0000101c /* Recv: PIO configuration */ 423 #define HPC1_ENETX_CBP 0x00000020 /* Xmit: Current buffer ptr */ 424 #define HPC1_ENETX_NDBP 0x00000010 /* Xmit: Next descriptor ptr */ 425 #define HPC1_ENETX_CFXBP 0x00000024 /* Xmit: Current first buf */ 426 #define HPC1_ENETX_PFXBP 0x00000028 /* Xmit: Prev. first buf */ 427 #define HPC1_ENETX_BC 0x00000014 /* Xmit: DMA byte cnt/flags */ 428 #define HPC1_ENETX_CTL 0x00000034 /* Xmit: DMA control flags */ 429 #define HPC1_ENETX_CTL_ACTIVE 0x00400000 430 #define HPC1_ENETX_GIO 0x00003008 /* Xmit: GIO DMA FIFO ptr */ 431 #define HPC1_ENETX_DEV 0x0000300c /* Xmit: Device DMA FIFO ptr */ 432 #define HPC1_PBUS_FIFO 0x00020000 /* PBus DMA FIFO */ 433 #define HPC1_PBUS_FIFO_SIZE 0x00007fff /* PBus DMA FIFO size */ 434 #define HPC1_ENETR_FIFO 0x0002c000 /* Ether recv DMA FIFO */ 435 #define HPC1_ENETR_FIFO_SIZE 0x00001fff /* Ether recv DMA FIFO size */ 436 #define HPC1_ENETX_FIFO 0x0002e000 /* Ether xmit DMA FIFO */ 437 #define HPC1_ENETX_FIFO_SIZE 0x00001fff /* Ether xmit DMA FIFO size */ 438 #define HPC1_SCSI0_DEVREGS 0x0000011f 439 #define HPC1_SCSI0_DEVREGS_SIZE 0x00000008 440 #define HPC1_ENET_DEVREGS 0x00000100 /* Ethernet chip registers */ 441 #define HPC1_ENET_DEVREGS_SIZE 0x00000020 /* Size of chip registers */ 442 #define HPC1_PBUS_BBRAM 0x00000e00 /* PBus battery-backed RAM */ 443 #define HPC1_LPT_REGS 0x000000a8 /* LPT HPC Registers */ 444 #define HPC1_LPT_REGS_SIZE 0x00000018 445 #define HPC1_LPT_BC 0x00000000 /* Byte Count */ 446 #define HPC1_LPT_CBP 0x00000004 /* Current Buffer Ptr */ 447 #define HPC1_LPT_NDBP 0x00000008 /* Next Buffer Ptr */ 448 #define HPC1_LPT_CTL 0x0000000c /* DMA Control Flags */ 449 #define HPC1_LPT_DEV 0x00000010 /* DMA Fifo Ptr */ 450 #define HPC1_LPT_DMACFG 0x00000014 /* DMA Configuration */ 451 #define HPC1_LPT_DEVREGS 0x00000132 /* Ext. Parallel Registers */ 452 #define HPC1_LPT_DEVREGS_SIZE 0x00000001 /* Size of External Registers */ 453 #define HPC1_AUX_REGS 0x1fb801bc /* Serial EEPROM/LED Control */ 454 #define HPC1_AUX_REGS_SIZE 0x00000001 /* One Byte */ 455 #define HPC1_AUX_CONSLED 0x01 /* Console LED */ 456 457 #endif /* _ARCH_SGIMIPS_HPC_HPCREG_H_ */ 458
Indexes created Wed Sep 24 05:09:52 GMT 2025