hpcreg.h revision 1.2
1 /* $NetBSD: hpcreg.h,v 1.2 2001/06/07 12:10:34 rafal Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Rafal K. Boni 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef _ARCH_SGIMIPS_HPC_HPCREG_H_ 31 #define _ARCH_SGIMIPS_HPC_HPCREG_H_ 32 33 struct hpc_dma_desc { 34 u_int32_t hdd_bufptr; /* Physical address of buffer */ 35 u_int32_t hdd_ctl; /* Control flags and byte count */ 36 u_int32_t hdd_descptr; /* Physical address of next descr. */ 37 u_int32_t hdd_pad; /* Pad out to quadword alignment */ 38 }; 39 40 /* 41 * Control flags 42 */ 43 #define HDD_CTL_EOCHAIN 0x80000000 /* End of descriptor chain */ 44 #define HDD_CTL_EOPACKET 0x40000000 /* Ethernet: end of packet */ 45 #define HDD_CTL_INTR 0x20000000 /* Interrupt when finished */ 46 #define HDD_CTL_XMITDONE 0x00008000 /* Ethernet transmit done */ 47 #define HDD_CTL_OWN 0x00004000 /* CPU owns this frame */ 48 49 #define HDD_CTL_BYTECNT(x) ((x) & 0x3fff) /* Byte count: for ethernet 50 * rcv channel also doubles as 51 * length of packet received 52 */ 53 54 /* 55 * HPC memory map, as offsets from HPC base 56 * 57 * XXXrkb: should each section be used as a base and have the specific 58 * registers offset from there?? 59 * 60 * XXX: define register values as well as their offsets. 61 * 62 */ 63 #define HPC_PBUS_DMAREGS 0x00000000 /* DMA registers for PBus */ 64 #define HPC_PBUS_DMAREGS_SIZE 0x0000ffff /* channels 0 - 7 */ 65 66 #define HPC_PBUS_CH0_BP 0x00000004 /* Chan 0 Buffer Ptr */ 67 #define HPC_PBUS_CH0_DP 0x00000008 /* Chan 0 Descriptor Ptr */ 68 #define HPC_PBUS_CH0_CTL 0x00001000 /* Chan 0 Control Register */ 69 70 #define HPC_PBUS_CH1_BP 0x00002004 /* Chan 1 Buffer Ptr */ 71 #define HPC_PBUS_CH1_DP 0x00002008 /* Chan 1 Descriptor Ptr */ 72 #define HPC_PBUS_CH1_CTL 0x00003000 /* Chan 1 Control Register */ 73 74 #define HPC_PBUS_CH2_BP 0x00004004 /* Chan 2 Buffer Ptr */ 75 #define HPC_PBUS_CH2_DP 0x00004008 /* Chan 2 Descriptor Ptr */ 76 #define HPC_PBUS_CH2_CTL 0x00005000 /* Chan 2 Control Register */ 77 78 #define HPC_PBUS_CH3_BP 0x00006004 /* Chan 3 Buffer Ptr */ 79 #define HPC_PBUS_CH3_DP 0x00006008 /* Chan 3 Descriptor Ptr */ 80 #define HPC_PBUS_CH3_CTL 0x00007000 /* Chan 3 Control Register */ 81 82 #define HPC_PBUS_CH4_BP 0x00008004 /* Chan 4 Buffer Ptr */ 83 #define HPC_PBUS_CH4_DP 0x00008008 /* Chan 4 Descriptor Ptr */ 84 #define HPC_PBUS_CH4_CTL 0x00009000 /* Chan 4 Control Register */ 85 86 #define HPC_PBUS_CH5_BP 0x0000a004 /* Chan 5 Buffer Ptr */ 87 #define HPC_PBUS_CH5_DP 0x0000a008 /* Chan 5 Descriptor Ptr */ 88 #define HPC_PBUS_CH5_CTL 0x0000b000 /* Chan 5 Control Register */ 89 90 #define HPC_PBUS_CH6_BP 0x0000c004 /* Chan 6 Buffer Ptr */ 91 #define HPC_PBUS_CH6_DP 0x0000c008 /* Chan 6 Descriptor Ptr */ 92 #define HPC_PBUS_CH6_CTL 0x0000d000 /* Chan 6 Control Register */ 93 94 #define HPC_PBUS_CH7_BP 0x0000e004 /* Chan 7 Buffer Ptr */ 95 #define HPC_PBUS_CH7_DP 0x0000e008 /* Chan 7 Descriptor Ptr */ 96 #define HPC_PBUS_CH7_CTL 0x0000f000 /* Chan 7 Control Register */ 97 98 #define HPC_SCSI0_REGS 0x00010000 /* SCSI channel 0 registers */ 99 #define HPC_SCSI0_REGS_SIZE 0x00001fff 100 101 #define HPC_SCSI0_CBP 0x00000000 /* Current buffer ptr */ 102 #define HPC_SCSI0_NDBP 0x00000004 /* Next descriptor ptr */ 103 104 #define HPC_SCSI0_BC 0x00001000 /* DMA byte count & flags */ 105 #define HPC_SCSI0_CTL 0x00001004 /* DMA control flags */ 106 #define HPC_SCSI0_GIO 0x00001008 /* GIO DMA FIFO pointer */ 107 #define HPC_SCSI0_DEV 0x0000100c /* Device DMA FIFO pointer */ 108 #define HPC_SCSI0_DMACFG 0x00001010 /* DMA configururation */ 109 #define HPC_SCSI0_PIOCFG 0x00001014 /* PIO configururation */ 110 111 #define HPC_SCSI1_REGS 0x00012000 /* SCSI channel 1 registers */ 112 #define HPC_SCSI1_REGS_SIZE 0x00001fff 113 114 #define HPC_SCSI1_CBP 0x00000000 /* Current buffer ptr */ 115 #define HPC_SCSI1_NDBP 0x00000004 /* Next descriptor ptr */ 116 117 #define HPC_SCSI1_BC 0x00001000 /* DMA byte count & flags */ 118 #define HPC_SCSI1_CTL 0x00001004 /* DMA control flags */ 119 #define HPC_SCSI1_GIO 0x00001008 /* GIO DMA FIFO pointer */ 120 #define HPC_SCSI1_DEV 0x0000100c /* Device DMA FIFO pointer */ 121 #define HPC_SCSI1_DMACFG 0x00001010 /* DMA configururation */ 122 #define HPC_SCSI1_PIOCFG 0x00001014 /* PIO configururation */ 123 124 #define HPC_ENET_REGS 0x00014000 /* Ethernet registers */ 125 #define HPC_ENET_REGS_SIZE 0x00003fff 126 127 #define HPC_ENETR_CBP 0x00000000 /* Recv: Current buffer ptr */ 128 #define HPC_ENETR_NDBP 0x00000004 /* Recv: Next descriptor ptr */ 129 130 #define HPC_ENETR_BC 0x00001000 /* Recv: DMA byte cnt/flags */ 131 #define HPC_ENETR_CTL 0x00001004 /* Recv: DMA control flags */ 132 133 #define ENETR_CTL_STAT_5_0 0x003f /* Seeq irq status: bits 0-5 */ 134 #define ENETR_CTL_STAT_6 0x0040 /* Irq status: late_rxdc */ 135 #define ENETR_CTL_STAT_7 0x0080 /* Irq status: old/new bit */ 136 #define ENETR_CTL_LENDIAN 0x0100 /* DMA channel endian mode */ 137 #define ENETR_CTL_ACTIVE 0x0200 /* DMA channel active? */ 138 #define ENETR_CTL_ACTIVE_MSK 0x0400 /* DMA channel active? */ 139 #define ENETR_CTL_RBO 0x0800 /* Recv buffer overflow */ 140 141 #define HPC_ENETR_GIO 0x00001008 /* Recv: GIO DMA FIFO ptr */ 142 #define HPC_ENETR_DEV 0x0000100c /* Recv: Device DMA FIFO ptr */ 143 #define HPC_ENETR_RESET 0x00001014 /* Recv: Ethernet chip reset */ 144 145 #define ENETR_RESET_CH 0x0001 /* Reset controller & chan */ 146 #define ENETR_RESET_CLRINT 0x0002 /* Clear channel interrupt */ 147 #define ENETR_RESET_LOOPBK 0x0004 /* External loopback enable */ 148 #define ENETR_RESET_CLRRBO 0x0008 /* Clear RBO condition (??) */ 149 150 #define HPC_ENETR_DMACFG 0x00001018 /* Recv: DMA configururation */ 151 152 #define ENETR_DMACFG_D1 0x0000f /* DMA D1 state cycles */ 153 #define ENETR_DMACFG_D2 0x000f0 /* DMA D2 state cycles */ 154 #define ENETR_DMACFG_D3 0x00f00 /* DMA D3 state cycles */ 155 #define ENETR_DMACFG_WRCTL 0x01000 /* Enable IPG write */ 156 157 /* 158 * The following three bits work around bugs in the Seeq 8003; if you 159 * don't set them, the Seeq gets wonky pretty often. 160 */ 161 #define ENETR_DMACFG_FIX_RXDC 0x02000 /* Clear EOP bits on RXDC */ 162 #define ENETR_DMACFG_FIX_EOP 0x04000 /* Enable rxintr timeout */ 163 #define ENETR_DMACFG_FIX_INTR 0x08000 /* Enable EOP timeout */ 164 #define ENETR_DMACFG_TIMO 0x30000 /* Timeout for above two */ 165 166 #define HPC_ENETR_PIOCFG 0x0000101c /* Recv: PIO configururation */ 167 168 #define HPC_ENETX_CBP 0x00002000 /* Xmit: Current buffer ptr */ 169 #define HPC_ENETX_NDBP 0x00002004 /* Xmit: Next descriptor ptr */ 170 171 #define HPC_ENETX_BC 0x00003000 /* Xmit: DMA byte cnt/flags */ 172 #define HPC_ENETX_CTL 0x00003004 /* Xmit: DMA control flags */ 173 174 #define ENETX_CTL_STAT_5_0 0x003f /* Seeq irq status: bits 0-5 */ 175 #define ENETX_CTL_STAT_6 0x0040 /* Irq status: late_rxdc */ 176 #define ENETX_CTL_STAT_7 0x0080 /* Irq status: old/new bit */ 177 #define ENETX_CTL_LENDIAN 0x0100 /* DMA channel endian mode */ 178 #define ENETX_CTL_ACTIVE 0x0200 /* DMA channel active? */ 179 #define ENETX_CTL_ACTIVE_MSK 0x0400 /* DMA channel active? */ 180 #define ENETX_CTL_RBO 0x0800 /* Recv buffer overflow */ 181 182 #define HPC_ENETX_GIO 0x00003008 /* Xmit: GIO DMA FIFO ptr */ 183 #define HPC_ENETX_DEV 0x0000300c /* Xmit: Device DMA FIFO ptr */ 184 185 #define HPC_PBUS_FIFO 0x00020000 /* PBus DMA FIFO */ 186 #define HPC_PBUS_FIFO_SIZE 0x00007fff /* PBus DMA FIFO size */ 187 188 #define HPC_SCSI0_FIFO 0x00028000 /* SCSI0 DMA FIFO */ 189 #define HPC_SCSI0_FIFO_SIZE 0x00001fff /* SCSI0 DMA FIFO size */ 190 191 #define HPC_SCSI1_FIFO 0x0002a000 /* SCSI1 DMA FIFO */ 192 #define HPC_SCSI1_FIFO_SIZE 0x00001fff /* SCSI1 DMA FIFO size */ 193 194 #define HPC_ENETR_FIFO 0x0002c000 /* Ether recv DMA FIFO */ 195 #define HPC_ENETR_FIFO_SIZE 0x00001fff /* Ether recv DMA FIFO size */ 196 197 #define HPC_ENETX_FIFO 0x0002e000 /* Ether xmit DMA FIFO */ 198 #define HPC_ENETX_FIFO_SIZE 0x00001fff /* Ether xmit DMA FIFO size */ 199 200 /* 201 * HPCBUG: The interrupt status is split amongst two registers, and they're 202 * not even consecutive in the HPC address space. This is documented as a 203 * bug by SGI. 204 */ 205 #define HPC_INTRSTAT_40 0x00030000 /* Interrupt stat, bits 4:0 */ 206 #define HPC_INTRSTAT_95 0x0003000c /* Interrupt stat, bits 9:5 */ 207 208 #define HPC_GIO_MISC 0x00030004 /* GIO64 misc register */ 209 210 #define HPC_EEPROM_DATA 0x00030008 /* Serial EEPROM data reg. */ 211 212 #define HPC_GIO_BUSERR 0x00030010 /* GIO64 bus error intr stat */ 213 214 #define HPC_SCSI0_DEVREGS 0x00044000 /* SCSI channel 0 chip regs */ 215 #define HPC_SCSI0_DEVREGS_SIZE 0x000003ff /* Size of chip registers */ 216 217 #define HPC_SCSI1_DEVREGS 0x0004c000 /* SCSI channel 1 chip regs */ 218 #define HPC_SCSI1_DEVREGS_SIZE 0x000003ff /* Size of chip registers */ 219 220 #define HPC_ENET_DEVREGS 0x00054000 /* Ethernet chip registers */ 221 #define HPC_ENET_DEVREGS_SIZE 0x000004ff /* Size of chip registers */ 222 223 #define HPC_PBUS_DEVREGS 0x00054000 /* PBus PIO chip registers */ 224 #define HPC_PBUS_DEVREGS_SIZE 0x000003ff /* PBus PIO chip registers */ 225 226 #define HPC_PBUS_CH0_DEVREGS 0x00058000 /* PBus ch. 0 chip registers */ 227 #define HPC_PBUS_CH0_DEVREGS_SIZE 0x03ff 228 229 #define HPC_PBUS_CH1_DEVREGS 0x00058400 /* PBus ch. 1 chip registers */ 230 #define HPC_PBUS_CH1_DEVREGS_SIZE 0x03ff 231 232 #define HPC_PBUS_CH2_DEVREGS 0x00058800 /* PBus ch. 2 chip registers */ 233 #define HPC_PBUS_CH2_DEVREGS_SIZE 0x03ff 234 235 #define HPC_PBUS_CH3_DEVREGS 0x00058c00 /* PBus ch. 3 chip registers */ 236 #define HPC_PBUS_CH3_DEVREGS_SIZE 0x03ff 237 238 #define HPC_PBUS_CH4_DEVREGS 0x00059000 /* PBus ch. 4 chip registers */ 239 #define HPC_PBUS_CH4_DEVREGS_SIZE 0x03ff 240 241 #define HPC_PBUS_CH5_DEVREGS 0x00059400 /* PBus ch. 5 chip registers */ 242 #define HPC_PBUS_CH5_DEVREGS_SIZE 0x03ff 243 244 #define HPC_PBUS_CH6_DEVREGS 0x00059800 /* PBus ch. 6 chip registers */ 245 #define HPC_PBUS_CH6_DEVREGS_SIZE 0x03ff 246 247 #define HPC_PBUS_CH7_DEVREGS 0x00059c00 /* PBus ch. 7 chip registers */ 248 #define HPC_PBUS_CH7_DEVREGS_SIZE 0x03ff 249 250 #define HPC_PBUS_CH8_DEVREGS 0x0005a000 /* PBus ch. 8 chip registers */ 251 #define HPC_PBUS_CH8_DEVREGS_SIZE 0x03ff 252 253 #define HPC_PBUS_CH9_DEVREGS 0x0005a400 /* PBus ch. 9 chip registers */ 254 #define HPC_PBUS_CH9_DEVREGS_SIZE 0x03ff 255 256 #define HPC_PBUS_CH8_DEVREGS_2 0x0005a800 /* PBus ch. 8 chip registers */ 257 #define HPC_PBUS_CH8_DEVREGS_2_SIZE 0x03ff 258 259 #define HPC_PBUS_CH9_DEVREGS_2 0x0005ac00 /* PBus ch. 9 chip registers */ 260 #define HPC_PBUS_CH9_DEVREGS_2_SIZE 0x03ff 261 262 #define HPC_PBUS_CH8_DEVREGS_3 0x0005b000 /* PBus ch. 8 chip registers */ 263 #define HPC_PBUS_CH8_DEVREGS_3_SIZE 0x03ff 264 265 #define HPC_PBUS_CH9_DEVREGS_3 0x0005b400 /* PBus ch. 9 chip registers */ 266 #define HPC_PBUS_CH9_DEVREGS_3_SIZE 0x03ff 267 268 #define HPC_PBUS_CH8_DEVREGS_4 0x0005b800 /* PBus ch. 8 chip registers */ 269 #define HPC_PBUS_CH8_DEVREGS_4_SIZE 0x03ff 270 271 #define HPC_PBUS_CH9_DEVREGS_4 0x0005bc00 /* PBus ch. 9 chip registers */ 272 #define HPC_PBUS_CH9_DEVREGS_4_SIZE 0x03ff 273 274 #define HPC_PBUS_CFGDMA_REGS 0x0005c000 /* PBus DMA config registers */ 275 #define HPC_PBUS_CFGDMA_REGS_SIZE 0x0fff 276 277 #define HPC_PBUS_CH0_CFGDMA 0x0005c000 /* PBus Ch. 0 DMA config */ 278 #define HPC_PBUS_CH0_CFGDMA_SIZE 0x01ff 279 280 #define HPC_PBUS_CH1_CFGDMA 0x0005c200 /* PBus Ch. 1 DMA config */ 281 #define HPC_PBUS_CH1_CFGDMA_SIZE 0x01ff 282 283 #define HPC_PBUS_CH2_CFGDMA 0x0005c400 /* PBus Ch. 2 DMA config */ 284 #define HPC_PBUS_CH2_CFGDMA_SIZE 0x01ff 285 286 #define HPC_PBUS_CH3_CFGDMA 0x0005c600 /* PBus Ch. 3 DMA config */ 287 #define HPC_PBUS_CH3_CFGDMA_SIZE 0x01ff 288 289 #define HPC_PBUS_CH4_CFGDMA 0x0005c800 /* PBus Ch. 4 DMA config */ 290 #define HPC_PBUS_CH4_CFGDMA_SIZE 0x01ff 291 292 #define HPC_PBUS_CH5_CFGDMA 0x0005ca00 /* PBus Ch. 5 DMA config */ 293 #define HPC_PBUS_CH5_CFGDMA_SIZE 0x01ff 294 295 #define HPC_PBUS_CH6_CFGDMA 0x0005cc00 /* PBus Ch. 6 DMA config */ 296 #define HPC_PBUS_CH6_CFGDMA_SIZE 0x01ff 297 298 #define HPC_PBUS_CH7_CFGDMA 0x0005ce00 /* PBus Ch. 7 DMA config */ 299 #define HPC_PBUS_CH7_CFGDMA_SIZE 0x01ff 300 301 #define HPC_PBUS_CFGPIO_REGS 0x0005d000 /* PBus PIO config registers */ 302 #define HPC_PBUS_CFGPIO_REGS_SIZE 0x0fff 303 304 #define HPC_PBUS_CH0_CFGPIO 0x0005d000 /* PBus Ch. 0 PIO config */ 305 #define HPC_PBUS_CH1_CFGPIO 0x0005d100 /* PBus Ch. 1 PIO config */ 306 #define HPC_PBUS_CH2_CFGPIO 0x0005d200 /* PBus Ch. 2 PIO config */ 307 #define HPC_PBUS_CH3_CFGPIO 0x0005d300 /* PBus Ch. 3 PIO config */ 308 #define HPC_PBUS_CH4_CFGPIO 0x0005d400 /* PBus Ch. 4 PIO config */ 309 #define HPC_PBUS_CH5_CFGPIO 0x0005d500 /* PBus Ch. 5 PIO config */ 310 #define HPC_PBUS_CH6_CFGPIO 0x0005d600 /* PBus Ch. 6 PIO config */ 311 #define HPC_PBUS_CH7_CFGPIO 0x0005d700 /* PBus Ch. 7 PIO config */ 312 #define HPC_PBUS_CH8_CFGPIO 0x0005d800 /* PBus Ch. 8 PIO config */ 313 #define HPC_PBUS_CH9_CFGPIO 0x0005d900 /* PBus Ch. 9 PIO config */ 314 #define HPC_PBUS_CH8_CFGPIO_2 0x0005da00 /* PBus Ch. 8 PIO config */ 315 #define HPC_PBUS_CH9_CFGPIO_2 0x0005db00 /* PBus Ch. 9 PIO config */ 316 #define HPC_PBUS_CH8_CFGPIO_3 0x0005dc00 /* PBus Ch. 8 PIO config */ 317 #define HPC_PBUS_CH9_CFGPIO_3 0x0005dd00 /* PBus Ch. 9 PIO config */ 318 #define HPC_PBUS_CH8_CFGPIO_4 0x0005de00 /* PBus Ch. 8 PIO config */ 319 #define HPC_PBUS_CH9_CFGPIO_4 0x0005df00 /* PBus Ch. 9 PIO config */ 320 321 #define HPC_PBUS_PROM_WE 0x0005e000 /* PBus boot-prom write 322 * enable register 323 */ 324 325 #define HPC_PBUS_PROM_SWAP 0x0005e800 /* PBus boot-prom chip-select 326 * swap register 327 */ 328 329 #define HPC_PBUS_GEN_OUT 0x0005f000 /* PBus general-purpose output 330 * register 331 */ 332 333 #define HPC_PBUS_BBRAM 0x00060000 /* PBus battery-backed RAM 334 * external registers 335 */ 336 #endif /* _ARCH_SGIMIPS_HPC_HPCREG_H_ */ 337
Indexes created Mon Sep 22 10:09:38 GMT 2025