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hpcvar.h revision 1.6 
      1 /*	$NetBSD: hpcvar.h,v 1.6 2003/12/16 11:59:04 sekiya Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2001 Rafal K. Boni
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. The name of the author may not be used to endorse or promote products
     16  *    derived from this software without specific prior written permission.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     28  */
     29 
     30 #ifndef _ARCH_SGIMIPS_HPC_HPCVAR_H_
     31 #define	_ARCH_SGIMIPS_HPC_HPCVAR_H_
     32 
     33 #define HPCDEV_IP12		(1U << 0)	/* Indigo R3k, 4D/3x */
     34 #define HPCDEV_IP20		(1U << 1)	/* Indigo R4k */
     35 #define HPCDEV_IP22		(1U << 2)	/* Indigo2 */
     36 #define HPCDEV_IP24		(1U << 3)	/* Indy */
     37 
     38 /* HPC 1.5/3 differ a bit, thus we need an abstraction layer */
     39 
     40 struct hpc_values {
     41 	int		revision;
     42         u_int32_t       scsi0_regs;
     43         u_int32_t       scsi0_regs_size;
     44         u_int32_t       scsi0_cbp;
     45         u_int32_t       scsi0_ndbp;
     46         u_int32_t       scsi0_bc;
     47         u_int32_t       scsi0_ctl;
     48         u_int32_t       scsi0_gio;
     49         u_int32_t       scsi0_dev;
     50         u_int32_t       scsi0_dmacfg;
     51         u_int32_t       scsi0_piocfg;
     52         u_int32_t       scsi1_regs;
     53         u_int32_t       scsi1_regs_size;
     54         u_int32_t       scsi1_cbp;
     55         u_int32_t       scsi1_ndbp;
     56         u_int32_t       scsi1_bc;
     57         u_int32_t       scsi1_ctl;
     58         u_int32_t       scsi1_gio;
     59         u_int32_t       scsi1_dev;
     60         u_int32_t       scsi1_dmacfg;
     61         u_int32_t       scsi1_piocfg;
     62         u_int32_t       dmactl_dir;
     63         u_int32_t       dmactl_flush;
     64         u_int32_t       dmactl_active;
     65         u_int32_t       dmactl_reset;
     66         u_int32_t       enet_regs;
     67         u_int32_t       enet_regs_size;
     68         u_int32_t       enet_intdelay;
     69         u_int32_t       enet_intdelayval;
     70         u_int32_t       enetr_cbp;
     71         u_int32_t       enetr_ndbp;
     72         u_int32_t       enetr_bc;
     73         u_int32_t       enetr_ctl;
     74         u_int32_t       enetr_ctl_active;
     75         u_int32_t       enetr_reset;
     76         u_int32_t       enetr_dmacfg;
     77         u_int32_t       enetr_piocfg;
     78         u_int32_t       enetx_cbp;
     79         u_int32_t       enetx_ndbp;
     80         u_int32_t       enetx_bc;
     81         u_int32_t       enetx_ctl;
     82         u_int32_t       enetx_ctl_active;
     83         u_int32_t       enetx_dev;
     84         u_int32_t       enetr_fifo;
     85         u_int32_t       enetr_fifo_size;
     86         u_int32_t       enetx_fifo;
     87         u_int32_t       enetx_fifo_size;
     88         u_int32_t       scsi0_devregs_size;
     89         u_int32_t       scsi1_devregs_size;
     90         u_int32_t       enet_devregs;
     91         u_int32_t       enet_devregs_size;
     92         u_int32_t       pbus_fifo;
     93         u_int32_t       pbus_fifo_size;
     94         u_int32_t       pbus_bbram;
     95 	u_int32_t       scsi_dma_segs;
     96         u_int32_t       scsi_dma_segs_size;
     97         u_int32_t       clk_freq;
     98         u_int32_t       dma_datain_cmd;
     99         u_int32_t       dma_dataout_cmd;
    100         u_int32_t       scsi_dmactl_flush;
    101         u_int32_t       scsi_dmactl_active;
    102         u_int32_t       scsi_dmactl_reset;
    103 };
    104 
    105 struct hpc_attach_args {
    106 	const char		*ha_name;	/* name of device */
    107 	bus_addr_t		ha_devoff;	/* offset of device */
    108 	bus_addr_t		ha_dmaoff;	/* offset of DMA regs */
    109 	int			ha_irq;		/* interrupt line */
    110 
    111 	bus_space_tag_t		ha_st;		/* HPC space tag */
    112 	bus_space_handle_t	ha_sh;		/* HPC space handle XXX */
    113 	bus_dma_tag_t		ha_dmat;	/* HPC DMA tag */
    114 
    115 	struct hpc_values	*hpc_regs;	/* HPC register definitions */
    116 };
    117 
    118 #endif	/* _ARCH_SGIMIPS_HPC_HPCVAR_H_ */
    119