if_sq.c revision 1.46
1 /* $NetBSD: if_sq.c,v 1.46 2016/06/10 13:27:12 ozaki-r Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Rafal K. Boni 5 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * Portions of this code are derived from software contributed to The 9 * NetBSD Foundation by Jason R. Thorpe of the Numerical Aerospace 10 * Simulation Facility, NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: if_sq.c,v 1.46 2016/06/10 13:27:12 ozaki-r Exp $"); 37 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/callout.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/syslog.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <machine/endian.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 60 #include <net/bpf.h> 61 62 #include <sys/bus.h> 63 #include <machine/intr.h> 64 #include <machine/sysconf.h> 65 66 #include <dev/ic/seeq8003reg.h> 67 68 #include <sgimips/hpc/sqvar.h> 69 #include <sgimips/hpc/hpcvar.h> 70 #include <sgimips/hpc/hpcreg.h> 71 72 #include <dev/arcbios/arcbios.h> 73 #include <dev/arcbios/arcbiosvar.h> 74 75 #define static 76 77 /* 78 * Short TODO list: 79 * (1) Do counters for bad-RX packets. 80 * (2) Allow multi-segment transmits, instead of copying to a single, 81 * contiguous mbuf. 82 * (3) Verify sq_stop() turns off enough stuff; I was still getting 83 * seeq interrupts after sq_stop(). 84 * (4) Implement EDLC modes: especially packet auto-pad and simplex 85 * mode. 86 * (5) Should the driver filter out its own transmissions in non-EDLC 87 * mode? 88 * (6) Multicast support -- multicast filter, address management, ... 89 * (7) Deal with RB0 (recv buffer overflow) on reception. Will need 90 * to figure out if RB0 is read-only as stated in one spot in the 91 * HPC spec or read-write (ie, is the 'write a one to clear it') 92 * the correct thing? 93 */ 94 95 #if defined(SQ_DEBUG) 96 int sq_debug = 0; 97 #define SQ_DPRINTF(x) if (sq_debug) printf x 98 #else 99 #define SQ_DPRINTF(x) 100 #endif 101 102 static int sq_match(device_t, cfdata_t, void *); 103 static void sq_attach(device_t, device_t, void *); 104 static int sq_init(struct ifnet *); 105 static void sq_start(struct ifnet *); 106 static void sq_stop(struct ifnet *, int); 107 static void sq_watchdog(struct ifnet *); 108 static int sq_ioctl(struct ifnet *, u_long, void *); 109 110 static void sq_set_filter(struct sq_softc *); 111 static int sq_intr(void *); 112 static int sq_rxintr(struct sq_softc *); 113 static int sq_txintr(struct sq_softc *); 114 static void sq_txring_hpc1(struct sq_softc *); 115 static void sq_txring_hpc3(struct sq_softc *); 116 static void sq_reset(struct sq_softc *); 117 static int sq_add_rxbuf(struct sq_softc *, int); 118 static void sq_dump_buffer(paddr_t addr, psize_t len); 119 static void sq_trace_dump(struct sq_softc *); 120 121 CFATTACH_DECL_NEW(sq, sizeof(struct sq_softc), 122 sq_match, sq_attach, NULL, NULL); 123 124 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 125 126 #define sq_seeq_read(sc, off) \ 127 bus_space_read_1(sc->sc_regt, sc->sc_regh, (off << 2) + 3) 128 #define sq_seeq_write(sc, off, val) \ 129 bus_space_write_1(sc->sc_regt, sc->sc_regh, (off << 2) + 3, val) 130 131 #define sq_hpc_read(sc, off) \ 132 bus_space_read_4(sc->sc_hpct, sc->sc_hpch, off) 133 #define sq_hpc_write(sc, off, val) \ 134 bus_space_write_4(sc->sc_hpct, sc->sc_hpch, off, val) 135 136 /* MAC address offset for non-onboard implementations */ 137 #define SQ_HPC_EEPROM_ENADDR 250 138 139 #define SGI_OUI_0 0x08 140 #define SGI_OUI_1 0x00 141 #define SGI_OUI_2 0x69 142 143 static int 144 sq_match(device_t parent, cfdata_t cf, void *aux) 145 { 146 struct hpc_attach_args *ha = aux; 147 148 if (strcmp(ha->ha_name, cf->cf_name) == 0) { 149 vaddr_t reset, txstat; 150 151 reset = MIPS_PHYS_TO_KSEG1(ha->ha_sh + 152 ha->ha_dmaoff + ha->hpc_regs->enetr_reset); 153 txstat = MIPS_PHYS_TO_KSEG1(ha->ha_sh + 154 ha->ha_devoff + (SEEQ_TXSTAT << 2)); 155 156 if (platform.badaddr((void *)reset, sizeof(reset))) 157 return 0; 158 159 *(volatile uint32_t *)reset = 0x1; 160 delay(20); 161 *(volatile uint32_t *)reset = 0x0; 162 163 if (platform.badaddr((void *)txstat, sizeof(txstat))) 164 return 0; 165 166 if ((*(volatile uint32_t *)txstat & 0xff) == TXSTAT_OLDNEW) 167 return 1; 168 } 169 170 return 0; 171 } 172 173 static void 174 sq_attach(device_t parent, device_t self, void *aux) 175 { 176 int i, err; 177 const char* macaddr; 178 struct sq_softc *sc = device_private(self); 179 struct hpc_attach_args *haa = aux; 180 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 181 182 sc->sc_dev = self; 183 sc->sc_hpct = haa->ha_st; 184 sc->hpc_regs = haa->hpc_regs; /* HPC register definitions */ 185 186 if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh, 187 haa->ha_dmaoff, sc->hpc_regs->enet_regs_size, 188 &sc->sc_hpch)) != 0) { 189 printf(": unable to map HPC DMA registers, error = %d\n", err); 190 goto fail_0; 191 } 192 193 sc->sc_regt = haa->ha_st; 194 if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh, 195 haa->ha_devoff, sc->hpc_regs->enet_devregs_size, 196 &sc->sc_regh)) != 0) { 197 printf(": unable to map Seeq registers, error = %d\n", err); 198 goto fail_0; 199 } 200 201 sc->sc_dmat = haa->ha_dmat; 202 203 if ((err = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct sq_control), 204 PAGE_SIZE, PAGE_SIZE, &sc->sc_cdseg, 1, &sc->sc_ncdseg, 205 BUS_DMA_NOWAIT)) != 0) { 206 printf(": unable to allocate control data, error = %d\n", err); 207 goto fail_0; 208 } 209 210 if ((err = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_ncdseg, 211 sizeof(struct sq_control), (void **)&sc->sc_control, 212 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 213 printf(": unable to map control data, error = %d\n", err); 214 goto fail_1; 215 } 216 217 if ((err = bus_dmamap_create(sc->sc_dmat, 218 sizeof(struct sq_control), 1, sizeof(struct sq_control), PAGE_SIZE, 219 BUS_DMA_NOWAIT, &sc->sc_cdmap)) != 0) { 220 printf(": unable to create DMA map for control data, error " 221 "= %d\n", err); 222 goto fail_2; 223 } 224 225 if ((err = bus_dmamap_load(sc->sc_dmat, sc->sc_cdmap, 226 sc->sc_control, sizeof(struct sq_control), NULL, 227 BUS_DMA_NOWAIT)) != 0) { 228 printf(": unable to load DMA map for control data, error " 229 "= %d\n", err); 230 goto fail_3; 231 } 232 233 memset(sc->sc_control, 0, sizeof(struct sq_control)); 234 235 /* Create transmit buffer DMA maps */ 236 for (i = 0; i < SQ_NTXDESC; i++) { 237 if ((err = bus_dmamap_create(sc->sc_dmat, 238 MCLBYTES, 1, MCLBYTES, 0, 239 BUS_DMA_NOWAIT, &sc->sc_txmap[i])) != 0) { 240 printf(": unable to create tx DMA map %d, error = %d\n", 241 i, err); 242 goto fail_4; 243 } 244 } 245 246 /* Create receive buffer DMA maps */ 247 for (i = 0; i < SQ_NRXDESC; i++) { 248 if ((err = bus_dmamap_create(sc->sc_dmat, 249 MCLBYTES, 1, MCLBYTES, 0, 250 BUS_DMA_NOWAIT, &sc->sc_rxmap[i])) != 0) { 251 printf(": unable to create rx DMA map %d, error = %d\n", 252 i, err); 253 goto fail_5; 254 } 255 } 256 257 /* Pre-allocate the receive buffers. */ 258 for (i = 0; i < SQ_NRXDESC; i++) { 259 if ((err = sq_add_rxbuf(sc, i)) != 0) { 260 printf(": unable to allocate or map rx buffer %d\n," 261 " error = %d\n", i, err); 262 goto fail_6; 263 } 264 } 265 266 memcpy(sc->sc_enaddr, &haa->hpc_eeprom[SQ_HPC_EEPROM_ENADDR], 267 ETHER_ADDR_LEN); 268 269 /* 270 * If our mac address is bogus, obtain it from ARCBIOS. This will 271 * be true of the onboard HPC3 on IP22, since there is no eeprom, 272 * but rather the DS1386 RTC's battery-backed ram is used. 273 */ 274 if (sc->sc_enaddr[0] != SGI_OUI_0 || 275 sc->sc_enaddr[1] != SGI_OUI_1 || 276 sc->sc_enaddr[2] != SGI_OUI_2) { 277 macaddr = arcbios_GetEnvironmentVariable("eaddr"); 278 if (macaddr == NULL) { 279 printf(": unable to get MAC address!\n"); 280 goto fail_6; 281 } 282 ether_aton_r(sc->sc_enaddr, sizeof(sc->sc_enaddr), macaddr); 283 } 284 285 evcnt_attach_dynamic(&sc->sq_intrcnt, EVCNT_TYPE_INTR, NULL, 286 device_xname(self), "intr"); 287 288 if ((cpu_intr_establish(haa->ha_irq, IPL_NET, sq_intr, sc)) == NULL) { 289 printf(": unable to establish interrupt!\n"); 290 goto fail_6; 291 } 292 293 /* Reset the chip to a known state. */ 294 sq_reset(sc); 295 296 /* 297 * Determine if we're an 8003 or 80c03 by setting the first 298 * MAC address register to non-zero, and then reading it back. 299 * If it's zero, we have an 80c03, because we will have read 300 * the TxCollLSB register. 301 */ 302 sq_seeq_write(sc, SEEQ_TXCOLLS0, 0xa5); 303 if (sq_seeq_read(sc, SEEQ_TXCOLLS0) == 0) 304 sc->sc_type = SQ_TYPE_80C03; 305 else 306 sc->sc_type = SQ_TYPE_8003; 307 sq_seeq_write(sc, SEEQ_TXCOLLS0, 0x00); 308 309 printf(": SGI Seeq %s\n", 310 sc->sc_type == SQ_TYPE_80C03 ? "80c03" : "8003"); 311 312 printf("%s: Ethernet address %s\n", 313 device_xname(self), ether_sprintf(sc->sc_enaddr)); 314 315 strcpy(ifp->if_xname, device_xname(self)); 316 ifp->if_softc = sc; 317 ifp->if_mtu = ETHERMTU; 318 ifp->if_init = sq_init; 319 ifp->if_stop = sq_stop; 320 ifp->if_start = sq_start; 321 ifp->if_ioctl = sq_ioctl; 322 ifp->if_watchdog = sq_watchdog; 323 ifp->if_flags = IFF_BROADCAST | IFF_NOTRAILERS | IFF_MULTICAST; 324 IFQ_SET_READY(&ifp->if_snd); 325 326 if_attach(ifp); 327 ether_ifattach(ifp, sc->sc_enaddr); 328 329 memset(&sc->sq_trace, 0, sizeof(sc->sq_trace)); 330 /* Done! */ 331 return; 332 333 /* 334 * Free any resources we've allocated during the failed attach 335 * attempt. Do this in reverse order and fall through. 336 */ 337 fail_6: 338 for (i = 0; i < SQ_NRXDESC; i++) { 339 if (sc->sc_rxmbuf[i] != NULL) { 340 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmap[i]); 341 m_freem(sc->sc_rxmbuf[i]); 342 } 343 } 344 fail_5: 345 for (i = 0; i < SQ_NRXDESC; i++) { 346 if (sc->sc_rxmap[i] != NULL) 347 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmap[i]); 348 } 349 fail_4: 350 for (i = 0; i < SQ_NTXDESC; i++) { 351 if (sc->sc_txmap[i] != NULL) 352 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txmap[i]); 353 } 354 bus_dmamap_unload(sc->sc_dmat, sc->sc_cdmap); 355 fail_3: 356 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cdmap); 357 fail_2: 358 bus_dmamem_unmap(sc->sc_dmat, 359 (void *)sc->sc_control, sizeof(struct sq_control)); 360 fail_1: 361 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_ncdseg); 362 fail_0: 363 return; 364 } 365 366 /* Set up data to get the interface up and running. */ 367 int 368 sq_init(struct ifnet *ifp) 369 { 370 int i; 371 struct sq_softc *sc = ifp->if_softc; 372 373 /* Cancel any in-progress I/O */ 374 sq_stop(ifp, 0); 375 376 sc->sc_nextrx = 0; 377 378 sc->sc_nfreetx = SQ_NTXDESC; 379 sc->sc_nexttx = sc->sc_prevtx = 0; 380 381 SQ_TRACE(SQ_RESET, sc, 0, 0); 382 383 /* Set into 8003 mode, bank 0 to program ethernet address */ 384 sq_seeq_write(sc, SEEQ_TXCMD, TXCMD_BANK0); 385 386 /* Now write the address */ 387 for (i = 0; i < ETHER_ADDR_LEN; i++) 388 sq_seeq_write(sc, i, sc->sc_enaddr[i]); 389 390 sc->sc_rxcmd = 391 RXCMD_IE_CRC | 392 RXCMD_IE_DRIB | 393 RXCMD_IE_SHORT | 394 RXCMD_IE_END | 395 RXCMD_IE_GOOD; 396 397 /* 398 * Set the receive filter -- this will add some bits to the 399 * prototype RXCMD register. Do this before setting the 400 * transmit config register, since we might need to switch 401 * banks. 402 */ 403 sq_set_filter(sc); 404 405 /* Set up Seeq transmit command register */ 406 sq_seeq_write(sc, SEEQ_TXCMD, 407 TXCMD_IE_UFLOW | 408 TXCMD_IE_COLL | 409 TXCMD_IE_16COLL | 410 TXCMD_IE_GOOD); 411 412 /* Now write the receive command register. */ 413 sq_seeq_write(sc, SEEQ_RXCMD, sc->sc_rxcmd); 414 415 /* 416 * Set up HPC ethernet PIO and DMA configurations. 417 * 418 * The PROM appears to do most of this for the onboard HPC3, but 419 * not for the Challenge S's IOPLUS chip. We copy how the onboard 420 * chip is configured and assume that it's correct for both. 421 */ 422 if (sc->hpc_regs->revision == 3) { 423 uint32_t dmareg, pioreg; 424 425 pioreg = 426 HPC3_ENETR_PIOCFG_P1(1) | 427 HPC3_ENETR_PIOCFG_P2(6) | 428 HPC3_ENETR_PIOCFG_P3(1); 429 430 dmareg = 431 HPC3_ENETR_DMACFG_D1(6) | 432 HPC3_ENETR_DMACFG_D2(2) | 433 HPC3_ENETR_DMACFG_D3(0) | 434 HPC3_ENETR_DMACFG_FIX_RXDC | 435 HPC3_ENETR_DMACFG_FIX_INTR | 436 HPC3_ENETR_DMACFG_FIX_EOP | 437 HPC3_ENETR_DMACFG_TIMEOUT; 438 439 sq_hpc_write(sc, HPC3_ENETR_PIOCFG, pioreg); 440 sq_hpc_write(sc, HPC3_ENETR_DMACFG, dmareg); 441 } 442 443 /* Pass the start of the receive ring to the HPC */ 444 sq_hpc_write(sc, sc->hpc_regs->enetr_ndbp, SQ_CDRXADDR(sc, 0)); 445 446 /* And turn on the HPC ethernet receive channel */ 447 sq_hpc_write(sc, sc->hpc_regs->enetr_ctl, 448 sc->hpc_regs->enetr_ctl_active); 449 450 /* 451 * Turn off delayed receive interrupts on HPC1. 452 * (see Hollywood HPC Specification 2.1.4.3) 453 */ 454 if (sc->hpc_regs->revision != 3) 455 sq_hpc_write(sc, HPC1_ENET_INTDELAY, HPC1_ENET_INTDELAY_OFF); 456 457 ifp->if_flags |= IFF_RUNNING; 458 ifp->if_flags &= ~IFF_OACTIVE; 459 460 return 0; 461 } 462 463 static void 464 sq_set_filter(struct sq_softc *sc) 465 { 466 struct ethercom *ec = &sc->sc_ethercom; 467 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 468 struct ether_multi *enm; 469 struct ether_multistep step; 470 471 /* 472 * Check for promiscuous mode. Also implies 473 * all-multicast. 474 */ 475 if (ifp->if_flags & IFF_PROMISC) { 476 sc->sc_rxcmd |= RXCMD_REC_ALL; 477 ifp->if_flags |= IFF_ALLMULTI; 478 return; 479 } 480 481 /* 482 * The 8003 has no hash table. If we have any multicast 483 * addresses on the list, enable reception of all multicast 484 * frames. 485 * 486 * XXX The 80c03 has a hash table. We should use it. 487 */ 488 489 ETHER_FIRST_MULTI(step, ec, enm); 490 491 if (enm == NULL) { 492 sc->sc_rxcmd &= ~RXCMD_REC_MASK; 493 sc->sc_rxcmd |= RXCMD_REC_BROAD; 494 495 ifp->if_flags &= ~IFF_ALLMULTI; 496 return; 497 } 498 499 sc->sc_rxcmd |= RXCMD_REC_MULTI; 500 ifp->if_flags |= IFF_ALLMULTI; 501 } 502 503 int 504 sq_ioctl(struct ifnet *ifp, u_long cmd, void *data) 505 { 506 int s, error = 0; 507 508 SQ_TRACE(SQ_IOCTL, (struct sq_softc *)ifp->if_softc, 0, 0); 509 510 s = splnet(); 511 512 error = ether_ioctl(ifp, cmd, data); 513 if (error == ENETRESET) { 514 /* 515 * Multicast list has changed; set the hardware filter 516 * accordingly. 517 */ 518 if (ifp->if_flags & IFF_RUNNING) 519 error = sq_init(ifp); 520 else 521 error = 0; 522 } 523 524 splx(s); 525 return error; 526 } 527 528 void 529 sq_start(struct ifnet *ifp) 530 { 531 struct sq_softc *sc = ifp->if_softc; 532 uint32_t status; 533 struct mbuf *m0, *m; 534 bus_dmamap_t dmamap; 535 int err, totlen, nexttx, firsttx, lasttx = -1, ofree, seg; 536 537 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 538 return; 539 540 /* 541 * Remember the previous number of free descriptors and 542 * the first descriptor we'll use. 543 */ 544 ofree = sc->sc_nfreetx; 545 firsttx = sc->sc_nexttx; 546 547 /* 548 * Loop through the send queue, setting up transmit descriptors 549 * until we drain the queue, or use up all available transmit 550 * descriptors. 551 */ 552 while (sc->sc_nfreetx != 0) { 553 /* 554 * Grab a packet off the queue. 555 */ 556 IFQ_POLL(&ifp->if_snd, m0); 557 if (m0 == NULL) 558 break; 559 m = NULL; 560 561 dmamap = sc->sc_txmap[sc->sc_nexttx]; 562 563 /* 564 * Load the DMA map. If this fails, the packet either 565 * didn't fit in the alloted number of segments, or we were 566 * short on resources. In this case, we'll copy and try 567 * again. 568 * Also copy it if we need to pad, so that we are sure there 569 * is room for the pad buffer. 570 * XXX the right way of doing this is to use a static buffer 571 * for padding and adding it to the transmit descriptor (see 572 * sys/dev/pci/if_tl.c for example). We can't do this here yet 573 * because we can't send packets with more than one fragment. 574 */ 575 if (m0->m_pkthdr.len < ETHER_PAD_LEN || 576 bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 577 BUS_DMA_NOWAIT) != 0) { 578 MGETHDR(m, M_DONTWAIT, MT_DATA); 579 if (m == NULL) { 580 printf("%s: unable to allocate Tx mbuf\n", 581 device_xname(sc->sc_dev)); 582 break; 583 } 584 if (m0->m_pkthdr.len > MHLEN) { 585 MCLGET(m, M_DONTWAIT); 586 if ((m->m_flags & M_EXT) == 0) { 587 printf("%s: unable to allocate Tx " 588 "cluster\n", 589 device_xname(sc->sc_dev)); 590 m_freem(m); 591 break; 592 } 593 } 594 595 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 596 if (m0->m_pkthdr.len < ETHER_PAD_LEN) { 597 memset(mtod(m, char *) + m0->m_pkthdr.len, 0, 598 ETHER_PAD_LEN - m0->m_pkthdr.len); 599 m->m_pkthdr.len = m->m_len = ETHER_PAD_LEN; 600 } else 601 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 602 603 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 604 m, BUS_DMA_NOWAIT)) != 0) { 605 printf("%s: unable to load Tx buffer, " 606 "error = %d\n", 607 device_xname(sc->sc_dev), err); 608 break; 609 } 610 } 611 612 /* 613 * Ensure we have enough descriptors free to describe 614 * the packet. 615 */ 616 if (dmamap->dm_nsegs > sc->sc_nfreetx) { 617 /* 618 * Not enough free descriptors to transmit this 619 * packet. We haven't committed to anything yet, 620 * so just unload the DMA map, put the packet 621 * back on the queue, and punt. Notify the upper 622 * layer that there are no more slots left. 623 * 624 * XXX We could allocate an mbuf and copy, but 625 * XXX it is worth it? 626 */ 627 ifp->if_flags |= IFF_OACTIVE; 628 bus_dmamap_unload(sc->sc_dmat, dmamap); 629 if (m != NULL) 630 m_freem(m); 631 break; 632 } 633 634 IFQ_DEQUEUE(&ifp->if_snd, m0); 635 /* 636 * Pass the packet to any BPF listeners. 637 */ 638 bpf_mtap(ifp, m0); 639 if (m != NULL) { 640 m_freem(m0); 641 m0 = m; 642 } 643 644 /* 645 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 646 */ 647 648 SQ_TRACE(SQ_ENQUEUE, sc, sc->sc_nexttx, 0); 649 650 /* Sync the DMA map. */ 651 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 652 BUS_DMASYNC_PREWRITE); 653 654 /* 655 * Initialize the transmit descriptors. 656 */ 657 for (nexttx = sc->sc_nexttx, seg = 0, totlen = 0; 658 seg < dmamap->dm_nsegs; 659 seg++, nexttx = SQ_NEXTTX(nexttx)) { 660 if (sc->hpc_regs->revision == 3) { 661 sc->sc_txdesc[nexttx].hpc3_hdd_bufptr = 662 dmamap->dm_segs[seg].ds_addr; 663 sc->sc_txdesc[nexttx].hpc3_hdd_ctl = 664 dmamap->dm_segs[seg].ds_len; 665 } else { 666 sc->sc_txdesc[nexttx].hpc1_hdd_bufptr = 667 dmamap->dm_segs[seg].ds_addr; 668 sc->sc_txdesc[nexttx].hpc1_hdd_ctl = 669 dmamap->dm_segs[seg].ds_len; 670 } 671 sc->sc_txdesc[nexttx].hdd_descptr = 672 SQ_CDTXADDR(sc, SQ_NEXTTX(nexttx)); 673 lasttx = nexttx; 674 totlen += dmamap->dm_segs[seg].ds_len; 675 } 676 677 /* Last descriptor gets end-of-packet */ 678 KASSERT(lasttx != -1); 679 if (sc->hpc_regs->revision == 3) 680 sc->sc_txdesc[lasttx].hpc3_hdd_ctl |= 681 HPC3_HDD_CTL_EOPACKET; 682 else 683 sc->sc_txdesc[lasttx].hpc1_hdd_ctl |= 684 HPC1_HDD_CTL_EOPACKET; 685 686 SQ_DPRINTF(("%s: transmit %d-%d, len %d\n", 687 device_xname(sc->sc_dev), sc->sc_nexttx, lasttx, totlen)); 688 689 if (ifp->if_flags & IFF_DEBUG) { 690 printf(" transmit chain:\n"); 691 for (seg = sc->sc_nexttx;; seg = SQ_NEXTTX(seg)) { 692 printf(" descriptor %d:\n", seg); 693 printf(" hdd_bufptr: 0x%08x\n", 694 (sc->hpc_regs->revision == 3) ? 695 sc->sc_txdesc[seg].hpc3_hdd_bufptr : 696 sc->sc_txdesc[seg].hpc1_hdd_bufptr); 697 printf(" hdd_ctl: 0x%08x\n", 698 (sc->hpc_regs->revision == 3) ? 699 sc->sc_txdesc[seg].hpc3_hdd_ctl: 700 sc->sc_txdesc[seg].hpc1_hdd_ctl); 701 printf(" hdd_descptr: 0x%08x\n", 702 sc->sc_txdesc[seg].hdd_descptr); 703 704 if (seg == lasttx) 705 break; 706 } 707 } 708 709 /* Sync the descriptors we're using. */ 710 SQ_CDTXSYNC(sc, sc->sc_nexttx, dmamap->dm_nsegs, 711 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 712 713 /* Store a pointer to the packet so we can free it later */ 714 sc->sc_txmbuf[sc->sc_nexttx] = m0; 715 716 /* Advance the tx pointer. */ 717 sc->sc_nfreetx -= dmamap->dm_nsegs; 718 sc->sc_nexttx = nexttx; 719 } 720 721 /* All transmit descriptors used up, let upper layers know */ 722 if (sc->sc_nfreetx == 0) 723 ifp->if_flags |= IFF_OACTIVE; 724 725 if (sc->sc_nfreetx != ofree) { 726 SQ_DPRINTF(("%s: %d packets enqueued, first %d, INTR on %d\n", 727 device_xname(sc->sc_dev), lasttx - firsttx + 1, 728 firsttx, lasttx)); 729 730 /* 731 * Cause a transmit interrupt to happen on the 732 * last packet we enqueued, mark it as the last 733 * descriptor. 734 * 735 * HPC1_HDD_CTL_INTR will generate an interrupt on 736 * HPC1. HPC3 requires HPC3_HDD_CTL_EOPACKET in 737 * addition to HPC3_HDD_CTL_INTR to interrupt. 738 */ 739 KASSERT(lasttx != -1); 740 if (sc->hpc_regs->revision == 3) { 741 sc->sc_txdesc[lasttx].hpc3_hdd_ctl |= 742 HPC3_HDD_CTL_INTR | HPC3_HDD_CTL_EOCHAIN; 743 } else { 744 sc->sc_txdesc[lasttx].hpc1_hdd_ctl |= HPC1_HDD_CTL_INTR; 745 sc->sc_txdesc[lasttx].hpc1_hdd_bufptr |= 746 HPC1_HDD_CTL_EOCHAIN; 747 } 748 749 SQ_CDTXSYNC(sc, lasttx, 1, 750 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 751 752 /* 753 * There is a potential race condition here if the HPC 754 * DMA channel is active and we try and either update 755 * the 'next descriptor' pointer in the HPC PIO space 756 * or the 'next descriptor' pointer in a previous desc- 757 * riptor. 758 * 759 * To avoid this, if the channel is active, we rely on 760 * the transmit interrupt routine noticing that there 761 * are more packets to send and restarting the HPC DMA 762 * engine, rather than mucking with the DMA state here. 763 */ 764 status = sq_hpc_read(sc, sc->hpc_regs->enetx_ctl); 765 766 if ((status & sc->hpc_regs->enetx_ctl_active) != 0) { 767 SQ_TRACE(SQ_ADD_TO_DMA, sc, firsttx, status); 768 769 /* 770 * NB: hpc3_hdd_ctl == hpc1_hdd_bufptr, and 771 * HPC1_HDD_CTL_EOCHAIN == HPC3_HDD_CTL_EOCHAIN 772 */ 773 sc->sc_txdesc[SQ_PREVTX(firsttx)].hpc3_hdd_ctl &= 774 ~HPC3_HDD_CTL_EOCHAIN; 775 776 if (sc->hpc_regs->revision != 3) 777 sc->sc_txdesc[SQ_PREVTX(firsttx)].hpc1_hdd_ctl 778 &= ~HPC1_HDD_CTL_INTR; 779 780 SQ_CDTXSYNC(sc, SQ_PREVTX(firsttx), 1, 781 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 782 } else if (sc->hpc_regs->revision == 3) { 783 SQ_TRACE(SQ_START_DMA, sc, firsttx, status); 784 785 sq_hpc_write(sc, HPC3_ENETX_NDBP, SQ_CDTXADDR(sc, 786 firsttx)); 787 788 /* Kick DMA channel into life */ 789 sq_hpc_write(sc, HPC3_ENETX_CTL, HPC3_ENETX_CTL_ACTIVE); 790 } else { 791 /* 792 * In the HPC1 case where transmit DMA is 793 * inactive, we can either kick off if 794 * the ring was previously empty, or call 795 * our transmit interrupt handler to 796 * figure out if the ring stopped short 797 * and restart at the right place. 798 */ 799 if (ofree == SQ_NTXDESC) { 800 SQ_TRACE(SQ_START_DMA, sc, firsttx, status); 801 802 sq_hpc_write(sc, HPC1_ENETX_NDBP, 803 SQ_CDTXADDR(sc, firsttx)); 804 sq_hpc_write(sc, HPC1_ENETX_CFXBP, 805 SQ_CDTXADDR(sc, firsttx)); 806 sq_hpc_write(sc, HPC1_ENETX_CBP, 807 SQ_CDTXADDR(sc, firsttx)); 808 809 /* Kick DMA channel into life */ 810 sq_hpc_write(sc, HPC1_ENETX_CTL, 811 HPC1_ENETX_CTL_ACTIVE); 812 } else 813 sq_txring_hpc1(sc); 814 } 815 816 /* Set a watchdog timer in case the chip flakes out. */ 817 ifp->if_timer = 5; 818 } 819 } 820 821 void 822 sq_stop(struct ifnet *ifp, int disable) 823 { 824 int i; 825 struct sq_softc *sc = ifp->if_softc; 826 827 for (i = 0; i < SQ_NTXDESC; i++) { 828 if (sc->sc_txmbuf[i] != NULL) { 829 bus_dmamap_unload(sc->sc_dmat, sc->sc_txmap[i]); 830 m_freem(sc->sc_txmbuf[i]); 831 sc->sc_txmbuf[i] = NULL; 832 } 833 } 834 835 /* Clear Seeq transmit/receive command registers */ 836 sq_seeq_write(sc, SEEQ_TXCMD, 0); 837 sq_seeq_write(sc, SEEQ_RXCMD, 0); 838 839 sq_reset(sc); 840 841 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 842 ifp->if_timer = 0; 843 } 844 845 /* Device timeout/watchdog routine. */ 846 void 847 sq_watchdog(struct ifnet *ifp) 848 { 849 uint32_t status; 850 struct sq_softc *sc = ifp->if_softc; 851 852 status = sq_hpc_read(sc, sc->hpc_regs->enetx_ctl); 853 log(LOG_ERR, "%s: device timeout (prev %d, next %d, free %d, " 854 "status %08x)\n", device_xname(sc->sc_dev), sc->sc_prevtx, 855 sc->sc_nexttx, sc->sc_nfreetx, status); 856 857 sq_trace_dump(sc); 858 859 memset(&sc->sq_trace, 0, sizeof(sc->sq_trace)); 860 sc->sq_trace_idx = 0; 861 862 ++ifp->if_oerrors; 863 864 sq_init(ifp); 865 } 866 867 static void 868 sq_trace_dump(struct sq_softc *sc) 869 { 870 int i; 871 const char *act; 872 873 for (i = 0; i < sc->sq_trace_idx; i++) { 874 switch (sc->sq_trace[i].action) { 875 case SQ_RESET: act = "SQ_RESET"; break; 876 case SQ_ADD_TO_DMA: act = "SQ_ADD_TO_DMA"; break; 877 case SQ_START_DMA: act = "SQ_START_DMA"; break; 878 case SQ_DONE_DMA: act = "SQ_DONE_DMA"; break; 879 case SQ_RESTART_DMA: act = "SQ_RESTART_DMA"; break; 880 case SQ_TXINTR_ENTER: act = "SQ_TXINTR_ENTER"; break; 881 case SQ_TXINTR_EXIT: act = "SQ_TXINTR_EXIT"; break; 882 case SQ_TXINTR_BUSY: act = "SQ_TXINTR_BUSY"; break; 883 case SQ_IOCTL: act = "SQ_IOCTL"; break; 884 case SQ_ENQUEUE: act = "SQ_ENQUEUE"; break; 885 default: act = "UNKNOWN"; 886 } 887 888 printf("%s: [%03d] action %-16s buf %03d free %03d " 889 "status %08x line %d\n", device_xname(sc->sc_dev), i, act, 890 sc->sq_trace[i].bufno, sc->sq_trace[i].freebuf, 891 sc->sq_trace[i].status, sc->sq_trace[i].line); 892 } 893 } 894 895 static int 896 sq_intr(void *arg) 897 { 898 struct sq_softc *sc = arg; 899 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 900 int handled = 0; 901 uint32_t stat; 902 903 stat = sq_hpc_read(sc, sc->hpc_regs->enetr_reset); 904 905 if ((stat & 2) == 0) 906 SQ_DPRINTF(("%s: Unexpected interrupt!\n", 907 device_xname(sc->sc_dev))); 908 else 909 sq_hpc_write(sc, sc->hpc_regs->enetr_reset, (stat | 2)); 910 911 /* 912 * If the interface isn't running, the interrupt couldn't 913 * possibly have come from us. 914 */ 915 if ((ifp->if_flags & IFF_RUNNING) == 0) 916 return 0; 917 918 sc->sq_intrcnt.ev_count++; 919 920 /* Always check for received packets */ 921 if (sq_rxintr(sc) != 0) 922 handled++; 923 924 /* Only handle transmit interrupts if we actually sent something */ 925 if (sc->sc_nfreetx < SQ_NTXDESC) { 926 sq_txintr(sc); 927 handled++; 928 } 929 930 if (handled) 931 rnd_add_uint32(&sc->rnd_source, stat); 932 return handled; 933 } 934 935 static int 936 sq_rxintr(struct sq_softc *sc) 937 { 938 int count = 0; 939 struct mbuf* m; 940 int i, framelen; 941 uint8_t pktstat; 942 uint32_t status; 943 uint32_t ctl_reg; 944 int new_end, orig_end; 945 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 946 947 for (i = sc->sc_nextrx;; i = SQ_NEXTRX(i)) { 948 SQ_CDRXSYNC(sc, i, 949 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 950 951 /* 952 * If this is a CPU-owned buffer, we're at the end of the list. 953 */ 954 if (sc->hpc_regs->revision == 3) 955 ctl_reg = 956 sc->sc_rxdesc[i].hpc3_hdd_ctl & HPC3_HDD_CTL_OWN; 957 else 958 ctl_reg = 959 sc->sc_rxdesc[i].hpc1_hdd_ctl & HPC1_HDD_CTL_OWN; 960 961 if (ctl_reg) { 962 #if defined(SQ_DEBUG) 963 uint32_t reg; 964 965 reg = sq_hpc_read(sc, sc->hpc_regs->enetr_ctl); 966 SQ_DPRINTF(("%s: rxintr: done at %d (ctl %08x)\n", 967 device_xname(sc->sc_dev), i, reg)); 968 #endif 969 break; 970 } 971 972 count++; 973 974 m = sc->sc_rxmbuf[i]; 975 framelen = m->m_ext.ext_size - 3; 976 if (sc->hpc_regs->revision == 3) 977 framelen -= 978 HPC3_HDD_CTL_BYTECNT(sc->sc_rxdesc[i].hpc3_hdd_ctl); 979 else 980 framelen -= 981 HPC1_HDD_CTL_BYTECNT(sc->sc_rxdesc[i].hpc1_hdd_ctl); 982 983 /* Now sync the actual packet data */ 984 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[i], 0, 985 sc->sc_rxmap[i]->dm_mapsize, BUS_DMASYNC_POSTREAD); 986 987 pktstat = *((uint8_t *)m->m_data + framelen + 2); 988 989 if ((pktstat & RXSTAT_GOOD) == 0) { 990 ifp->if_ierrors++; 991 992 if (pktstat & RXSTAT_OFLOW) 993 printf("%s: receive FIFO overflow\n", 994 device_xname(sc->sc_dev)); 995 996 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[i], 0, 997 sc->sc_rxmap[i]->dm_mapsize, BUS_DMASYNC_PREREAD); 998 SQ_INIT_RXDESC(sc, i); 999 SQ_DPRINTF(("%s: sq_rxintr: buf %d no RXSTAT_GOOD\n", 1000 device_xname(sc->sc_dev), i)); 1001 continue; 1002 } 1003 1004 if (sq_add_rxbuf(sc, i) != 0) { 1005 ifp->if_ierrors++; 1006 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[i], 0, 1007 sc->sc_rxmap[i]->dm_mapsize, BUS_DMASYNC_PREREAD); 1008 SQ_INIT_RXDESC(sc, i); 1009 SQ_DPRINTF(("%s: sq_rxintr: buf %d sq_add_rxbuf() " 1010 "failed\n", device_xname(sc->sc_dev), i)); 1011 continue; 1012 } 1013 1014 1015 m->m_data += 2; 1016 m_set_rcvif(m, ifp); 1017 m->m_pkthdr.len = m->m_len = framelen; 1018 1019 ifp->if_ipackets++; 1020 1021 SQ_DPRINTF(("%s: sq_rxintr: buf %d len %d\n", 1022 device_xname(sc->sc_dev), i, framelen)); 1023 1024 bpf_mtap(ifp, m); 1025 if_percpuq_enqueue(ifp->if_percpuq, m); 1026 } 1027 1028 1029 /* If anything happened, move ring start/end pointers to new spot */ 1030 if (i != sc->sc_nextrx) { 1031 /* 1032 * NB: hpc3_hdd_ctl == hpc1_hdd_bufptr, and 1033 * HPC1_HDD_CTL_EOCHAIN == HPC3_HDD_CTL_EOCHAIN 1034 */ 1035 1036 new_end = SQ_PREVRX(i); 1037 sc->sc_rxdesc[new_end].hpc3_hdd_ctl |= HPC3_HDD_CTL_EOCHAIN; 1038 SQ_CDRXSYNC(sc, new_end, 1039 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1040 1041 orig_end = SQ_PREVRX(sc->sc_nextrx); 1042 sc->sc_rxdesc[orig_end].hpc3_hdd_ctl &= ~HPC3_HDD_CTL_EOCHAIN; 1043 SQ_CDRXSYNC(sc, orig_end, 1044 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1045 1046 sc->sc_nextrx = i; 1047 } 1048 1049 status = sq_hpc_read(sc, sc->hpc_regs->enetr_ctl); 1050 1051 /* If receive channel is stopped, restart it... */ 1052 if ((status & sc->hpc_regs->enetr_ctl_active) == 0) { 1053 /* Pass the start of the receive ring to the HPC */ 1054 sq_hpc_write(sc, sc->hpc_regs->enetr_ndbp, 1055 SQ_CDRXADDR(sc, sc->sc_nextrx)); 1056 1057 /* And turn on the HPC ethernet receive channel */ 1058 sq_hpc_write(sc, sc->hpc_regs->enetr_ctl, 1059 sc->hpc_regs->enetr_ctl_active); 1060 } 1061 1062 return count; 1063 } 1064 1065 static int 1066 sq_txintr(struct sq_softc *sc) 1067 { 1068 int shift = 0; 1069 uint32_t status, tmp; 1070 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1071 1072 if (sc->hpc_regs->revision != 3) 1073 shift = 16; 1074 1075 status = sq_hpc_read(sc, sc->hpc_regs->enetx_ctl) >> shift; 1076 1077 SQ_TRACE(SQ_TXINTR_ENTER, sc, sc->sc_prevtx, status); 1078 1079 tmp = (sc->hpc_regs->enetx_ctl_active >> shift) | TXSTAT_GOOD; 1080 if ((status & tmp) == 0) { 1081 if (status & TXSTAT_COLL) 1082 ifp->if_collisions++; 1083 1084 if (status & TXSTAT_UFLOW) { 1085 printf("%s: transmit underflow\n", 1086 device_xname(sc->sc_dev)); 1087 ifp->if_oerrors++; 1088 } 1089 1090 if (status & TXSTAT_16COLL) { 1091 printf("%s: max collisions reached\n", 1092 device_xname(sc->sc_dev)); 1093 ifp->if_oerrors++; 1094 ifp->if_collisions += 16; 1095 } 1096 } 1097 1098 /* prevtx now points to next xmit packet not yet finished */ 1099 if (sc->hpc_regs->revision == 3) 1100 sq_txring_hpc3(sc); 1101 else 1102 sq_txring_hpc1(sc); 1103 1104 /* If we have buffers free, let upper layers know */ 1105 if (sc->sc_nfreetx > 0) 1106 ifp->if_flags &= ~IFF_OACTIVE; 1107 1108 /* If all packets have left the coop, cancel watchdog */ 1109 if (sc->sc_nfreetx == SQ_NTXDESC) 1110 ifp->if_timer = 0; 1111 1112 SQ_TRACE(SQ_TXINTR_EXIT, sc, sc->sc_prevtx, status); 1113 sq_start(ifp); 1114 1115 return 1; 1116 } 1117 1118 /* 1119 * Reclaim used transmit descriptors and restart the transmit DMA 1120 * engine if necessary. 1121 */ 1122 static void 1123 sq_txring_hpc1(struct sq_softc *sc) 1124 { 1125 /* 1126 * HPC1 doesn't tag transmitted descriptors, however, 1127 * the NDBP register points to the next descriptor that 1128 * has not yet been processed. If DMA is not in progress, 1129 * we can safely reclaim all descriptors up to NDBP, and, 1130 * if necessary, restart DMA at NDBP. Otherwise, if DMA 1131 * is active, we can only safely reclaim up to CBP. 1132 * 1133 * For now, we'll only reclaim on inactive DMA and assume 1134 * that a sufficiently large ring keeps us out of trouble. 1135 */ 1136 uint32_t reclaimto, status; 1137 int reclaimall, i = sc->sc_prevtx; 1138 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1139 1140 status = sq_hpc_read(sc, HPC1_ENETX_CTL); 1141 if (status & HPC1_ENETX_CTL_ACTIVE) { 1142 SQ_TRACE(SQ_TXINTR_BUSY, sc, i, status); 1143 return; 1144 } else 1145 reclaimto = sq_hpc_read(sc, HPC1_ENETX_NDBP); 1146 1147 if (sc->sc_nfreetx == 0 && SQ_CDTXADDR(sc, i) == reclaimto) 1148 reclaimall = 1; 1149 else 1150 reclaimall = 0; 1151 1152 while (sc->sc_nfreetx < SQ_NTXDESC) { 1153 if (SQ_CDTXADDR(sc, i) == reclaimto && !reclaimall) 1154 break; 1155 1156 SQ_CDTXSYNC(sc, i, sc->sc_txmap[i]->dm_nsegs, 1157 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1158 1159 /* Sync the packet data, unload DMA map, free mbuf */ 1160 bus_dmamap_sync(sc->sc_dmat, sc->sc_txmap[i], 1161 0, sc->sc_txmap[i]->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1162 bus_dmamap_unload(sc->sc_dmat, sc->sc_txmap[i]); 1163 m_freem(sc->sc_txmbuf[i]); 1164 sc->sc_txmbuf[i] = NULL; 1165 1166 ifp->if_opackets++; 1167 sc->sc_nfreetx++; 1168 1169 SQ_TRACE(SQ_DONE_DMA, sc, i, status); 1170 1171 i = SQ_NEXTTX(i); 1172 } 1173 1174 if (sc->sc_nfreetx < SQ_NTXDESC) { 1175 SQ_TRACE(SQ_RESTART_DMA, sc, i, status); 1176 1177 KASSERT(reclaimto == SQ_CDTXADDR(sc, i)); 1178 1179 sq_hpc_write(sc, HPC1_ENETX_CFXBP, reclaimto); 1180 sq_hpc_write(sc, HPC1_ENETX_CBP, reclaimto); 1181 1182 /* Kick DMA channel into life */ 1183 sq_hpc_write(sc, HPC1_ENETX_CTL, HPC1_ENETX_CTL_ACTIVE); 1184 1185 /* 1186 * Set a watchdog timer in case the chip 1187 * flakes out. 1188 */ 1189 ifp->if_timer = 5; 1190 } 1191 1192 sc->sc_prevtx = i; 1193 } 1194 1195 /* 1196 * Reclaim used transmit descriptors and restart the transmit DMA 1197 * engine if necessary. 1198 */ 1199 static void 1200 sq_txring_hpc3(struct sq_softc *sc) 1201 { 1202 /* 1203 * HPC3 tags descriptors with a bit once they've been 1204 * transmitted. We need only free each XMITDONE'd 1205 * descriptor, and restart the DMA engine if any 1206 * descriptors are left over. 1207 */ 1208 int i; 1209 uint32_t status = 0; 1210 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1211 1212 i = sc->sc_prevtx; 1213 while (sc->sc_nfreetx < SQ_NTXDESC) { 1214 /* 1215 * Check status first so we don't end up with a case of 1216 * the buffer not being finished while the DMA channel 1217 * has gone idle. 1218 */ 1219 status = sq_hpc_read(sc, HPC3_ENETX_CTL); 1220 1221 SQ_CDTXSYNC(sc, i, sc->sc_txmap[i]->dm_nsegs, 1222 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1223 1224 /* Check for used descriptor and restart DMA chain if needed */ 1225 if ((sc->sc_txdesc[i].hpc3_hdd_ctl & 1226 HPC3_HDD_CTL_XMITDONE) == 0) { 1227 if ((status & HPC3_ENETX_CTL_ACTIVE) == 0) { 1228 SQ_TRACE(SQ_RESTART_DMA, sc, i, status); 1229 1230 sq_hpc_write(sc, HPC3_ENETX_NDBP, 1231 SQ_CDTXADDR(sc, i)); 1232 1233 /* Kick DMA channel into life */ 1234 sq_hpc_write(sc, HPC3_ENETX_CTL, 1235 HPC3_ENETX_CTL_ACTIVE); 1236 1237 /* 1238 * Set a watchdog timer in case the chip 1239 * flakes out. 1240 */ 1241 ifp->if_timer = 5; 1242 } else 1243 SQ_TRACE(SQ_TXINTR_BUSY, sc, i, status); 1244 break; 1245 } 1246 1247 /* Sync the packet data, unload DMA map, free mbuf */ 1248 bus_dmamap_sync(sc->sc_dmat, sc->sc_txmap[i], 1249 0, sc->sc_txmap[i]->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1250 bus_dmamap_unload(sc->sc_dmat, sc->sc_txmap[i]); 1251 m_freem(sc->sc_txmbuf[i]); 1252 sc->sc_txmbuf[i] = NULL; 1253 1254 ifp->if_opackets++; 1255 sc->sc_nfreetx++; 1256 1257 SQ_TRACE(SQ_DONE_DMA, sc, i, status); 1258 i = SQ_NEXTTX(i); 1259 } 1260 1261 sc->sc_prevtx = i; 1262 } 1263 1264 void 1265 sq_reset(struct sq_softc *sc) 1266 { 1267 1268 /* Stop HPC dma channels */ 1269 sq_hpc_write(sc, sc->hpc_regs->enetr_ctl, 0); 1270 sq_hpc_write(sc, sc->hpc_regs->enetx_ctl, 0); 1271 1272 sq_hpc_write(sc, sc->hpc_regs->enetr_reset, 3); 1273 delay(20); 1274 sq_hpc_write(sc, sc->hpc_regs->enetr_reset, 0); 1275 } 1276 1277 /* sq_add_rxbuf: Add a receive buffer to the indicated descriptor. */ 1278 int 1279 sq_add_rxbuf(struct sq_softc *sc, int idx) 1280 { 1281 int err; 1282 struct mbuf *m; 1283 1284 MGETHDR(m, M_DONTWAIT, MT_DATA); 1285 if (m == NULL) 1286 return ENOBUFS; 1287 1288 MCLGET(m, M_DONTWAIT); 1289 if ((m->m_flags & M_EXT) == 0) { 1290 m_freem(m); 1291 return ENOBUFS; 1292 } 1293 1294 if (sc->sc_rxmbuf[idx] != NULL) 1295 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmap[idx]); 1296 1297 sc->sc_rxmbuf[idx] = m; 1298 1299 if ((err = bus_dmamap_load(sc->sc_dmat, sc->sc_rxmap[idx], 1300 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1301 printf("%s: can't load rx DMA map %d, error = %d\n", 1302 device_xname(sc->sc_dev), idx, err); 1303 panic("sq_add_rxbuf"); /* XXX */ 1304 } 1305 1306 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[idx], 1307 0, sc->sc_rxmap[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1308 1309 SQ_INIT_RXDESC(sc, idx); 1310 1311 return 0; 1312 } 1313 1314 void 1315 sq_dump_buffer(paddr_t addr, psize_t len) 1316 { 1317 u_int i; 1318 uint8_t *physaddr = (uint8_t *)MIPS_PHYS_TO_KSEG1(addr); 1319 1320 if (len == 0) 1321 return; 1322 1323 printf("%p: ", physaddr); 1324 1325 for (i = 0; i < len; i++) { 1326 printf("%02x ", *(physaddr + i) & 0xff); 1327 if ((i % 16) == 15 && i != len - 1) 1328 printf("\n%p: ", physaddr + i); 1329 } 1330 1331 printf("\n"); 1332 } 1333
Indexes created Thu Sep 25 16:09:42 GMT 2025