if_sq.c revision 1.55
1 /* $NetBSD: if_sq.c,v 1.55 2022/09/18 13:23:53 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Rafal K. Boni 5 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * Portions of this code are derived from software contributed to The 9 * NetBSD Foundation by Jason R. Thorpe of the Numerical Aerospace 10 * Simulation Facility, NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: if_sq.c,v 1.55 2022/09/18 13:23:53 thorpej Exp $"); 37 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/callout.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/syslog.h> 50 51 #include <uvm/uvm_extern.h> 52 53 #include <machine/endian.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 60 #include <net/bpf.h> 61 62 #include <sys/bus.h> 63 #include <machine/intr.h> 64 #include <machine/sysconf.h> 65 66 #include <dev/ic/seeq8003reg.h> 67 68 #include <sgimips/hpc/sqvar.h> 69 #include <sgimips/hpc/hpcvar.h> 70 #include <sgimips/hpc/hpcreg.h> 71 72 #include <dev/arcbios/arcbios.h> 73 #include <dev/arcbios/arcbiosvar.h> 74 75 #define static 76 77 /* 78 * Short TODO list: 79 * (1) Do counters for bad-RX packets. 80 * (2) Allow multi-segment transmits, instead of copying to a single, 81 * contiguous mbuf. 82 * (3) Verify sq_stop() turns off enough stuff; I was still getting 83 * seeq interrupts after sq_stop(). 84 * (4) Implement EDLC modes: especially packet auto-pad and simplex 85 * mode. 86 * (5) Should the driver filter out its own transmissions in non-EDLC 87 * mode? 88 * (6) Multicast support -- multicast filter, address management, ... 89 * (7) Deal with RB0 (recv buffer overflow) on reception. Will need 90 * to figure out if RB0 is read-only as stated in one spot in the 91 * HPC spec or read-write (ie, is the 'write a one to clear it') 92 * the correct thing? 93 */ 94 95 #if defined(SQ_DEBUG) 96 int sq_debug = 0; 97 #define SQ_DPRINTF(x) if (sq_debug) printf x 98 #else 99 #define SQ_DPRINTF(x) 100 #endif 101 102 static int sq_match(device_t, cfdata_t, void *); 103 static void sq_attach(device_t, device_t, void *); 104 static int sq_init(struct ifnet *); 105 static void sq_start(struct ifnet *); 106 static void sq_stop(struct ifnet *, int); 107 static void sq_watchdog(struct ifnet *); 108 static int sq_ioctl(struct ifnet *, u_long, void *); 109 110 static void sq_set_filter(struct sq_softc *); 111 static int sq_intr(void *); 112 static int sq_rxintr(struct sq_softc *); 113 static int sq_txintr(struct sq_softc *); 114 static void sq_txring_hpc1(struct sq_softc *); 115 static void sq_txring_hpc3(struct sq_softc *); 116 static void sq_reset(struct sq_softc *); 117 static int sq_add_rxbuf(struct sq_softc *, int); 118 static void sq_dump_buffer(paddr_t, psize_t); 119 static void sq_trace_dump(struct sq_softc *); 120 121 CFATTACH_DECL_NEW(sq, sizeof(struct sq_softc), 122 sq_match, sq_attach, NULL, NULL); 123 124 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 125 126 #define sq_seeq_read(sc, off) \ 127 bus_space_read_1(sc->sc_regt, sc->sc_regh, (off << 2) + 3) 128 #define sq_seeq_write(sc, off, val) \ 129 bus_space_write_1(sc->sc_regt, sc->sc_regh, (off << 2) + 3, val) 130 131 #define sq_hpc_read(sc, off) \ 132 bus_space_read_4(sc->sc_hpct, sc->sc_hpch, off) 133 #define sq_hpc_write(sc, off, val) \ 134 bus_space_write_4(sc->sc_hpct, sc->sc_hpch, off, val) 135 136 /* MAC address offset for non-onboard implementations */ 137 #define SQ_HPC_EEPROM_ENADDR 250 138 139 #define SGI_OUI_0 0x08 140 #define SGI_OUI_1 0x00 141 #define SGI_OUI_2 0x69 142 143 static int 144 sq_match(device_t parent, cfdata_t cf, void *aux) 145 { 146 struct hpc_attach_args *ha = aux; 147 148 if (strcmp(ha->ha_name, cf->cf_name) == 0) { 149 vaddr_t reset, txstat; 150 151 reset = MIPS_PHYS_TO_KSEG1(ha->ha_sh + 152 ha->ha_dmaoff + ha->hpc_regs->enetr_reset); 153 txstat = MIPS_PHYS_TO_KSEG1(ha->ha_sh + 154 ha->ha_devoff + (SEEQ_TXSTAT << 2)); 155 156 if (platform.badaddr((void *)reset, sizeof(reset))) 157 return 0; 158 159 *(volatile uint32_t *)reset = 0x1; 160 delay(20); 161 *(volatile uint32_t *)reset = 0x0; 162 163 if (platform.badaddr((void *)txstat, sizeof(txstat))) 164 return 0; 165 166 if ((*(volatile uint32_t *)txstat & 0xff) == TXSTAT_OLDNEW) 167 return 1; 168 } 169 170 return 0; 171 } 172 173 static void 174 sq_attach(device_t parent, device_t self, void *aux) 175 { 176 int i, err; 177 const char* macaddr; 178 struct sq_softc *sc = device_private(self); 179 struct hpc_attach_args *haa = aux; 180 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 181 182 sc->sc_dev = self; 183 sc->sc_hpct = haa->ha_st; 184 sc->hpc_regs = haa->hpc_regs; /* HPC register definitions */ 185 186 if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh, 187 haa->ha_dmaoff, sc->hpc_regs->enet_regs_size, 188 &sc->sc_hpch)) != 0) { 189 printf(": unable to map HPC DMA registers, error = %d\n", err); 190 goto fail_0; 191 } 192 193 sc->sc_regt = haa->ha_st; 194 if ((err = bus_space_subregion(haa->ha_st, haa->ha_sh, 195 haa->ha_devoff, sc->hpc_regs->enet_devregs_size, 196 &sc->sc_regh)) != 0) { 197 printf(": unable to map Seeq registers, error = %d\n", err); 198 goto fail_0; 199 } 200 201 sc->sc_dmat = haa->ha_dmat; 202 203 if ((err = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct sq_control), 204 PAGE_SIZE, PAGE_SIZE, &sc->sc_cdseg, 1, &sc->sc_ncdseg, 205 BUS_DMA_NOWAIT)) != 0) { 206 printf(": unable to allocate control data, error = %d\n", err); 207 goto fail_0; 208 } 209 210 if ((err = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_ncdseg, 211 sizeof(struct sq_control), (void **)&sc->sc_control, 212 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 213 printf(": unable to map control data, error = %d\n", err); 214 goto fail_1; 215 } 216 217 if ((err = bus_dmamap_create(sc->sc_dmat, 218 sizeof(struct sq_control), 1, sizeof(struct sq_control), PAGE_SIZE, 219 BUS_DMA_NOWAIT, &sc->sc_cdmap)) != 0) { 220 printf(": unable to create DMA map for control data, error " 221 "= %d\n", err); 222 goto fail_2; 223 } 224 225 if ((err = bus_dmamap_load(sc->sc_dmat, sc->sc_cdmap, 226 sc->sc_control, sizeof(struct sq_control), NULL, 227 BUS_DMA_NOWAIT)) != 0) { 228 printf(": unable to load DMA map for control data, error " 229 "= %d\n", err); 230 goto fail_3; 231 } 232 233 memset(sc->sc_control, 0, sizeof(struct sq_control)); 234 235 /* Create transmit buffer DMA maps */ 236 for (i = 0; i < SQ_NTXDESC; i++) { 237 if ((err = bus_dmamap_create(sc->sc_dmat, 238 MCLBYTES, 1, MCLBYTES, 0, 239 BUS_DMA_NOWAIT, &sc->sc_txmap[i])) != 0) { 240 printf(": unable to create tx DMA map %d, error = %d\n", 241 i, err); 242 goto fail_4; 243 } 244 } 245 246 /* Create receive buffer DMA maps */ 247 for (i = 0; i < SQ_NRXDESC; i++) { 248 if ((err = bus_dmamap_create(sc->sc_dmat, 249 MCLBYTES, 1, MCLBYTES, 0, 250 BUS_DMA_NOWAIT, &sc->sc_rxmap[i])) != 0) { 251 printf(": unable to create rx DMA map %d, error = %d\n", 252 i, err); 253 goto fail_5; 254 } 255 } 256 257 /* Pre-allocate the receive buffers. */ 258 for (i = 0; i < SQ_NRXDESC; i++) { 259 if ((err = sq_add_rxbuf(sc, i)) != 0) { 260 printf(": unable to allocate or map rx buffer %d\n," 261 " error = %d\n", i, err); 262 goto fail_6; 263 } 264 } 265 266 memcpy(sc->sc_enaddr, &haa->hpc_eeprom[SQ_HPC_EEPROM_ENADDR], 267 ETHER_ADDR_LEN); 268 269 /* 270 * If our mac address is bogus, obtain it from ARCBIOS. This will 271 * be true of the onboard HPC3 on IP22, since there is no eeprom, 272 * but rather the DS1386 RTC's battery-backed ram is used. 273 */ 274 if (sc->sc_enaddr[0] != SGI_OUI_0 || 275 sc->sc_enaddr[1] != SGI_OUI_1 || 276 sc->sc_enaddr[2] != SGI_OUI_2) { 277 macaddr = arcbios_GetEnvironmentVariable("eaddr"); 278 if (macaddr == NULL) { 279 printf(": unable to get MAC address!\n"); 280 goto fail_6; 281 } 282 ether_aton_r(sc->sc_enaddr, sizeof(sc->sc_enaddr), macaddr); 283 } 284 285 evcnt_attach_dynamic(&sc->sq_intrcnt, EVCNT_TYPE_INTR, NULL, 286 device_xname(self), "intr"); 287 288 if ((cpu_intr_establish(haa->ha_irq, IPL_NET, sq_intr, sc)) == NULL) { 289 printf(": unable to establish interrupt!\n"); 290 goto fail_6; 291 } 292 293 /* Reset the chip to a known state. */ 294 sq_reset(sc); 295 296 /* 297 * Determine if we're an 8003 or 80c03 by setting the first 298 * MAC address register to non-zero, and then reading it back. 299 * If it's zero, we have an 80c03, because we will have read 300 * the TxCollLSB register. 301 */ 302 sq_seeq_write(sc, SEEQ_TXCOLLS0, 0xa5); 303 if (sq_seeq_read(sc, SEEQ_TXCOLLS0) == 0) 304 sc->sc_type = SQ_TYPE_80C03; 305 else 306 sc->sc_type = SQ_TYPE_8003; 307 sq_seeq_write(sc, SEEQ_TXCOLLS0, 0x00); 308 309 printf(": SGI Seeq %s\n", 310 sc->sc_type == SQ_TYPE_80C03 ? "80c03" : "8003"); 311 312 printf("%s: Ethernet address %s\n", 313 device_xname(self), ether_sprintf(sc->sc_enaddr)); 314 315 strcpy(ifp->if_xname, device_xname(self)); 316 ifp->if_softc = sc; 317 ifp->if_mtu = ETHERMTU; 318 ifp->if_init = sq_init; 319 ifp->if_stop = sq_stop; 320 ifp->if_start = sq_start; 321 ifp->if_ioctl = sq_ioctl; 322 ifp->if_watchdog = sq_watchdog; 323 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST; 324 IFQ_SET_READY(&ifp->if_snd); 325 326 if_attach(ifp); 327 if_deferred_start_init(ifp, NULL); 328 ether_ifattach(ifp, sc->sc_enaddr); 329 330 memset(&sc->sq_trace, 0, sizeof(sc->sq_trace)); 331 /* Done! */ 332 return; 333 334 /* 335 * Free any resources we've allocated during the failed attach 336 * attempt. Do this in reverse order and fall through. 337 */ 338 fail_6: 339 for (i = 0; i < SQ_NRXDESC; i++) { 340 if (sc->sc_rxmbuf[i] != NULL) { 341 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmap[i]); 342 m_freem(sc->sc_rxmbuf[i]); 343 } 344 } 345 fail_5: 346 for (i = 0; i < SQ_NRXDESC; i++) { 347 if (sc->sc_rxmap[i] != NULL) 348 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmap[i]); 349 } 350 fail_4: 351 for (i = 0; i < SQ_NTXDESC; i++) { 352 if (sc->sc_txmap[i] != NULL) 353 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txmap[i]); 354 } 355 bus_dmamap_unload(sc->sc_dmat, sc->sc_cdmap); 356 fail_3: 357 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cdmap); 358 fail_2: 359 bus_dmamem_unmap(sc->sc_dmat, 360 (void *)sc->sc_control, sizeof(struct sq_control)); 361 fail_1: 362 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_ncdseg); 363 fail_0: 364 return; 365 } 366 367 /* Set up data to get the interface up and running. */ 368 int 369 sq_init(struct ifnet *ifp) 370 { 371 int i; 372 struct sq_softc *sc = ifp->if_softc; 373 374 /* Cancel any in-progress I/O */ 375 sq_stop(ifp, 0); 376 377 sc->sc_nextrx = 0; 378 379 sc->sc_nfreetx = SQ_NTXDESC; 380 sc->sc_nexttx = sc->sc_prevtx = 0; 381 382 SQ_TRACE(SQ_RESET, sc, 0, 0); 383 384 /* Set into 8003 mode, bank 0 to program ethernet address */ 385 sq_seeq_write(sc, SEEQ_TXCMD, TXCMD_BANK0); 386 387 /* Now write the address */ 388 for (i = 0; i < ETHER_ADDR_LEN; i++) 389 sq_seeq_write(sc, i, sc->sc_enaddr[i]); 390 391 sc->sc_rxcmd = 392 RXCMD_IE_CRC | 393 RXCMD_IE_DRIB | 394 RXCMD_IE_SHORT | 395 RXCMD_IE_END | 396 RXCMD_IE_GOOD; 397 398 /* 399 * Set the receive filter -- this will add some bits to the 400 * prototype RXCMD register. Do this before setting the 401 * transmit config register, since we might need to switch 402 * banks. 403 */ 404 sq_set_filter(sc); 405 406 /* Set up Seeq transmit command register */ 407 sq_seeq_write(sc, SEEQ_TXCMD, 408 TXCMD_IE_UFLOW | 409 TXCMD_IE_COLL | 410 TXCMD_IE_16COLL | 411 TXCMD_IE_GOOD); 412 413 /* Now write the receive command register. */ 414 sq_seeq_write(sc, SEEQ_RXCMD, sc->sc_rxcmd); 415 416 /* 417 * Set up HPC ethernet PIO and DMA configurations. 418 * 419 * The PROM appears to do most of this for the onboard HPC3, but 420 * not for the Challenge S's IOPLUS chip. We copy how the onboard 421 * chip is configured and assume that it's correct for both. 422 */ 423 if (sc->hpc_regs->revision == 3) { 424 uint32_t dmareg, pioreg; 425 426 pioreg = 427 HPC3_ENETR_PIOCFG_P1(1) | 428 HPC3_ENETR_PIOCFG_P2(6) | 429 HPC3_ENETR_PIOCFG_P3(1); 430 431 dmareg = 432 HPC3_ENETR_DMACFG_D1(6) | 433 HPC3_ENETR_DMACFG_D2(2) | 434 HPC3_ENETR_DMACFG_D3(0) | 435 HPC3_ENETR_DMACFG_FIX_RXDC | 436 HPC3_ENETR_DMACFG_FIX_INTR | 437 HPC3_ENETR_DMACFG_FIX_EOP | 438 HPC3_ENETR_DMACFG_TIMEOUT; 439 440 sq_hpc_write(sc, HPC3_ENETR_PIOCFG, pioreg); 441 sq_hpc_write(sc, HPC3_ENETR_DMACFG, dmareg); 442 } 443 444 /* Pass the start of the receive ring to the HPC */ 445 sq_hpc_write(sc, sc->hpc_regs->enetr_ndbp, SQ_CDRXADDR(sc, 0)); 446 447 /* And turn on the HPC ethernet receive channel */ 448 sq_hpc_write(sc, sc->hpc_regs->enetr_ctl, 449 sc->hpc_regs->enetr_ctl_active); 450 451 /* 452 * Turn off delayed receive interrupts on HPC1. 453 * (see Hollywood HPC Specification 2.1.4.3) 454 */ 455 if (sc->hpc_regs->revision != 3) 456 sq_hpc_write(sc, HPC1_ENET_INTDELAY, HPC1_ENET_INTDELAY_OFF); 457 458 ifp->if_flags |= IFF_RUNNING; 459 460 return 0; 461 } 462 463 static void 464 sq_set_filter(struct sq_softc *sc) 465 { 466 struct ethercom *ec = &sc->sc_ethercom; 467 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 468 struct ether_multi *enm; 469 struct ether_multistep step; 470 471 /* 472 * Check for promiscuous mode. Also implies 473 * all-multicast. 474 */ 475 if (ifp->if_flags & IFF_PROMISC) { 476 sc->sc_rxcmd |= RXCMD_REC_ALL; 477 ifp->if_flags |= IFF_ALLMULTI; 478 return; 479 } 480 481 /* 482 * The 8003 has no hash table. If we have any multicast 483 * addresses on the list, enable reception of all multicast 484 * frames. 485 * 486 * XXX The 80c03 has a hash table. We should use it. 487 */ 488 489 ETHER_FIRST_MULTI(step, ec, enm); 490 491 if (enm == NULL) { 492 sc->sc_rxcmd &= ~RXCMD_REC_MASK; 493 sc->sc_rxcmd |= RXCMD_REC_BROAD; 494 495 ifp->if_flags &= ~IFF_ALLMULTI; 496 return; 497 } 498 499 sc->sc_rxcmd |= RXCMD_REC_MULTI; 500 ifp->if_flags |= IFF_ALLMULTI; 501 } 502 503 int 504 sq_ioctl(struct ifnet *ifp, u_long cmd, void *data) 505 { 506 int s, error = 0; 507 508 SQ_TRACE(SQ_IOCTL, (struct sq_softc *)ifp->if_softc, 0, 0); 509 510 s = splnet(); 511 512 error = ether_ioctl(ifp, cmd, data); 513 if (error == ENETRESET) { 514 /* 515 * Multicast list has changed; set the hardware filter 516 * accordingly. 517 */ 518 if (ifp->if_flags & IFF_RUNNING) 519 error = sq_init(ifp); 520 else 521 error = 0; 522 } 523 524 splx(s); 525 return error; 526 } 527 528 void 529 sq_start(struct ifnet *ifp) 530 { 531 struct sq_softc *sc = ifp->if_softc; 532 uint32_t status; 533 struct mbuf *m0, *m; 534 bus_dmamap_t dmamap; 535 int err, totlen, nexttx, firsttx, lasttx = -1, ofree, seg; 536 537 if ((ifp->if_flags & IFF_RUNNING) == 0) 538 return; 539 540 /* 541 * Remember the previous number of free descriptors and 542 * the first descriptor we'll use. 543 */ 544 ofree = sc->sc_nfreetx; 545 firsttx = sc->sc_nexttx; 546 547 /* 548 * Loop through the send queue, setting up transmit descriptors 549 * until we drain the queue, or use up all available transmit 550 * descriptors. 551 */ 552 while (sc->sc_nfreetx != 0) { 553 /* 554 * Grab a packet off the queue. 555 */ 556 IFQ_POLL(&ifp->if_snd, m0); 557 if (m0 == NULL) 558 break; 559 m = NULL; 560 561 dmamap = sc->sc_txmap[sc->sc_nexttx]; 562 563 /* 564 * Load the DMA map. If this fails, the packet either 565 * didn't fit in the alloted number of segments, or we were 566 * short on resources. In this case, we'll copy and try 567 * again. 568 * Also copy it if we need to pad, so that we are sure there 569 * is room for the pad buffer. 570 * XXX the right way of doing this is to use a static buffer 571 * for padding and adding it to the transmit descriptor (see 572 * sys/dev/pci/if_tl.c for example). We can't do this here yet 573 * because we can't send packets with more than one fragment. 574 */ 575 if (m0->m_pkthdr.len < ETHER_PAD_LEN || 576 bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 577 BUS_DMA_NOWAIT) != 0) { 578 MGETHDR(m, M_DONTWAIT, MT_DATA); 579 if (m == NULL) { 580 printf("%s: unable to allocate Tx mbuf\n", 581 device_xname(sc->sc_dev)); 582 break; 583 } 584 if (m0->m_pkthdr.len > MHLEN) { 585 MCLGET(m, M_DONTWAIT); 586 if ((m->m_flags & M_EXT) == 0) { 587 printf("%s: unable to allocate Tx " 588 "cluster\n", 589 device_xname(sc->sc_dev)); 590 m_freem(m); 591 break; 592 } 593 } 594 595 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 596 if (m0->m_pkthdr.len < ETHER_PAD_LEN) { 597 memset(mtod(m, char *) + m0->m_pkthdr.len, 0, 598 ETHER_PAD_LEN - m0->m_pkthdr.len); 599 m->m_pkthdr.len = m->m_len = ETHER_PAD_LEN; 600 } else 601 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 602 603 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 604 m, BUS_DMA_NOWAIT)) != 0) { 605 printf("%s: unable to load Tx buffer, " 606 "error = %d\n", 607 device_xname(sc->sc_dev), err); 608 break; 609 } 610 } 611 612 /* 613 * Ensure we have enough descriptors free to describe 614 * the packet. 615 */ 616 if (dmamap->dm_nsegs > sc->sc_nfreetx) { 617 /* 618 * Not enough free descriptors to transmit this 619 * packet. We haven't committed to anything yet, 620 * so just unload the DMA map, put the packet 621 * back on the queue, and punt. 622 * 623 * XXX We could allocate an mbuf and copy, but 624 * XXX it is worth it? 625 */ 626 bus_dmamap_unload(sc->sc_dmat, dmamap); 627 if (m != NULL) 628 m_freem(m); 629 break; 630 } 631 632 IFQ_DEQUEUE(&ifp->if_snd, m0); 633 /* 634 * Pass the packet to any BPF listeners. 635 */ 636 bpf_mtap(ifp, m0, BPF_D_OUT); 637 if (m != NULL) { 638 m_freem(m0); 639 m0 = m; 640 } 641 642 /* 643 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 644 */ 645 646 SQ_TRACE(SQ_ENQUEUE, sc, sc->sc_nexttx, 0); 647 648 /* Sync the DMA map. */ 649 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 650 BUS_DMASYNC_PREWRITE); 651 652 /* 653 * Initialize the transmit descriptors. 654 */ 655 for (nexttx = sc->sc_nexttx, seg = 0, totlen = 0; 656 seg < dmamap->dm_nsegs; 657 seg++, nexttx = SQ_NEXTTX(nexttx)) { 658 if (sc->hpc_regs->revision == 3) { 659 sc->sc_txdesc[nexttx].hpc3_hdd_bufptr = 660 dmamap->dm_segs[seg].ds_addr; 661 sc->sc_txdesc[nexttx].hpc3_hdd_ctl = 662 dmamap->dm_segs[seg].ds_len; 663 } else { 664 sc->sc_txdesc[nexttx].hpc1_hdd_bufptr = 665 dmamap->dm_segs[seg].ds_addr; 666 sc->sc_txdesc[nexttx].hpc1_hdd_ctl = 667 dmamap->dm_segs[seg].ds_len; 668 } 669 sc->sc_txdesc[nexttx].hdd_descptr = 670 SQ_CDTXADDR(sc, SQ_NEXTTX(nexttx)); 671 lasttx = nexttx; 672 totlen += dmamap->dm_segs[seg].ds_len; 673 } 674 675 /* Last descriptor gets end-of-packet */ 676 KASSERT(lasttx != -1); 677 if (sc->hpc_regs->revision == 3) 678 sc->sc_txdesc[lasttx].hpc3_hdd_ctl |= 679 HPC3_HDD_CTL_EOPACKET; 680 else 681 sc->sc_txdesc[lasttx].hpc1_hdd_ctl |= 682 HPC1_HDD_CTL_EOPACKET; 683 684 SQ_DPRINTF(("%s: transmit %d-%d, len %d\n", 685 device_xname(sc->sc_dev), sc->sc_nexttx, lasttx, totlen)); 686 687 if (ifp->if_flags & IFF_DEBUG) { 688 printf(" transmit chain:\n"); 689 for (seg = sc->sc_nexttx;; seg = SQ_NEXTTX(seg)) { 690 printf(" descriptor %d:\n", seg); 691 printf(" hdd_bufptr: 0x%08x\n", 692 (sc->hpc_regs->revision == 3) ? 693 sc->sc_txdesc[seg].hpc3_hdd_bufptr : 694 sc->sc_txdesc[seg].hpc1_hdd_bufptr); 695 printf(" hdd_ctl: 0x%08x\n", 696 (sc->hpc_regs->revision == 3) ? 697 sc->sc_txdesc[seg].hpc3_hdd_ctl: 698 sc->sc_txdesc[seg].hpc1_hdd_ctl); 699 printf(" hdd_descptr: 0x%08x\n", 700 sc->sc_txdesc[seg].hdd_descptr); 701 702 if (seg == lasttx) 703 break; 704 } 705 } 706 707 /* Sync the descriptors we're using. */ 708 SQ_CDTXSYNC(sc, sc->sc_nexttx, dmamap->dm_nsegs, 709 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 710 711 /* Store a pointer to the packet so we can free it later */ 712 sc->sc_txmbuf[sc->sc_nexttx] = m0; 713 714 /* Advance the tx pointer. */ 715 sc->sc_nfreetx -= dmamap->dm_nsegs; 716 sc->sc_nexttx = nexttx; 717 } 718 719 if (sc->sc_nfreetx != ofree) { 720 SQ_DPRINTF(("%s: %d packets enqueued, first %d, INTR on %d\n", 721 device_xname(sc->sc_dev), lasttx - firsttx + 1, 722 firsttx, lasttx)); 723 724 /* 725 * Cause a transmit interrupt to happen on the 726 * last packet we enqueued, mark it as the last 727 * descriptor. 728 * 729 * HPC1_HDD_CTL_INTR will generate an interrupt on 730 * HPC1. HPC3 requires HPC3_HDD_CTL_EOPACKET in 731 * addition to HPC3_HDD_CTL_INTR to interrupt. 732 */ 733 KASSERT(lasttx != -1); 734 if (sc->hpc_regs->revision == 3) { 735 sc->sc_txdesc[lasttx].hpc3_hdd_ctl |= 736 HPC3_HDD_CTL_INTR | HPC3_HDD_CTL_EOCHAIN; 737 } else { 738 sc->sc_txdesc[lasttx].hpc1_hdd_ctl |= HPC1_HDD_CTL_INTR; 739 sc->sc_txdesc[lasttx].hpc1_hdd_bufptr |= 740 HPC1_HDD_CTL_EOCHAIN; 741 } 742 743 SQ_CDTXSYNC(sc, lasttx, 1, 744 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 745 746 /* 747 * There is a potential race condition here if the HPC 748 * DMA channel is active and we try and either update 749 * the 'next descriptor' pointer in the HPC PIO space 750 * or the 'next descriptor' pointer in a previous desc- 751 * riptor. 752 * 753 * To avoid this, if the channel is active, we rely on 754 * the transmit interrupt routine noticing that there 755 * are more packets to send and restarting the HPC DMA 756 * engine, rather than mucking with the DMA state here. 757 */ 758 status = sq_hpc_read(sc, sc->hpc_regs->enetx_ctl); 759 760 if ((status & sc->hpc_regs->enetx_ctl_active) != 0) { 761 SQ_TRACE(SQ_ADD_TO_DMA, sc, firsttx, status); 762 763 /* 764 * NB: hpc3_hdd_ctl == hpc1_hdd_bufptr, and 765 * HPC1_HDD_CTL_EOCHAIN == HPC3_HDD_CTL_EOCHAIN 766 */ 767 sc->sc_txdesc[SQ_PREVTX(firsttx)].hpc3_hdd_ctl &= 768 ~HPC3_HDD_CTL_EOCHAIN; 769 770 if (sc->hpc_regs->revision != 3) 771 sc->sc_txdesc[SQ_PREVTX(firsttx)].hpc1_hdd_ctl 772 &= ~HPC1_HDD_CTL_INTR; 773 774 SQ_CDTXSYNC(sc, SQ_PREVTX(firsttx), 1, 775 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 776 } else if (sc->hpc_regs->revision == 3) { 777 SQ_TRACE(SQ_START_DMA, sc, firsttx, status); 778 779 sq_hpc_write(sc, HPC3_ENETX_NDBP, SQ_CDTXADDR(sc, 780 firsttx)); 781 782 /* Kick DMA channel into life */ 783 sq_hpc_write(sc, HPC3_ENETX_CTL, HPC3_ENETX_CTL_ACTIVE); 784 } else { 785 /* 786 * In the HPC1 case where transmit DMA is 787 * inactive, we can either kick off if 788 * the ring was previously empty, or call 789 * our transmit interrupt handler to 790 * figure out if the ring stopped short 791 * and restart at the right place. 792 */ 793 if (ofree == SQ_NTXDESC) { 794 SQ_TRACE(SQ_START_DMA, sc, firsttx, status); 795 796 sq_hpc_write(sc, HPC1_ENETX_NDBP, 797 SQ_CDTXADDR(sc, firsttx)); 798 sq_hpc_write(sc, HPC1_ENETX_CFXBP, 799 SQ_CDTXADDR(sc, firsttx)); 800 sq_hpc_write(sc, HPC1_ENETX_CBP, 801 SQ_CDTXADDR(sc, firsttx)); 802 803 /* Kick DMA channel into life */ 804 sq_hpc_write(sc, HPC1_ENETX_CTL, 805 HPC1_ENETX_CTL_ACTIVE); 806 } else 807 sq_txring_hpc1(sc); 808 } 809 810 /* Set a watchdog timer in case the chip flakes out. */ 811 ifp->if_timer = 5; 812 } 813 } 814 815 void 816 sq_stop(struct ifnet *ifp, int disable) 817 { 818 int i; 819 struct sq_softc *sc = ifp->if_softc; 820 821 for (i = 0; i < SQ_NTXDESC; i++) { 822 if (sc->sc_txmbuf[i] != NULL) { 823 bus_dmamap_unload(sc->sc_dmat, sc->sc_txmap[i]); 824 m_freem(sc->sc_txmbuf[i]); 825 sc->sc_txmbuf[i] = NULL; 826 } 827 } 828 829 /* Clear Seeq transmit/receive command registers */ 830 sq_seeq_write(sc, SEEQ_TXCMD, 0); 831 sq_seeq_write(sc, SEEQ_RXCMD, 0); 832 833 sq_reset(sc); 834 835 ifp->if_flags &= ~IFF_RUNNING; 836 ifp->if_timer = 0; 837 } 838 839 /* Device timeout/watchdog routine. */ 840 void 841 sq_watchdog(struct ifnet *ifp) 842 { 843 uint32_t status; 844 struct sq_softc *sc = ifp->if_softc; 845 846 status = sq_hpc_read(sc, sc->hpc_regs->enetx_ctl); 847 log(LOG_ERR, "%s: device timeout (prev %d, next %d, free %d, " 848 "status %08x)\n", device_xname(sc->sc_dev), sc->sc_prevtx, 849 sc->sc_nexttx, sc->sc_nfreetx, status); 850 851 sq_trace_dump(sc); 852 853 memset(&sc->sq_trace, 0, sizeof(sc->sq_trace)); 854 sc->sq_trace_idx = 0; 855 856 if_statinc(ifp, if_oerrors); 857 858 sq_init(ifp); 859 } 860 861 static void 862 sq_trace_dump(struct sq_softc *sc) 863 { 864 int i; 865 const char *act; 866 867 for (i = 0; i < sc->sq_trace_idx; i++) { 868 switch (sc->sq_trace[i].action) { 869 case SQ_RESET: act = "SQ_RESET"; break; 870 case SQ_ADD_TO_DMA: act = "SQ_ADD_TO_DMA"; break; 871 case SQ_START_DMA: act = "SQ_START_DMA"; break; 872 case SQ_DONE_DMA: act = "SQ_DONE_DMA"; break; 873 case SQ_RESTART_DMA: act = "SQ_RESTART_DMA"; break; 874 case SQ_TXINTR_ENTER: act = "SQ_TXINTR_ENTER"; break; 875 case SQ_TXINTR_EXIT: act = "SQ_TXINTR_EXIT"; break; 876 case SQ_TXINTR_BUSY: act = "SQ_TXINTR_BUSY"; break; 877 case SQ_IOCTL: act = "SQ_IOCTL"; break; 878 case SQ_ENQUEUE: act = "SQ_ENQUEUE"; break; 879 default: act = "UNKNOWN"; 880 } 881 882 printf("%s: [%03d] action %-16s buf %03d free %03d " 883 "status %08x line %d\n", device_xname(sc->sc_dev), i, act, 884 sc->sq_trace[i].bufno, sc->sq_trace[i].freebuf, 885 sc->sq_trace[i].status, sc->sq_trace[i].line); 886 } 887 } 888 889 static int 890 sq_intr(void *arg) 891 { 892 struct sq_softc *sc = arg; 893 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 894 int handled = 0; 895 uint32_t stat; 896 897 stat = sq_hpc_read(sc, sc->hpc_regs->enetr_reset); 898 899 if ((stat & 2) == 0) 900 SQ_DPRINTF(("%s: Unexpected interrupt!\n", 901 device_xname(sc->sc_dev))); 902 else 903 sq_hpc_write(sc, sc->hpc_regs->enetr_reset, (stat | 2)); 904 905 /* 906 * If the interface isn't running, the interrupt couldn't 907 * possibly have come from us. 908 */ 909 if ((ifp->if_flags & IFF_RUNNING) == 0) 910 return 0; 911 912 sc->sq_intrcnt.ev_count++; 913 914 /* Always check for received packets */ 915 if (sq_rxintr(sc) != 0) 916 handled++; 917 918 /* Only handle transmit interrupts if we actually sent something */ 919 if (sc->sc_nfreetx < SQ_NTXDESC) { 920 sq_txintr(sc); 921 handled++; 922 } 923 924 if (handled) 925 rnd_add_uint32(&sc->rnd_source, stat); 926 return handled; 927 } 928 929 static int 930 sq_rxintr(struct sq_softc *sc) 931 { 932 int count = 0; 933 struct mbuf* m; 934 int i, framelen; 935 uint8_t pktstat; 936 uint32_t status; 937 uint32_t ctl_reg; 938 int new_end, orig_end; 939 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 940 941 for (i = sc->sc_nextrx;; i = SQ_NEXTRX(i)) { 942 SQ_CDRXSYNC(sc, i, 943 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 944 945 /* 946 * If this is a CPU-owned buffer, we're at the end of the list. 947 */ 948 if (sc->hpc_regs->revision == 3) 949 ctl_reg = 950 sc->sc_rxdesc[i].hpc3_hdd_ctl & HPC3_HDD_CTL_OWN; 951 else 952 ctl_reg = 953 sc->sc_rxdesc[i].hpc1_hdd_ctl & HPC1_HDD_CTL_OWN; 954 955 if (ctl_reg) { 956 #if defined(SQ_DEBUG) 957 uint32_t reg; 958 959 reg = sq_hpc_read(sc, sc->hpc_regs->enetr_ctl); 960 SQ_DPRINTF(("%s: rxintr: done at %d (ctl %08x)\n", 961 device_xname(sc->sc_dev), i, reg)); 962 #endif 963 break; 964 } 965 966 count++; 967 968 m = sc->sc_rxmbuf[i]; 969 framelen = m->m_ext.ext_size - 3; 970 if (sc->hpc_regs->revision == 3) 971 framelen -= 972 HPC3_HDD_CTL_BYTECNT(sc->sc_rxdesc[i].hpc3_hdd_ctl); 973 else 974 framelen -= 975 HPC1_HDD_CTL_BYTECNT(sc->sc_rxdesc[i].hpc1_hdd_ctl); 976 977 /* Now sync the actual packet data */ 978 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[i], 0, 979 sc->sc_rxmap[i]->dm_mapsize, BUS_DMASYNC_POSTREAD); 980 981 pktstat = *((uint8_t *)m->m_data + framelen + 2); 982 983 if ((pktstat & RXSTAT_GOOD) == 0) { 984 if_statinc(ifp, if_ierrors); 985 986 if (pktstat & RXSTAT_OFLOW) 987 printf("%s: receive FIFO overflow\n", 988 device_xname(sc->sc_dev)); 989 990 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[i], 0, 991 sc->sc_rxmap[i]->dm_mapsize, BUS_DMASYNC_PREREAD); 992 SQ_INIT_RXDESC(sc, i); 993 SQ_DPRINTF(("%s: sq_rxintr: buf %d no RXSTAT_GOOD\n", 994 device_xname(sc->sc_dev), i)); 995 continue; 996 } 997 998 if (sq_add_rxbuf(sc, i) != 0) { 999 if_statinc(ifp, if_ierrors); 1000 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[i], 0, 1001 sc->sc_rxmap[i]->dm_mapsize, BUS_DMASYNC_PREREAD); 1002 SQ_INIT_RXDESC(sc, i); 1003 SQ_DPRINTF(("%s: sq_rxintr: buf %d sq_add_rxbuf() " 1004 "failed\n", device_xname(sc->sc_dev), i)); 1005 continue; 1006 } 1007 1008 1009 m->m_data += 2; 1010 m_set_rcvif(m, ifp); 1011 m->m_pkthdr.len = m->m_len = framelen; 1012 1013 SQ_DPRINTF(("%s: sq_rxintr: buf %d len %d\n", 1014 device_xname(sc->sc_dev), i, framelen)); 1015 1016 if_percpuq_enqueue(ifp->if_percpuq, m); 1017 } 1018 1019 1020 /* If anything happened, move ring start/end pointers to new spot */ 1021 if (i != sc->sc_nextrx) { 1022 /* 1023 * NB: hpc3_hdd_ctl == hpc1_hdd_bufptr, and 1024 * HPC1_HDD_CTL_EOCHAIN == HPC3_HDD_CTL_EOCHAIN 1025 */ 1026 1027 new_end = SQ_PREVRX(i); 1028 sc->sc_rxdesc[new_end].hpc3_hdd_ctl |= HPC3_HDD_CTL_EOCHAIN; 1029 SQ_CDRXSYNC(sc, new_end, 1030 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1031 1032 orig_end = SQ_PREVRX(sc->sc_nextrx); 1033 sc->sc_rxdesc[orig_end].hpc3_hdd_ctl &= ~HPC3_HDD_CTL_EOCHAIN; 1034 SQ_CDRXSYNC(sc, orig_end, 1035 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1036 1037 sc->sc_nextrx = i; 1038 } 1039 1040 status = sq_hpc_read(sc, sc->hpc_regs->enetr_ctl); 1041 1042 /* If receive channel is stopped, restart it... */ 1043 if ((status & sc->hpc_regs->enetr_ctl_active) == 0) { 1044 /* Pass the start of the receive ring to the HPC */ 1045 sq_hpc_write(sc, sc->hpc_regs->enetr_ndbp, 1046 SQ_CDRXADDR(sc, sc->sc_nextrx)); 1047 1048 /* And turn on the HPC ethernet receive channel */ 1049 sq_hpc_write(sc, sc->hpc_regs->enetr_ctl, 1050 sc->hpc_regs->enetr_ctl_active); 1051 } 1052 1053 return count; 1054 } 1055 1056 static int 1057 sq_txintr(struct sq_softc *sc) 1058 { 1059 int shift = 0; 1060 uint32_t status, tmp; 1061 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1062 1063 if (sc->hpc_regs->revision != 3) 1064 shift = 16; 1065 1066 status = sq_hpc_read(sc, sc->hpc_regs->enetx_ctl) >> shift; 1067 1068 SQ_TRACE(SQ_TXINTR_ENTER, sc, sc->sc_prevtx, status); 1069 1070 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1071 tmp = (sc->hpc_regs->enetx_ctl_active >> shift) | TXSTAT_GOOD; 1072 if ((status & tmp) == 0) { 1073 if (status & TXSTAT_COLL) 1074 if_statinc_ref(nsr, if_collisions); 1075 1076 if (status & TXSTAT_UFLOW) { 1077 printf("%s: transmit underflow\n", 1078 device_xname(sc->sc_dev)); 1079 if_statinc_ref(nsr, if_oerrors); 1080 } 1081 1082 if (status & TXSTAT_16COLL) { 1083 printf("%s: max collisions reached\n", 1084 device_xname(sc->sc_dev)); 1085 if_statinc_ref(nsr, if_oerrors); 1086 if_statadd_ref(nsr, if_collisions, 16); 1087 } 1088 } 1089 IF_STAT_PUTREF(ifp); 1090 1091 /* prevtx now points to next xmit packet not yet finished */ 1092 if (sc->hpc_regs->revision == 3) 1093 sq_txring_hpc3(sc); 1094 else 1095 sq_txring_hpc1(sc); 1096 1097 /* If all packets have left the coop, cancel watchdog */ 1098 if (sc->sc_nfreetx == SQ_NTXDESC) 1099 ifp->if_timer = 0; 1100 1101 SQ_TRACE(SQ_TXINTR_EXIT, sc, sc->sc_prevtx, status); 1102 if_schedule_deferred_start(ifp); 1103 1104 return 1; 1105 } 1106 1107 /* 1108 * Reclaim used transmit descriptors and restart the transmit DMA 1109 * engine if necessary. 1110 */ 1111 static void 1112 sq_txring_hpc1(struct sq_softc *sc) 1113 { 1114 /* 1115 * HPC1 doesn't tag transmitted descriptors, however, 1116 * the NDBP register points to the next descriptor that 1117 * has not yet been processed. If DMA is not in progress, 1118 * we can safely reclaim all descriptors up to NDBP, and, 1119 * if necessary, restart DMA at NDBP. Otherwise, if DMA 1120 * is active, we can only safely reclaim up to CBP. 1121 * 1122 * For now, we'll only reclaim on inactive DMA and assume 1123 * that a sufficiently large ring keeps us out of trouble. 1124 */ 1125 uint32_t reclaimto, status; 1126 int reclaimall, i = sc->sc_prevtx; 1127 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1128 1129 status = sq_hpc_read(sc, HPC1_ENETX_CTL); 1130 if (status & HPC1_ENETX_CTL_ACTIVE) { 1131 SQ_TRACE(SQ_TXINTR_BUSY, sc, i, status); 1132 return; 1133 } else 1134 reclaimto = sq_hpc_read(sc, HPC1_ENETX_NDBP); 1135 1136 if (sc->sc_nfreetx == 0 && SQ_CDTXADDR(sc, i) == reclaimto) 1137 reclaimall = 1; 1138 else 1139 reclaimall = 0; 1140 1141 while (sc->sc_nfreetx < SQ_NTXDESC) { 1142 if (SQ_CDTXADDR(sc, i) == reclaimto && !reclaimall) 1143 break; 1144 1145 SQ_CDTXSYNC(sc, i, sc->sc_txmap[i]->dm_nsegs, 1146 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1147 1148 /* Sync the packet data, unload DMA map, free mbuf */ 1149 bus_dmamap_sync(sc->sc_dmat, sc->sc_txmap[i], 1150 0, sc->sc_txmap[i]->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1151 bus_dmamap_unload(sc->sc_dmat, sc->sc_txmap[i]); 1152 m_freem(sc->sc_txmbuf[i]); 1153 sc->sc_txmbuf[i] = NULL; 1154 1155 if_statinc(ifp, if_opackets); 1156 sc->sc_nfreetx++; 1157 1158 SQ_TRACE(SQ_DONE_DMA, sc, i, status); 1159 1160 i = SQ_NEXTTX(i); 1161 } 1162 1163 if (sc->sc_nfreetx < SQ_NTXDESC) { 1164 SQ_TRACE(SQ_RESTART_DMA, sc, i, status); 1165 1166 KASSERT(reclaimto == SQ_CDTXADDR(sc, i)); 1167 1168 sq_hpc_write(sc, HPC1_ENETX_CFXBP, reclaimto); 1169 sq_hpc_write(sc, HPC1_ENETX_CBP, reclaimto); 1170 1171 /* Kick DMA channel into life */ 1172 sq_hpc_write(sc, HPC1_ENETX_CTL, HPC1_ENETX_CTL_ACTIVE); 1173 1174 /* 1175 * Set a watchdog timer in case the chip 1176 * flakes out. 1177 */ 1178 ifp->if_timer = 5; 1179 } 1180 1181 sc->sc_prevtx = i; 1182 } 1183 1184 /* 1185 * Reclaim used transmit descriptors and restart the transmit DMA 1186 * engine if necessary. 1187 */ 1188 static void 1189 sq_txring_hpc3(struct sq_softc *sc) 1190 { 1191 /* 1192 * HPC3 tags descriptors with a bit once they've been 1193 * transmitted. We need only free each XMITDONE'd 1194 * descriptor, and restart the DMA engine if any 1195 * descriptors are left over. 1196 */ 1197 int i; 1198 uint32_t status = 0; 1199 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1200 1201 i = sc->sc_prevtx; 1202 while (sc->sc_nfreetx < SQ_NTXDESC) { 1203 /* 1204 * Check status first so we don't end up with a case of 1205 * the buffer not being finished while the DMA channel 1206 * has gone idle. 1207 */ 1208 status = sq_hpc_read(sc, HPC3_ENETX_CTL); 1209 1210 SQ_CDTXSYNC(sc, i, sc->sc_txmap[i]->dm_nsegs, 1211 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1212 1213 /* Check for used descriptor and restart DMA chain if needed */ 1214 if ((sc->sc_txdesc[i].hpc3_hdd_ctl & 1215 HPC3_HDD_CTL_XMITDONE) == 0) { 1216 if ((status & HPC3_ENETX_CTL_ACTIVE) == 0) { 1217 SQ_TRACE(SQ_RESTART_DMA, sc, i, status); 1218 1219 sq_hpc_write(sc, HPC3_ENETX_NDBP, 1220 SQ_CDTXADDR(sc, i)); 1221 1222 /* Kick DMA channel into life */ 1223 sq_hpc_write(sc, HPC3_ENETX_CTL, 1224 HPC3_ENETX_CTL_ACTIVE); 1225 1226 /* 1227 * Set a watchdog timer in case the chip 1228 * flakes out. 1229 */ 1230 ifp->if_timer = 5; 1231 } else 1232 SQ_TRACE(SQ_TXINTR_BUSY, sc, i, status); 1233 break; 1234 } 1235 1236 /* Sync the packet data, unload DMA map, free mbuf */ 1237 bus_dmamap_sync(sc->sc_dmat, sc->sc_txmap[i], 1238 0, sc->sc_txmap[i]->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1239 bus_dmamap_unload(sc->sc_dmat, sc->sc_txmap[i]); 1240 m_freem(sc->sc_txmbuf[i]); 1241 sc->sc_txmbuf[i] = NULL; 1242 1243 if_statinc(ifp, if_opackets); 1244 sc->sc_nfreetx++; 1245 1246 SQ_TRACE(SQ_DONE_DMA, sc, i, status); 1247 i = SQ_NEXTTX(i); 1248 } 1249 1250 sc->sc_prevtx = i; 1251 } 1252 1253 void 1254 sq_reset(struct sq_softc *sc) 1255 { 1256 1257 /* Stop HPC dma channels */ 1258 sq_hpc_write(sc, sc->hpc_regs->enetr_ctl, 0); 1259 sq_hpc_write(sc, sc->hpc_regs->enetx_ctl, 0); 1260 1261 sq_hpc_write(sc, sc->hpc_regs->enetr_reset, 3); 1262 delay(20); 1263 sq_hpc_write(sc, sc->hpc_regs->enetr_reset, 0); 1264 } 1265 1266 /* sq_add_rxbuf: Add a receive buffer to the indicated descriptor. */ 1267 int 1268 sq_add_rxbuf(struct sq_softc *sc, int idx) 1269 { 1270 int err; 1271 struct mbuf *m; 1272 1273 MGETHDR(m, M_DONTWAIT, MT_DATA); 1274 if (m == NULL) 1275 return ENOBUFS; 1276 1277 MCLGET(m, M_DONTWAIT); 1278 if ((m->m_flags & M_EXT) == 0) { 1279 m_freem(m); 1280 return ENOBUFS; 1281 } 1282 1283 if (sc->sc_rxmbuf[idx] != NULL) 1284 bus_dmamap_unload(sc->sc_dmat, sc->sc_rxmap[idx]); 1285 1286 sc->sc_rxmbuf[idx] = m; 1287 1288 if ((err = bus_dmamap_load(sc->sc_dmat, sc->sc_rxmap[idx], 1289 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1290 printf("%s: can't load rx DMA map %d, error = %d\n", 1291 device_xname(sc->sc_dev), idx, err); 1292 panic("sq_add_rxbuf"); /* XXX */ 1293 } 1294 1295 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap[idx], 1296 0, sc->sc_rxmap[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1297 1298 SQ_INIT_RXDESC(sc, idx); 1299 1300 return 0; 1301 } 1302 1303 void 1304 sq_dump_buffer(paddr_t addr, psize_t len) 1305 { 1306 u_int i; 1307 uint8_t *physaddr = (uint8_t *)MIPS_PHYS_TO_KSEG1(addr); 1308 1309 if (len == 0) 1310 return; 1311 1312 printf("%p: ", physaddr); 1313 1314 for (i = 0; i < len; i++) { 1315 printf("%02x ", *(physaddr + i) & 0xff); 1316 if ((i % 16) == 15 && i != len - 1) 1317 printf("\n%p: ", physaddr + i); 1318 } 1319 1320 printf("\n"); 1321 } 1322
Indexes created Thu Sep 25 16:09:42 GMT 2025