pi1ppcvar.h revision 1.6
1 /* $NetBSD: pi1ppcvar.h,v 1.6 2011/07/01 18:53:47 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Alcove - Nicolas Souchu 5 * Copyright (c) 2005 Joe Britt <britt (at) danger.com> - SGI PI1 version 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * FreeBSD: src/sys/isa/ppcreg.h,v 1.10.2.4 2001/10/02 05:21:45 nsouch Exp 30 * 31 */ 32 33 #ifndef __PI1PPCVAR_H 34 #define __PI1PPCVAR_H 35 36 #include <sys/bus.h> 37 #include <machine/types.h> 38 #include <sys/device.h> 39 #include <sys/callout.h> 40 41 #include <dev/ppbus/ppbus_conf.h> 42 43 /* Maximum time to wait for device response */ 44 #define MAXBUSYWAIT (5 * (hz)) 45 46 /* Poll interval when wating for device to become ready */ 47 #define PI1PPC_POLL ((hz)/10) 48 49 /* Diagnostic and verbose printing macros */ 50 51 #ifdef PI1PPC_DEBUG 52 extern int pi1ppc_debug; 53 #define PI1PPC_DPRINTF(arg) if(pi1ppc_debug) printf arg 54 #else 55 #define PI1PPC_DPRINTF(arg) 56 #endif 57 58 #ifdef PI1PPC_VERBOSE 59 extern int pi1ppc_verbose; 60 #define PI1PPC_VPRINTF(arg) if(pi1ppc_verbose) printf arg 61 #else 62 #define PI1PPC_VPRINTF(arg) 63 #endif 64 65 /* Flag used in DMA transfer */ 66 #define PI1PPC_DMA_MODE_READ 0x0 67 #define PI1PPC_DMA_MODE_WRITE 0x1 68 69 /* Flags passed via config */ 70 #define PI1PPC_FLAG_DISABLE_INTR 0x01 71 #define PI1PPC_FLAG_DISABLE_DMA 0x02 72 73 /* Locking for pi1ppc device */ 74 #define PI1PPC_SC_LOCK(sc) (&((sc)->sc_lock)) 75 #define PI1PPC_LOCK(sc) mutex_enter(&sc->sc_lock) 76 #define PI1PPC_UNLOCK(sc) mutex_exit(&sc->sc_lock) 77 78 /* Single softintr callback entry */ 79 struct pi1ppc_handler_node { 80 void (*func)(void *); 81 void *arg; 82 SLIST_ENTRY(pi1ppc_handler_node) entries; 83 }; 84 85 /* Generic structure to hold parallel port chipset info. */ 86 struct pi1ppc_softc { 87 /* Generic device attributes */ 88 device_t sc_dev; 89 90 kmutex_t sc_lock; 91 kcondvar_t sc_in_cv; 92 kcondvar_t sc_out_cv; 93 94 /* Machine independent bus infrastructure */ 95 bus_space_tag_t sc_iot; 96 bus_space_handle_t sc_ioh; 97 bus_dma_tag_t sc_dmat; 98 bus_dmamap_t sc_dmapt; 99 bus_size_t sc_dma_maxsize; 100 101 /* Child device */ 102 device_t child; 103 104 /* Opaque handle used for interrupt handler establishment */ 105 void *sc_ieh; 106 107 /* List of soft interrupts to call */ 108 SLIST_HEAD(handler_list, pi1ppc_handler_node) sc_handler_listhead; 109 110 /* Input buffer: working pointers, and size in bytes. */ 111 char * sc_inb; 112 char * sc_inbstart; 113 uint32_t sc_inb_nbytes; 114 int sc_inerr; 115 116 /* Output buffer pointer, working pointer, and size in bytes. */ 117 char * sc_outb; 118 char * sc_outbstart; 119 uint32_t sc_outb_nbytes; 120 int sc_outerr; 121 122 /* DMA functions: setup by bus specific attach code */ 123 int (*sc_dma_start)(struct pi1ppc_softc *, void *, u_int, uint8_t); 124 int (*sc_dma_finish)(struct pi1ppc_softc *); 125 int (*sc_dma_abort)(struct pi1ppc_softc *); 126 int (*sc_dma_malloc)(device_t, void **, bus_addr_t *, 127 bus_size_t); 128 void (*sc_dma_free)(device_t, void **, bus_addr_t *, 129 bus_size_t); 130 131 /* Microsequence related members */ 132 char * sc_ptr; /* microseq current pointer */ 133 int sc_accum; /* microseq accumulator */ 134 135 /* Device attachment state */ 136 #define PI1PPC_ATTACHED 1 137 #define PI1PPC_NOATTACH 0 138 uint8_t sc_dev_ok; 139 140 /* 141 * Hardware capabilities flags: standard mode and nibble mode are 142 * assumed to always be available since if they aren't you don't 143 * HAVE a parallel port. 144 */ 145 #define PI1PPC_HAS_INTR 0x01 /* Interrupt available */ 146 #define PI1PPC_HAS_DMA 0x02 /* DMA available */ 147 #define PI1PPC_HAS_FIFO 0x04 /* FIFO available */ 148 #define PI1PPC_HAS_PS2 0x08 /* PS2 mode capable */ 149 uint8_t sc_has; /* Chipset detected capabilities */ 150 151 /* Flags specifying mode of chipset operation . */ 152 #define PI1PPC_MODE_STD 0x01 /* Use centronics-compatible mode */ 153 #define PI1PPC_MODE_PS2 0x02 /* Use PS2 mode */ 154 #define PI1PPC_MODE_NIBBLE 0x10 /* Use nibble mode */ 155 uint8_t sc_mode; /* Current operational mode */ 156 157 /* Flags which further define chipset operation */ 158 #define PI1PPC_USE_INTR 0x01 /* Use interrupts */ 159 #define PI1PPC_USE_DMA 0x02 /* Use DMA */ 160 uint8_t sc_use; /* Capabilities to use */ 161 162 /* Parallel Port Chipset model. */ 163 #define GENERIC 6 164 uint8_t sc_model; /* chipset model */ 165 166 /* EPP mode - UNUSED */ 167 uint8_t sc_epp; 168 169 /* Parallel Port Chipset Type. Only Indy-style needed? */ 170 #define PI1PPC_TYPE_INDY 0 171 uint8_t sc_type; 172 173 /* Stored register values after an interrupt occurs */ 174 uint8_t sc_ecr_intr; 175 uint8_t sc_ctr_intr; 176 uint8_t sc_str_intr; 177 178 #define PI1PPC_IRQ_NONE 0x0 179 #define PI1PPC_IRQ_nACK 0x1 180 #define PI1PPC_IRQ_DMA 0x2 181 #define PI1PPC_IRQ_FIFO 0x4 182 #define PI1PPC_IRQ_nFAULT 0x8 183 uint8_t sc_irqstat; /* Record irq settings */ 184 185 #define PI1PPC_DMA_INIT 0x01 186 #define PI1PPC_DMA_STARTED 0x02 187 #define PI1PPC_DMA_COMPLETE 0x03 188 #define PI1PPC_DMA_INTERRUPTED 0x04 189 #define PI1PPC_DMA_ERROR 0x05 190 uint8_t sc_dmastat; /* Record dma state */ 191 192 #define PI1PPC_PWORD_MASK 0x30 193 #define PI1PPC_PWORD_16 0x00 194 #define PI1PPC_PWORD_8 0x10 195 #define PI1PPC_PWORD_32 0x20 196 uint8_t sc_pword; /* PWord size: used for FIFO DMA transfers */ 197 uint8_t sc_fifo; /* FIFO size */ 198 199 /* Indicates number of PWords in FIFO queues that generate interrupt */ 200 uint8_t sc_wthr; /* writeIntrThresold */ 201 uint8_t sc_rthr; /* readIntrThresold */ 202 }; 203 204 #ifdef _KERNEL 205 206 /* Function prototypes */ 207 208 /* Soft config attach/detach routines */ 209 void pi1ppc_sc_attach(struct pi1ppc_softc *); 210 int pi1ppc_sc_detach(struct pi1ppc_softc *, int); 211 212 /* Detection routines */ 213 int pi1ppc_detect_port(bus_space_tag_t, bus_space_handle_t); 214 215 /* Interrupt handler for pi1ppc device */ 216 int pi1ppcintr(void *); 217 218 #endif /* _KERNEL */ 219 220 #endif /* __PI1PPCVAR_H */ 221
Indexes created Thu Oct 02 07:10:07 GMT 2025